Fix race in POSIX port vPortEndScheduler (#1262)

* Fix race in POSIX port `vPortEndScheduler`

The `vPortEndScheduler` checks whether it's a FreeRTOS thread after signalling the scheduler thread to stop. This creates a race between the check and the destruction of the thread key. By moving the signal to the scheduler thread after the check, the race is prevented.

* Code review suggestions

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>

---------

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>

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.github/CODEOWNERS

@@ -4,7 +4,7 @@
 # the repo. Unless a later match takes precedence,
 # @global-owner1 and @global-owner2 will be requested for
 # review when someone opens a pull request.
-*      @FreeRTOS/pr-bar-raiser
+*      @FreeRTOS/pr-bar-raisers
 
 # Order is important; the last matching pattern takes the most
 # precedence. When someone opens a pull request that only

.github/CONTRIBUTING.md

@@ -55,7 +55,7 @@ GitHub provides additional document on [forking a repository](https://help.githu
 
 
 ## Getting your pull request merged
-All pull requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed. The time it takes to review will depend on complexity and consideration of wider implications.
+All pull requests must be approved by our review team before it can be merged in. We appreciate your patience while pull requests are reviewed. The time it takes to review will depend on complexity and consideration of wider implications. For more information on the pull request process, please see the documentation [here](pull_request_process.md).
 
 
 ## Finding contributions to work on

.github/actions/url_verifier.sh

@@ -1,65 +0,0 @@
-#!/bin/bash -
-
-PROJECT=$1
-echo "Verifying url links of: ${PROJECT}"
-if [ ! -d "$PROJECT" ]
-then
-    echo "Directory passed does not exist"
-    exit 2
-fi
-
-USER_AGENT="Mozilla/5.0 (Macintosh; Intel Mac OS X 10_14_6) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/88.0.4324.146 Safari/537.36"
-SCRIPT_RET=0
-
-set -o nounset        # Treat unset variables as an error
-
-declare -A dict
-
-function test {
-    while IFS= read -r LINE; do
-        FILE=$(echo $LINE | cut -f 1 -d ':')
-        URL=$(echo $LINE | grep -IoE '\b(https?|ftp|file)://[-A-Za-z0-9+&@#/%?=~_|!:,.;]*[-A-Za-z0-9+&@#/%=~_|]')
-
-        # remove trailing / if it exists curl diferenciate between links with
-        # and without / at the end
-        # URL=`echo "$URL" | sed 's,/$,,'`
-        dict+=(["$URL"]="$FILE ")
-    done < <(grep -e 'https\?://' ${PROJECT} -RIa --exclude='*.exe' --exclude-dir=.git | tr '*' ' ')
-
-    for UNIQ_URL in ${!dict[@]} # loop urls
-    do
-     CURL_RES=$(curl -si --user-agent "${USER_AGENT}" ${UNIQ_URL} 2>/dev/null| head -n 1 | cut -f 2 -d ' ')
-     RES=$?
-
-        echo "================================="
-        echo "Checking URL: ${UNIQ_URL}"
-
-        if [ "${CURL_RES}" == '' -o "${CURL_RES}" != '200' ]
-        then
-            if [ "${CURL_RES}" == '' ]  # curl returned an error
-            then
-                CURL_RES=$RES
-                SCRIPT_RET=1
-                echo ERROR: Result is: "${CURL_RES}"
-            elif [ "${CURL_RES}" == '403' ]
-            then
-                SCRIPT_RET=1
-                echo ERROR: Result is: "${CURL_RES}"
-            else
-                echo WARNING: Result is: "${CURL_RES}"
-            fi
-        else
-            echo SUCCESS: Result is: "${CURL_RES}"
-        fi
-        echo "================================="
-    done
-
-    if [ "${SCRIPT_RET}" -eq 0 ]
-    then
-        exit 0
-    else
-        exit 1
-    fi
-}
-
-test

.github/allowed_urls.txt

@@ -0,0 +1,3 @@
+https://www.renesas.com/us/en/document/mah/rh850f1k-group-users-manual-hardware?r=1170166
+https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rh850-automotive-mcus
+https://www.renesas.com/us/en/software-tool/c-compiler-package-rh850-family#downloads

.github/pull_request_process.md

@@ -0,0 +1,115 @@
+# Pull Request Process
+
+This document explains the stages that a Pull Request (PR) goes through when a pull request is submitted to a git repository in the FreeRTOS organization in Github. Before you start a PR, please read and familiarize yourself with [CONTRIBUTING.md](CONTRIBUTING.md)
+
+## ****Terminologies****
+
+**FreeRTOS Partner Contributors**: These are selected developers and experts from community. 
+
+**FreeRTOS Team**: The FreeRTOS team consists of “AWS employees”. 
+
+**CODEOWNERS**: For all the FreeRTOS repositories, “FreeRTOS Team” and/or “FreeRTOS Partner contributors” will be CODEOWNER.
+
+**Contributor**: The Contributor is the person who submitted the pull request.
+
+**Assignee**: The Assignee is an AWS Employee who is responsible for identifying reviewers  and managing the PR. They track the progress of pull requests and ensure that they are reviewed and merged in a timely manner. 
+
+**Reviewer**: Reviewers are responsible for reviewing pull requests and providing feedback to the contributor. Two approving reviews, one of which must be from the CODEOWNER of the reposiroty, are required for a PR to be merged. 
+
+
+## ****Pull Request Life-Cycle****
+
+Once a pull request (PR) is submitted, it goes through the following stages:
+
+1. Open
+    1. The PR is created.
+    2. All the GitHub Actions pass and the PR is ready to be reviewed. 
+2. Triage
+    1. The PR is assigned to an assignee.
+    2. The assignee assigns a reviewer from the FreeRTOS Team to the PR.
+3. Review
+    1. The reviewer provides feedback and discusses open questions with the contributor, if needed.
+    2. If the contributor and the reviewer conclude, after discussion, that the PR will not be merged, then the PR is closed.
+    3. The PR contributor addresses the feedback and makes changes to the PR, if needed.
+    4. The reviewer approves the PR and assigns a second reviewer.
+4. Second Review
+    1. The second reviewer reviews the PR and provides feedback, if needed.
+    2. The PR contributor addresses the feedback and makes changes to the PR, if needed.
+    3. The second reviewer approves the PR.
+5. Testing
+    1. One of the reviewers tests the PR to ensure that it works correctly.
+6. Ready to Merge  
+   A PR becomes Ready to Merge when all the branch protection rules are satisfied. We have branch protection rules which require the following:
+    1. At least 2 reviews. 
+    2. One review from the CODEOWNER of the given repository. 
+    3. All PR checks must pass.
+7. Merge
+    1. The PR is merged.
+
+</br>
+
+The status of a PR is indicated through GitHub labels added by Reviewers/Assignees. The following are the most common status indicators: Triaged, Reviewer Assigned, Concept ACK/NACK, First Code Review In Progress, First Code Review Complete, Second Code Review In Progress, Second Code Review Complete, Testing In Progress and Testing Complete.
+
+Please note that we may decide to skip some stages depending on the type of PR. For example, a PR with a simple doc update will likely not go through all the above stages, however every PR is required to get approvals from 2 reviewers.
+
+The pictorial representation of our PR process is shown below.
+
+![PR Process](media/pr_process.png)
+
+
+</br>
+
+## **Turnaround Times**
+
+The length of time required to review a PR is unpredictable and varies from PR to PR since it depends on the complexity of the changes, availability of reviewers, and overall workload of the team. We generally attempt to resolve each PR in accordance with the timeframes below, excluding weekends and public holidays:
+
+* Triage: < 24 hours
+* Concept ACK/NACK: 1-2 weeks
+* Code Review: 1-2 weeks
+* Testing: 1-2 weeks
+
+
+## **Addressing the changes requested by reviewers**
+
+The author should address any review comments in 4 weeks or less. If the author is unable to address the comments in that time, we will do one of the following:
+
+* Make the required changes ourselves and merge the pull request.
+* Close the pull request.
+
+</br>
+
+### **Best Practices for Faster Reviews**
+
+Here are some best practices to follow so that your PR gets reviewed quickly. 
+
+1. If you plan to contribute a new feature to FreeRTOS, please get confirmation beforehand that the FreeRTOS team and community want, and will accept, this feature. This is true especially when you plan to make large or significant changes.  To get confirmation and feedback from FreeRTOS Team and  community, create a post in the FreeRTOS forums. 
+2. Smaller is better. Small, focused PR’s are reviewed more quickly and thoroughly, are simpler to rollback, and involve less wasted effort if rejected.  Avoid opening pull requests that span the whole repository.
+3. Don’t mix refactoring, bug fixes and feature development into a single PR. Lets say you are developing feature-x  and you come across poorly named variables or incomplete/incorrect comments. You should consider fixing those, but in a separate PR, not in the same PR as feature-x. 
+4. Comments matter. The code you develop will need to be maintained for a long time. Well placed comments provide context to your reviewers, maintainers and users, and also prevent them from misunderstanding the purpose of the code.  However, DO NOT add comments to explain things which are obvious by just glancing at the code. [Good Read: https://stackoverflow.blog/2021/12/23/best-practices-for-writing-code-comments/]
+5. Test your PR. In your PR, please accompany your changes with suitable unit tests and any other tests that will be helpful, and include descriptions of how to perform any manual tests. Instructions for unit tests can be found at [freertos.org](https://freertos.org/FreeRTOS-Coding-Standard-and-Style-Guide.html#Testing) and [Github](https://github.com/FreeRTOS/FreeRTOS/blob/main/FreeRTOS/Test/CMock/Readme.md)
+
+
+**Push Back its ok:**
+Sometimes reviewers make mistakes. If a reviewer has requested you to make changes and you feel strongly about doing it a certain way, you are free to debate the merits of the requested change with the reviewer, while still following the code of conduct. You might be overruled, but you might also prevail. 
+
+**Be Pragmatic**
+Put a bit of thought into how your PR can be made easier to review and merge. No document can replace common sense and good taste. The best practices shared here and the contribution guidelines, if followed, will help you get your code reviewed and merged with less friction. 
+
+</br>
+
+### **Why is  my PR closed?** 
+
+Pull requests older than 120 days or not in-line with scope of the project will be closed. Exceptions can be made for pull requests that have active review comments, or that are awaiting other dependent pull requests. Closed pull requests are easy to recreate, and little work is lost by closing a pull request that is subsequently reopened. We want to limit the total number of pull requests in flight to:
+
+* Maintain a clean project
+* Remove old pull requests that would be difficult to rebase since the underlying code has changed over time
+* Encourage code velocity
+
+### **Why is my PR not getting reviewed/merged?**
+
+* It may be because of a feature freeze due to an upcoming release. During this time, only bug fixes are taken into consideration. If your pull request is a new feature, it will not be prioritised until after the release. Wait for the release.
+* It could be related to best practices (see contributing.md) not being followed. One common issue is that the pull request is too big to review. Let’s say you’ve touched 21 files and have 9347 insertions. When your would-be reviewers pull up the diffs, they run away - this pull request is going to take a few hours to review and they don’t have a few hours right now. They’ll get to it later, just as soon as they have more free time (ha!).
+* If you think the above two situations are not the reason, and you are not getting some pull request love,  please drop a couple of reminders on the PR comments. If everything else fails, please create a post on FreeRTOS forums with link to PR. 
+
+
+

.github/scripts/kernel_checker.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 #/*
 # * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+# * Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 # *
 # * SPDX-License-Identifier: MIT
 # *
@@ -28,6 +28,7 @@
 # */
 
 import os
+import re
 from common.header_checker import HeaderChecker
 
 #--------------------------------------------------------------------------------------------------
@@ -36,7 +37,9 @@ from common.header_checker import HeaderChecker
 KERNEL_IGNORED_FILES = [
     'FreeRTOS-openocd.c',
     'Makefile',
-    '.DS_Store'
+    '.DS_Store',
+    'cspell.config.yaml',
+    '.clang-format'
 ]
 
 KERNEL_IGNORED_EXTENSIONS = [
@@ -61,7 +64,8 @@ KERNEL_IGNORED_EXTENSIONS = [
     '.bat',
     '.sh',
     '.txt',
-    '.cmake'
+    '.cmake',
+    '.config'
 ]
 
 KERNEL_ASM_EXTENSIONS = [
@@ -87,7 +91,13 @@ KERNEL_IGNORED_PATTERNS = [
     r'.*\.git.*',
     r'.*portable/IAR/AtmelSAM7S64/.*AT91SAM7.*',
     r'.*portable/GCC/ARM7_AT91SAM7S/.*',
-    r'.*portable/MPLAB/PIC18F/stdio.h'
+    r'.*portable/MPLAB/PIC18F/stdio.h',
+    r'.*portable/ThirdParty/xClang/XCOREAI/*',
+    r'.*IAR/ARM_C*',
+    r'.*IAR/78K0R/*',
+    r'.*CCS/MSP430X/*',
+    r'.*portable/template/*',
+    r'.*template_configuration/*'
 ]
 
 KERNEL_THIRD_PARTY_PATTERNS = [
@@ -97,10 +107,19 @@ KERNEL_THIRD_PARTY_PATTERNS = [
     r'.*portable/GCC/AVR32_UC3/.*',
 ]
 
+KERNEL_ARM_COLLAB_FILES_PATTERNS = [
+    r'.*portable/ARMv8M/*',
+    r'.*portable/.*/ARM_CM23*',
+    r'.*portable/.*/ARM_CM33*',
+    r'.*portable/.*/ARM_CM35*',
+    r'.*portable/.*/ARM_CM55*',
+    r'.*portable/.*/ARM_CM85*',
+]
+
 KERNEL_HEADER = [
     '/*\n',
     ' * FreeRTOS Kernel <DEVELOPMENT BRANCH>\n',
-    ' * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n',
+    ' * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.\n',
     ' *\n',
     ' * SPDX-License-Identifier: MIT\n',
     ' *\n',
@@ -127,18 +146,95 @@ KERNEL_HEADER = [
     ' */\n',
 ]
 
+
+FREERTOS_COPYRIGHT_REGEX = r"^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$"
+
+FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX = r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright \(C\) 20\d\d Amazon.com, Inc. or its affiliates. All Rights Reserved\.( \*\/)?$)|" + \
+                                      r"(^(;|#)?( *(\/\*|\*|#|\/\/))? Copyright 20\d\d Arm Limited and/or its affiliates( \*\/)?$)|" + \
+                                      r"(^(;|#)?( *(\/\*|\*|#|\/\/))? <open-source-office@arm.com>( \*\/)?$)"
+
+
+class KernelHeaderChecker(HeaderChecker):
+    def __init__(
+        self,
+        header,
+        padding=1000,
+        ignored_files=None,
+        ignored_ext=None,
+        ignored_patterns=None,
+        py_ext=None,
+        asm_ext=None,
+        third_party_patterns=None,
+        copyright_regex = None
+    ):
+        super().__init__(header, padding, ignored_files, ignored_ext, ignored_patterns,
+                         py_ext, asm_ext, third_party_patterns, copyright_regex)
+
+        self.armCollabRegex = re.compile(FREERTOS_ARM_COLLAB_COPYRIGHT_REGEX)
+
+        self.armCollabFilesPatternList = []
+        for pattern in KERNEL_ARM_COLLAB_FILES_PATTERNS:
+            self.armCollabFilesPatternList.append(re.compile(pattern))
+
+    def isArmCollabFile(self, path):
+        for pattern in self.armCollabFilesPatternList:
+            if pattern.match(path):
+                return True
+        return False
+
+    def checkArmCollabFile(self, path):
+        isValid = False
+        file_ext = os.path.splitext(path)[-1]
+
+        with open(path, encoding="utf-8", errors="ignore") as file:
+            chunk = file.read(len("".join(self.header)) + self.padding)
+            lines = [("%s\n" % line) for line in chunk.strip().splitlines()][
+                : len(self.header) + 2
+            ]
+            if (len(lines) > 0) and (lines[0].find("#!") == 0):
+                lines.remove(lines[0])
+
+        # Split lines in sections.
+        headers = dict()
+        headers["text"] = []
+        headers["copyright"] = []
+        headers["spdx"] = []
+        for line in lines:
+            if self.armCollabRegex.match(line):
+                headers["copyright"].append(line)
+            elif "SPDX-License-Identifier:" in line:
+                headers["spdx"].append(line)
+            else:
+                headers["text"].append(line)
+
+        text_equal = self.isValidHeaderSection(file_ext, "text", headers["text"])
+        spdx_equal = self.isValidHeaderSection(file_ext, "spdx", headers["spdx"])
+
+        if text_equal and spdx_equal and len(headers["copyright"]) == 3:
+            isValid = True
+
+        return isValid
+
+    def customCheck(self, path):
+        isValid = False
+        if self.isArmCollabFile(path):
+            isValid = self.checkArmCollabFile(path)
+        return isValid
+
+
 def main():
     parser = HeaderChecker.configArgParser()
     args   = parser.parse_args()
 
     # Configure the checks then run
-    checker = HeaderChecker(KERNEL_HEADER,
-                            ignored_files=KERNEL_IGNORED_FILES,
-                            ignored_ext=KERNEL_IGNORED_EXTENSIONS,
-                            ignored_patterns=KERNEL_IGNORED_PATTERNS,
-                            third_party_patterns=KERNEL_THIRD_PARTY_PATTERNS,
-                            py_ext=KERNEL_PY_EXTENSIONS,
-                            asm_ext=KERNEL_ASM_EXTENSIONS)
+    checker = KernelHeaderChecker(KERNEL_HEADER,
+                                  copyright_regex=FREERTOS_COPYRIGHT_REGEX,
+                                  ignored_files=KERNEL_IGNORED_FILES,
+                                  ignored_ext=KERNEL_IGNORED_EXTENSIONS,
+                                  ignored_patterns=KERNEL_IGNORED_PATTERNS,
+                                  third_party_patterns=KERNEL_THIRD_PARTY_PATTERNS,
+                                  py_ext=KERNEL_PY_EXTENSIONS,
+                                  asm_ext=KERNEL_ASM_EXTENSIONS)
     checker.ignoreFile(os.path.split(__file__)[-1])
 
     rc = checker.processArgs(args)

.github/scripts/manifest_updater.py

@@ -0,0 +1,32 @@
+#!/usr/bin/env python3
+import os
+import argparse
+
+THIS_FILE_PATH = os.path.dirname(os.path.abspath(__file__))
+MANIFEST_FILE = os.path.join(THIS_FILE_PATH, '..', '..', 'manifest.yml')
+
+def update_manifest_file(new_version_number):
+    updated_lines = []
+    with open(MANIFEST_FILE, 'r') as f:
+        for line in f:
+            line = line.strip()
+            if line.startswith('version'):
+                updated_lines.append(f'version: "V{new_version_number}"\n')
+            else:
+                updated_lines.append(f'{line}\n')
+
+    with open(MANIFEST_FILE, 'w') as f:
+        f.writelines(updated_lines)
+
+def parse_args():
+    parser = argparse.ArgumentParser()
+    parser.add_argument('-v', '--version', required=True, help='New version number.')
+    args = parser.parse_args()
+    return args
+
+def main():
+    args = parse_args()
+    update_manifest_file(args.version)
+
+if __name__ == '__main__':
+    main()

.github/third_party_tools.md

@@ -0,0 +1,14 @@
+Note that these tools are provided by different vendors and not by the FreeRTOS
+team.
+
+## Tracing Tools
+| Tool | Website | Getting Started |
+|------|---------|-----------------|
+| Tracelyzer | [Link](https://percepio.com/tracealyzer/freertostrace/) | [Link](https://percepio.com/getstarted/latest/html/freertos.html) |
+| SystemView | [Link](https://www.segger.com/products/development-tools/systemview/) | [Link](https://wiki.segger.com/FreeRTOS_with_SystemView) |
+
+## Static Code Analysis Tools
+| Tool | Website | Getting Started |
+|------|---------|-----------------|
+| Code Sonar | [Link](https://codesecure.com/our-products/codesonar/) | [Link](https://github.com/CodeSecure-SE/FreeRTOS-Kernel/blob/main/examples/codesonar/README.md) |
+| Coverity | [Link](https://www.blackduck.com/static-analysis-tools-sast/coverity.html) | [Link](../examples/coverity/README.md) |

.github/workflows/auto-release.yml

@@ -31,37 +31,62 @@ jobs:
 
       # Currently FreeRTOS/.github/scripts houses the release script. Download it for upcoming usage
       - name: Checkout FreeRTOS Release Tools
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           repository: FreeRTOS/FreeRTOS
           path: tools
 
       # Simpler git auth if we use checkout action and forward the repo to release script
       - name: Checkout FreeRTOS Kernel
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           path: local_kernel
           fetch-depth: 0
 
       - name: Configure git identity
+        env:
+          ACTOR: ${{ github.actor }}
         run: |
-          git config --global user.name ${{ github.actor }}
-          git config --global user.email ${{ github.actor }}@users.noreply.github.com
+          git config --global user.name "$ACTOR"
+          git config --global user.email "$ACTOR"@users.noreply.github.com
 
       - name: create a new branch that references commit id
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
+          COMMIT_ID: ${{ github.event.inputs.commit_id }}
         working-directory: ./local_kernel
         run: |
-          git checkout -b ${{ github.event.inputs.version_number }} ${{ github.event.inputs.commit_id }}
+          git checkout -b "$VERSION_NUMBER" "$COMMIT_ID"
           echo "COMMIT_SHA_1=$(git rev-parse HEAD)" >> $GITHUB_ENV
 
       - name: Update source files with version info
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
+          MAIN_BR_VERSION_NUMBER: ${{ github.event.inputs.main_br_version }}
+          COMMIT_SHA_1: ${{ env.COMMIT_SHA_1 }}
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
         run: |
           # Install deps and run
           pip install -r ./tools/.github/scripts/release-requirements.txt
-          ./tools/.github/scripts/update_src_version.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit=${{ env.COMMIT_SHA_1 }} --new-kernel-version=${{ github.event.inputs.version_number }} --new-kernel-main-br-version=${{ github.event.inputs.main_br_version }}
+          ./tools/.github/scripts/update_src_version.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_1" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER"
           exit $?
+
+      - name : Update version number in manifest.yml
         env:
-            GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
+        working-directory: ./local_kernel
+        run: |
+          ./.github/scripts/manifest_updater.py -v "$VERSION_NUMBER"
+          exit $?
+
+      - name : Commit version number change in manifest.yml
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
+        working-directory: ./local_kernel
+        run: |
+          git add .
+          git commit -m '[AUTO][RELEASE]: Update version number in manifest.yml'
+          git push -u origin "$VERSION_NUMBER"
 
       - name: Generate SBOM
         uses: FreeRTOS/CI-CD-Github-Actions/sbom-generator@main
@@ -70,24 +95,32 @@ jobs:
           source_path: ./
 
       - name: commit SBOM file
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
         working-directory: ./local_kernel
         run: |
           git add .
-          git commit -m 'Update SBOM'
-          git push -u origin ${{ github.event.inputs.version_number }}
+          git commit -m '[AUTO][RELEASE]: Update SBOM'
+          git push -u origin "$VERSION_NUMBER"
           echo "COMMIT_SHA_2=$(git rev-parse HEAD)" >> $GITHUB_ENV
 
       - name: Release
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
+          MAIN_BR_VERSION_NUMBER: ${{ github.event.inputs.main_br_version }}
+          COMMIT_SHA_2: ${{ env.COMMIT_SHA_2 }}
+          REPO_OWNER: ${{ github.repository_owner }}
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
         run: |
           # Install deps and run
           pip install -r ./tools/.github/scripts/release-requirements.txt
-          ./tools/.github/scripts/release.py FreeRTOS --kernel-repo-path=local_kernel --kernel-commit=${{ env.COMMIT_SHA_2 }} --new-kernel-version=${{ github.event.inputs.version_number }} --new-kernel-main-br-version=${{ github.event.inputs.main_br_version }}
+          ./tools/.github/scripts/release.py "$REPO_OWNER" --kernel-repo-path=local_kernel --kernel-commit="$COMMIT_SHA_2" --new-kernel-version="$VERSION_NUMBER" --new-kernel-main-br-version="$MAIN_BR_VERSION_NUMBER"
           exit $?
-        env:
-            GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
 
       - name: Cleanup
+        env:
+          VERSION_NUMBER: ${{ github.event.inputs.version_number }}
         working-directory: ./local_kernel
         run: |
           # Delete the branch created for Tag by SBOM generator
-          git push -u origin --delete ${{ github.event.inputs.version_number }}
+          git push -u origin --delete "$VERSION_NUMBER"

.github/workflows/ci.yml

@@ -6,75 +6,46 @@ on:
     branches: [main]
   workflow_dispatch:
 jobs:
-  spell-check:
-    runs-on: ubuntu-latest
-    steps:
-      - name: Checkout Parent Repo
-        uses: actions/checkout@v2
-        with:
-          ref: main
-          repository: aws/aws-iot-device-sdk-embedded-C
-          path: main
-      - name: Clone This Repo
-        uses: actions/checkout@v2
-        with:
-            path: ./kernel
-      - name: Install spell
-        run: |
-          sudo apt-get install spell
-          sudo apt-get install util-linux
-      - name: Check spelling
-        run: |
-          PATH=$PATH:main/tools/spell
-          # Make sure that the portable directory is not included in the spellcheck.
-          sed -i 's/find $DIRNAME/find $DIRNAME -not -path '*portable*'/g' main/tools/spell/find-unknown-comment-words
-          find-unknown-comment-words --directory kernel/ --lexicon ./kernel/.github/lexicon.txt
-          if [ "$?" = "0" ]; then
-            exit 0
-          else
-            exit 1
-          fi
   formatting:
     runs-on: ubuntu-20.04
     steps:
-      - uses: actions/checkout@v2
-      - name: Install Uncrustify
-        run: sudo apt-get install uncrustify=0.69.0+dfsg1-1build1
-      - name: Run Uncrustify
-        run: |
-          uncrustify --version
-          find . portable/MemMang/* portable/Common/* \( -name portable \) -prune -false -o -iname "*.[hc]" -exec uncrustify --check -c .github/uncrustify.cfg {} +
-      - name: Check For Trailing Whitespace
-        run: |
-          set +e
-          grep --exclude="*.md" --exclude-dir=".git"  -rnI -e "[[:blank:]]$" .
-          if [ "$?" = "0" ]; then
-            echo "Files have trailing whitespace."
-            exit 1
-          else
-            exit 0
-          fi
-        shell: bash
-      - name: Check for CRLF
-        working-directory: ${{ inputs.path }}
-        run: |
-          set +e
-          find . -path ./.git -prune -o -exec file {} + |  grep "CRLF"
-          if [ "$?" = "0" ]; then
-            echo "Files have CRLF line endings."
-            exit 1
-          else
-            exit 0
-          fi
-        shell: bash
+      - uses: actions/checkout@v4.1.1
+      - name: Check Formatting of FreeRTOS-Kernel Files
+        uses: FreeRTOS/CI-CD-Github-Actions/formatting@main
+        with:
+          exclude-dirs: portable
 
-  url-check:
+  spell-check:
+      runs-on: ubuntu-latest
+      steps:
+        - name: Clone This Repo
+          uses: actions/checkout@v4.1.1
+        - name: Run spellings check
+          uses: FreeRTOS/CI-CD-Github-Actions/spellings@main
+          with:
+            path: ./
+            exclude-files: History.txt
+
+  link-verifier:
     runs-on: ubuntu-latest
     steps:
       - name: Clone This Repo
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
+      - name: Link Verification
+        uses: FreeRTOS/CI-CD-Github-Actions/link-verifier@main
         with:
-            path: ./kernel
-      - name: URL Checker
-        run: |
-            bash kernel/.github/actions/url_verifier.sh kernel
+          allowlist-file: '.github/allowed_urls.txt'
+
+  verify-manifest:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4.1.1
+        with:
+          submodules: true
+          fetch-depth: 0
+
+      - name: Run manifest verifier
+        uses: FreeRTOS/CI-CD-GitHub-Actions/manifest-verifier@main
+        with:
+          path: ./
+          fail-on-incorrect-version: true

.github/workflows/coverity_scan.yml

@@ -0,0 +1,127 @@
+name: Coverity Scan
+on:
+  # Run on every commit to mainline
+  push:
+    branches: main
+  # Allow manual running of the scan
+  workflow_dispatch:
+
+env:
+  bashPass: \033[32;1mPASSED -
+  bashInfo: \033[33;1mINFO -
+  bashFail: \033[31;1mFAILED -
+  bashEnd:  \033[0m
+
+jobs:
+  Coverity-Scan:
+    if: ( github.repository == 'FreeRTOS/FreeRTOS-Kernel' )
+    name: Coverity Scan
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout the Repository
+        uses: actions/checkout@v4.1.1
+
+      - env:
+          stepName: Install Build Essentials
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+          sudo apt-get -y update
+          sudo apt-get -y install build-essential
+
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+      - env:
+          stepName: Install Coverity Build
+          COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+          wget -nv -qO- https://scan.coverity.com/download/linux64 --post-data "token=${COVERITY_TOKEN}&project=FreeRTOS-Kernel" | tar -zx --one-top-level=cov_scan --strip-components 1
+          echo "cov_scan_path=$(pwd)/cov_scan/bin" >> $GITHUB_ENV
+
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+
+      - env:
+          stepName: Coverity Build
+          COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+          COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+          export PATH="$PATH:${{env.cov_scan_path}}"
+          cmake -S ./examples/cmake_example/ -B build
+          cd build
+          cov-build --dir cov-int make -j
+          # Move the report out of the build directory
+          tar czvf ../gcc_freertos_kernel_sample_build.tgz cov-int
+
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+
+      - env:
+          stepName: Upload Coverity Report for Scan
+          COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+          COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+          COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
+            --form email=${COVERITY_EMAIL} \
+            --form file=@gcc_freertos_kernel_sample_build.tgz \
+            --form version="Mainline" \
+            --form description="FreeRTOS Kernel Commit Scan" \
+            https://scan.coverity.com/builds?project=FreeRTOS-Kernel)
+
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+          echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}"
+
+      - env:
+            stepName: Coverity Build for SMP FreeRTOS
+            COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+            COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
+        shell: bash
+        run: |
+            # ${{ env.stepName }}
+            echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+  
+            export PATH="$PATH:${{env.cov_scan_path}}"
+            cmake -S ./examples/cmake_example/ -B build -DFREERTOS_SMP_EXAMPLE=1
+            cd build
+            cov-build --dir cov-int make -j
+            # Move the report out of the build directory
+            tar czvf ../gcc_freertos_kernel_smp_sample_build.tgz cov-int
+  
+            echo "::endgroup::"
+            echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+
+      - env:
+            stepName: Upload FreeRTOS SMP Coverity Report for Scan
+            COVERITY_TOKEN: ${{ secrets.COVERITY_SCAN_TOKEN }}
+            COVERITY_EMAIL: ${{ secrets.COVERITY_SCAN_EMAIL }}
+        shell: bash
+        run: |
+            # ${{ env.stepName }}
+            echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+  
+            COV_SCAN_UPLOAD_STATUS=$(curl --form token=${COVERITY_TOKEN} \
+              --form email=${COVERITY_EMAIL} \
+              --form file=@gcc_freertos_kernel_smp_sample_build.tgz \
+              --form version="Mainline" \
+              --form description="FreeRTOS Kernel SMP Commit Scan" \
+              https://scan.coverity.com/builds?project=FreeRTOS-Kernel)
+  
+            echo "::endgroup::"
+            echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }} "
+            echo "${COV_SCAN_UPLOAD_STATUS}" | grep -q -e 'Build successfully submitted' || echo >&2 "Error submitting build for analysis: ${COV_SCAN_UPLOAD_STATUS}"

.github/workflows/formatting.yml

@@ -0,0 +1,25 @@
+name: Format Pull Request Files
+
+on:
+  issue_comment:
+    types: [created]
+
+env:
+  bashPass: \033[32;1mPASSED -
+  bashInfo: \033[33;1mINFO -
+  bashFail: \033[31;1mFAILED -
+  bashEnd:  \033[0m
+
+jobs:
+  Formatting:
+    name: Run Formatting Check
+    if: ${{ github.event.issue.pull_request &&
+        ( ( github.event.comment.body == '/bot run uncrustify' ) ||
+          ( github.event.comment.body == '/bot run formatting' ) ) }}
+    runs-on: ubuntu-20.04
+    steps:
+    - name: Apply Formatting Fix
+      id: check-formatting
+      uses: FreeRTOS/CI-CD-Github-Actions/formatting-bot@main
+      with:
+        exclude-dirs: portable

.github/workflows/git-secrets.yml

@@ -7,11 +7,11 @@ jobs:
   git-secrets:
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4.1.1
         with:
           submodules: recursive
       - name: Checkout awslabs/git-secrets
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           repository: awslabs/git-secrets
           ref: master

.github/workflows/kernel-checks.yml

@@ -9,38 +9,61 @@ jobs:
     steps:
       # Install python 3
       - name: Tool Setup
-        uses: actions/setup-python@v2
-        with:
-          python-version: 3.7.10
-          architecture:   x64
+        uses: actions/setup-python@v3
         env:
           GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
 
       # There is shared code, hosted by FreeRTOS/FreeRTOS, with deps needed by header checker
       - name: Checkout FreeRTOS Tools
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           repository: FreeRTOS/FreeRTOS
+          sparse-checkout: '.github'
           ref:  main
           path: tools
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           path: inspect
 
       # Collect all affected files
       - name: Collecting changed files
-        uses: lots0logs/gh-action-get-changed-files@2.1.4
+        uses: lots0logs/gh-action-get-changed-files@2.2.2
         with:
           token: ${{ secrets.GITHUB_TOKEN }}
 
       # Run checks
-      - name: Check File Headers
+      - env:
+          bashPass: \033[32;1mPASSED -
+          bashInfo: \033[33;1mINFO -
+          bashFail: \033[31;1mFAILED -
+          bashEnd:  \033[0m
+          stepName: Check File Headers
+        name: ${{ env.stepName }}
+        shell: bash
         run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} Install Dependencies ${{ env.bashEnd }}"
+
+          # Copy the common tools from the FreeRTOS/FreeRTOS repo.
           mv tools/.github/scripts/common inspect/.github/scripts
+
+          # Install the necessary python dependencies
           pip install -r inspect/.github/scripts/common/requirements.txt
           cd inspect
+
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+          # Use the python script to check the copyright header of modified files.
           .github/scripts/kernel_checker.py --json ${HOME}/files_modified.json ${HOME}/files_added.json ${HOME}/files_renamed.json
-          exit $?
+          exitStatus=$?
+          echo -e "::endgroup::"
+
+          if [ $exitStatus -eq 0 ]; then
+            echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          else
+            echo -e "${{ env.bashFail }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          fi
+          exit $exitStatus

.github/workflows/kernel-demos.yml

@@ -1,13 +1,20 @@
 name: FreeRTOS-Kernel Demos
 on: [push, pull_request]
 
+env:
+  # The bash escape character is \033
+  bashPass:   \033[32;1mPASSED -
+  bashInfo:   \033[33;1mINFO -
+  bashFail:   \033[31;1mFAILED -
+  bashEnd:    \033[0m
+
 jobs:
   WIN32-MSVC:
     name: WIN32 MSVC
     runs-on: windows-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -16,7 +23,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           path: ./FreeRTOS/Source
 
@@ -36,7 +43,7 @@ jobs:
     runs-on: windows-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -45,7 +52,7 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           path: ./FreeRTOS/Source
 
@@ -58,10 +65,16 @@ jobs:
 
   POSIX-GCC:
     name: Native GCC
-    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        os:
+          - macos-latest
+          - ubuntu-latest
+    runs-on: ${{ matrix.os }}
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -70,12 +83,13 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           path: ./FreeRTOS/Source
 
       - name: Install GCC
         shell: bash
+        if: matrix.os == 'ubuntu-latest'
         run: |
           sudo apt-get -y update
           sudo apt-get -y install build-essential
@@ -85,12 +99,45 @@ jobs:
         working-directory: FreeRTOS/Demo/Posix_GCC
         run: make -j
 
+      - name: Build Posix_GCC Demo for Coverage Test
+        shell: bash
+        working-directory: FreeRTOS/Demo/Posix_GCC
+        run: make -j COVERAGE_TEST=1
+
+  CMake-Example:
+    name: CMake Example with Native GCC
+    runs-on: ubuntu-latest
+    steps:
+      # Checkout user pull request changes
+      - name: Checkout Repository
+        uses: actions/checkout@v4.1.1
+
+      - name: Install GCC
+        shell: bash
+        run: |
+          sudo apt-get -y update
+          sudo apt-get -y install build-essential
+
+      - name: Build CMake Example Demo
+        shell: bash
+        working-directory: examples/cmake_example
+        run: |
+          cmake -S . -B build
+          cmake --build build
+
+      - name: Build CMake SMP Example Demo
+        shell: bash
+        working-directory: examples/cmake_example
+        run: |
+          cmake -S . -B build -DFREERTOS_SMP_EXAMPLE=1
+          cmake --build build
+
   MSP430-GCC:
     name: GNU MSP430 Toolchain
     runs-on: ubuntu-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
@@ -99,36 +146,139 @@ jobs:
 
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           path: ./FreeRTOS/Source
 
-      - name: Install MSP430 Toolchain
+      - env:
+          stepName: Install MSP430 Toolchain
         shell: bash
         run: |
-          sudo apt-get -y update
-          sudo apt-get -y install gcc-msp430 build-essential
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          curl -L -O https://dr-download.ti.com/software-development/ide-configuration-compiler-or-debugger/MD-LlCjWuAbzH/9.3.1.2/msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
+          sudo apt update -y
+          sudo apt install -y p7zip-full
+          7z x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.7z
+          chmod +x ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run
+          sudo ./msp430-gcc-full-linux-x64-installer-9.3.1.2.run --prefix /usr/bin/msp430-gcc --mode unattended
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
 
       - name: Build msp430_GCC Demo
         shell: bash
         working-directory: FreeRTOS/Demo/msp430_GCC
-        run: make -j
+        run: make -j CC=/usr/bin/msp430-gcc/bin/msp430-elf-gcc OPT="-Os -I/usr/bin/msp430-gcc/include -L/usr/bin/msp430-gcc/include"
+
+  MicroBlaze-GCC:
+    name: GCC MicroBlaze Toolchain
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout the FreeRTOS/FreeRTOS Repository
+        uses: actions/checkout@v4.1.1
+        with:
+          ref: main
+          repository: FreeRTOS/FreeRTOS
+          fetch-depth: 1
+
+      - env:
+          stepName: Fetch Community-Supported-Demos Submodule
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos
+          # This repository contains the microblaze_instructions.h header file
+          git clone https://github.com/Xilinx/embeddedsw.git --branch xilinx_v2023.1
+          echo "::endgroup::"
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+      # Checkout user pull request changes
+      - name: Checkout Pull Request
+        uses: actions/checkout@v4.1.1
+        with:
+          path: ./FreeRTOS/Source
+
+      - env:
+          stepName: Install Dependancies
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          sudo apt update -y
+          sudo apt upgrade -y
+          sudo apt install -y build-essential m4 debhelper bison texinfo dejagnu flex
+          sudo apt install -y autogen gawk libgmp-dev libmpc-dev libmpfr-dev
+          sudo apt install -y patchutils sharutils zlib1g-dev autoconf2.64
+
+          # Download the mb-gcc toolchain from github
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/binutils-microblaze_2.35-2021-0623+1_amd64.deb;
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/gcc-microblaze_10.2.0-2021-0623+2_amd64.deb;
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-dev_3.3.0-2021-0623+3_all.deb;
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze-doc_3.3.0-2021-0623+3_all.deb;
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/libnewlib-microblaze_3.3.0-2021-0623+3_all.deb;
+          curl -L -O https://github.com/mdednev/mb-gcc/releases/download/2021-0623%2B2/newlib-source_3.3.0-2021-0623+3_all.deb;
+
+          # Install the packages for the toolchain
+          sudo apt install -y ./binutils-microblaze*.deb;
+          sudo apt install -y ./gcc-microblaze*.deb;
+          sudo apt install -y ./libnewlib-microblaze-dev*.deb;
+          sudo apt install -y ./libnewlib-microblaze-doc*.deb;
+          sudo apt install -y ./libnewlib-microblaze*.deb;
+          sudo apt install -y ./newlib-source*.deb;
+
+          # Validate that the toolchain is in the path and can be called
+          which mb-gcc
+          mb-gcc --version
+
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
+      - env:
+          stepName: Compile Microblaze Port
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          # Compile MicroBlazeV9 Port files to validate they build
+          mb-gcc -mcpu=v9.5 -c \
+            FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c \
+            FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S \
+            FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c \
+            FreeRTOS/Source/tasks.c \
+            FreeRTOS/Source/list.c \
+            -I embeddedsw/lib/bsp/standalone/src/microblaze \
+            -I FreeRTOS/Source/portable/GCC/MicroBlazeV9/ \
+            -I FreeRTOS/Source/include \
+            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src \
+            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/standalone_v5_4/src \
+            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/include \
+            -I FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/BSP/microblaze_0/libsrc/intc_v3_5/src
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
 
   ARM-GCC:
     name: GNU ARM Toolchain
     runs-on: ubuntu-latest
     steps:
       - name: Checkout the FreeRTOS/FreeRTOS Repository
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           ref: main
           repository: FreeRTOS/FreeRTOS
-          submodules: 'recursive'
           fetch-depth: 1
 
+      - env:
+          stepName: Fetch Dependencies
+        shell: bash
+        run: |
+          # ${{ env.stepName }}
+          echo -e "::group::${{ env.bashInfo }} ${{ env.stepName }} ${{ env.bashEnd }}"
+          git submodule update --checkout --init --depth 1 FreeRTOS/Demo/ThirdParty/Community-Supported-Demos FreeRTOS-Plus/Source/FreeRTOS-Plus-Trace
+          echo -e "${{ env.bashPass }} ${{ env.stepName }} ${{ env.bashEnd }}"
+
       # Checkout user pull request changes
       - name: Checkout Pull Request
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4.1.1
         with:
           path: ./FreeRTOS/Source
 
@@ -143,25 +293,21 @@ jobs:
         working-directory: FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC
         run: make -j
 
+      - name: Build CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC Demo
+        shell: bash
+        working-directory: FreeRTOS/Demo/CORTEX_MPU_R4F_TI_RM46_HERCULES_GCC
+        run: cmake -S . -B build && make -j -C build all
+
+      - name: Build CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC Demo
+        shell: bash
+        working-directory: FreeRTOS/Demo/CORTEX_MPU_R5F_TI_RM57_HERCULES_GCC
+        run: cmake -S . -B build && make -j -C build all
+
       - name: Build CORTEX_LM3S102_GCC Demo
         shell: bash
         working-directory: FreeRTOS/Demo/CORTEX_LM3S102_GCC
         run: make -j
 
-      - name: Build CORTEX_M3_MPS2_QEMU_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/CORTEX_M3_MPS2_QEMU_GCC
-        run: |
-          make clean
-          make -j
-
-      - name: Build CORTEX_M3_MPS2_QEMU_GCC Demo
-        shell: bash
-        working-directory: FreeRTOS/Demo/CORTEX_M3_MPS2_QEMU_GCC
-        run: |
-          make clean
-          make FULL_DEMO=1 -j
-
       - name: Build CORTEX_LM3S811_GCC Demo
         shell: bash
         working-directory: FreeRTOS/Demo/CORTEX_LM3S811_GCC
@@ -169,7 +315,7 @@ jobs:
 
       - name: Build CORTEX_M0+_RP2040 Demos
         shell: bash
-        working-directory: FreeRTOS/Demo/ThirdParty/Community-Supported/CORTEX_M0+_RP2040
+        working-directory: FreeRTOS/Demo/ThirdParty/Community-Supported-Demos/CORTEX_M0+_RP2040
         run: |
           git clone https://github.com/raspberrypi/pico-sdk.git
           cmake -B build -DPICO_SDK_PATH=pico-sdk -GNinja

.github/workflows/unit-tests.yml

@@ -6,7 +6,7 @@ jobs:
     runs-on: ubuntu-20.04
     steps:
     - name: Checkout Parent Repository
-      uses: actions/checkout@v2
+      uses: actions/checkout@v4.1.1
       with:
         ref: main
         repository: FreeRTOS/FreeRTOS
@@ -15,7 +15,7 @@ jobs:
 
     # Checkout user pull request changes
     - name: Checkout Pull Request
-      uses: actions/checkout@v2
+      uses: actions/checkout@v4.1.1
       with:
         path: ./FreeRTOS/Source
 
@@ -45,12 +45,12 @@ jobs:
         fail_ci_if_error: false
         verbose: false
     - name: Archive code coverage data
-      uses: actions/upload-artifact@v2
+      uses: actions/upload-artifact@v4
       with:
         name: coverage-data
         path: FreeRTOS/Test/CMock/build/cmock_test*
     - name: Archive code coverage html report
-      uses: actions/upload-artifact@v2
+      uses: actions/upload-artifact@v4
       with:
         name: coverage-report
         path: FreeRTOS/Test/CMock/build/coverage

CMakeLists.txt

@@ -4,14 +4,16 @@ cmake_minimum_required(VERSION 3.15)
 #   FREERTOS_PORT, if not specified and native port detected, uses the native compile.
 #
 # User is responsible for one library target:
-#   freertos_config ,typcially an INTERFACE library
+#   freertos_config ,typically an INTERFACE library
 #
 # DEPRECATED: FREERTOS_CONFIG_FILE_DIRECTORY - but still supported if no freertos_config defined for now.
 #             May be removed at some point in the future.
+#
 # User can choose which heap implementation to use (either the implementations
-# included with FreeRTOS [1..5] or a custom implementation ) by providing the
-# option FREERTOS_HEAP. If the option is not set, the cmake will default to
-# using heap_4.c.
+# included with FreeRTOS [1..5] or a custom implementation) by providing the
+# option FREERTOS_HEAP. When dynamic allocation is used, the user must specify a
+# heap implementation. If the option is not set, the cmake will use no heap
+# implementation (e.g. when only static allocation is used).
 
 # `freertos_config` target defines the path to FreeRTOSConfig.h and optionally other freertos based config files
 if(NOT TARGET freertos_config )
@@ -37,9 +39,6 @@ if(NOT TARGET freertos_config )
     endif()
 endif()
 
-# Heap number or absolute path to custom heap implementation provided by user
-set(FREERTOS_HEAP "4" CACHE STRING "FreeRTOS heap model number. 1 .. 5. Or absolute path to custom heap source file")
-
 # FreeRTOS port option
 if(NOT FREERTOS_PORT)
     message(WARNING " FREERTOS_PORT is not set. Please specify it from top-level CMake file (example):\n"
@@ -59,8 +58,8 @@ if(NOT FREERTOS_PORT)
         " CODEWARRIOR_COLDFIRE_V2          - Compiler: CoreWarrior   Target: ColdFire V2\n"
         " CODEWARRIOR_HCS12                - Compiler: CoreWarrior   Target: HCS12\n"
         " GCC_ARM_CA9                      - Compiler: GCC           Target: ARM Cortex-A9\n"
-        " GCC_ARM_CA53_64_BIT              - Compiler: GCC           Target: ARM Cortex-A53 64 bit\n"
-        " GCC_ARM_CA53_64_BIT_SRE          - Compiler: GCC           Target: ARM Cortex-A53 64 bit SRE\n"
+        " GCC_ARM_AARCH64                  - Compiler: GCC           Target: ARM v8-A\n"
+        " GCC_ARM_AARCH64_SRE              - Compiler: GCC           Target: ARM v8-A SRE\n"
         " GCC_ARM_CM0                      - Compiler: GCC           Target: ARM Cortex-M0\n"
         " GCC_ARM_CM3                      - Compiler: GCC           Target: ARM Cortex-M3\n"
         " GCC_ARM_CM3_MPU                  - Compiler: GCC           Target: ARM Cortex-M3 with MPU\n"
@@ -86,6 +85,7 @@ if(NOT FREERTOS_PORT)
         " GCC_ARM_CM85_NTZ_NONSECURE       - Compiler: GCC           Target: ARM Cortex-M85 non-trustzone non-secure\n"
         " GCC_ARM_CM85_TFM                 - Compiler: GCC           Target: ARM Cortex-M85 non-secure for TF-M\n"
         " GCC_ARM_CR5                      - Compiler: GCC           Target: ARM Cortex-R5\n"
+        " GCC_ARM_CRX_MPU                  - Compiler: GCC           Target: ARM Cortex-Rx with MPU\n"
         " GCC_ARM_CRX_NOGIC                - Compiler: GCC           Target: ARM Cortex-Rx no GIC\n"
         " GCC_ARM7_AT91FR40008             - Compiler: GCC           Target: ARM7 Atmel AT91R40008\n"
         " GCC_ARM7_AT91SAM7S               - Compiler: GCC           Target: ARM7 Atmel AT91SAM7S\n"
@@ -107,6 +107,7 @@ if(NOT FREERTOS_PORT)
         " GCC_PPC440_XILINX                - Compiler: GCC           Target: Xilinx PPC440\n"
         " GCC_RISC_V                       - Compiler: GCC           Target: RISC-V\n"
         " GCC_RISC_V_PULPINO_VEGA_RV32M1RM - Compiler: GCC           Target: RISC-V Pulpino Vega RV32M1RM\n"
+        " GCC_RISC_V_GENERIC               - Compiler: GCC           Target: RISC-V with FREERTOS_RISCV_EXTENSION\n"
         " GCC_RL78                         - Compiler: GCC           Target: Renesas RL78\n"
         " GCC_RX100                        - Compiler: GCC           Target: Renesas RX100\n"
         " GCC_RX200                        - Compiler: GCC           Target: Renesas RX200\n"
@@ -137,15 +138,18 @@ if(NOT FREERTOS_PORT)
         " IAR_ARM_CM33_NONSECURE           - Compiler: IAR           Target: ARM Cortex-M33 non-secure\n"
         " IAR_ARM_CM33_SECURE              - Compiler: IAR           Target: ARM Cortex-M33 secure\n"
         " IAR_ARM_CM33_NTZ_NONSECURE       - Compiler: IAR           Target: ARM Cortex-M33 non-trustzone non-secure\n"
+        " IAR_ARM_CM33_TFM                 - Compiler: IAR           Target: ARM Cortex-M33 non-secure for TF-M\n"
         " IAR_ARM_CM35P_NONSECURE          - Compiler: IAR           Target: ARM Cortex-M35P non-secure\n"
         " IAR_ARM_CM35P_SECURE             - Compiler: IAR           Target: ARM Cortex-M35P secure\n"
         " IAR_ARM_CM35P_NTZ_NONSECURE      - Compiler: IAR           Target: ARM Cortex-M35P non-trustzone non-secure\n"
         " IAR_ARM_CM55_NONSECURE           - Compiler: IAR           Target: ARM Cortex-M55 non-secure\n"
         " IAR_ARM_CM55_SECURE              - Compiler: IAR           Target: ARM Cortex-M55 secure\n"
         " IAR_ARM_CM55_NTZ_NONSECURE       - Compiler: IAR           Target: ARM Cortex-M55 non-trustzone non-secure\n"
+        " IAR_ARM_CM55_TFM                 - Compiler: IAR           Target: ARM Cortex-M55 non-secure for TF-M\n"
         " IAR_ARM_CM85_NONSECURE           - Compiler: IAR           Target: ARM Cortex-M85 non-secure\n"
         " IAR_ARM_CM85_SECURE              - Compiler: IAR           Target: ARM Cortex-M85 secure\n"
         " IAR_ARM_CM85_NTZ_NONSECURE       - Compiler: IAR           Target: ARM Cortex-M85 non-trustzone non-secure\n"
+        " IAR_ARM_CM85_TFM                 - Compiler: IAR           Target: ARM Cortex-M85 non-secure for TF-M\n"
         " IAR_ARM_CRX_NOGIC                - Compiler: IAR           Target: ARM Cortex-Rx no GIC\n"
         " IAR_ATMEGA323                    - Compiler: IAR           Target: ATMega323\n"
         " IAR_ATMEL_SAM7S64                - Compiler: IAR           Target: Atmel SAM7S64\n"
@@ -157,6 +161,7 @@ if(NOT FREERTOS_PORT)
         " IAR_MSP430                       - Compiler: IAR           Target: MSP430\n"
         " IAR_MSP430X                      - Compiler: IAR           Target: MSP430X\n"
         " IAR_RISC_V                       - Compiler: IAR           Target: RISC-V\n"
+        " IAR_RISC_V_GENERIC               - Compiler: IAR           Target: RISC-V with FREERTOS_RISCV_EXTENSION\n"
         " IAR_RL78                         - Compiler: IAR           Target: Renesas RL78\n"
         " IAR_RX100                        - Compiler: IAR           Target: Renesas RX100\n"
         " IAR_RX600                        - Compiler: IAR           Target: Renesas RX600\n"
@@ -196,6 +201,7 @@ if(NOT FREERTOS_PORT)
         " SOFTUNE_MB91460                  - Compiler: Softune       Target: MB91460\n"
         " SOFTUNE_MB96340                  - Compiler: Softune       Target: MB96340\n"
         " TASKING_ARM_CM4F                 - Compiler: Tasking       Target: ARM Cortex-M4 with FPU\n"
+        " TEMPLATE                         - Compiler: HOST          Target: None\n"
         " CDK_THEAD_CK802                  - Compiler: CDK           Target: T-head CK802\n"
         " XCC_XTENSA                       - Compiler: XCC           Target: Xtensa\n"
         " WIZC_PIC18                       - Compiler: WizC          Target: PIC18")
@@ -215,59 +221,27 @@ elseif((FREERTOS_PORT STREQUAL "A_CUSTOM_PORT") AND (NOT TARGET freertos_kernel_
     "    port.c\n"
     "    portmacro.h\n"
     " Where FreeRTOSCustomPort/CMakeLists.txt is a modified version of:\n"
-    "   add_library(freertos_kernel_port STATIC)\n"
+    "   add_library(freertos_kernel_port OBJECT)\n"
     "   target_sources(freertos_kernel_port\n"
     "     PRIVATE\n"
     "       port.c\n"
     "       portmacro.h)\n"
-    "   target_include_directories(freertos_kernel_port\n"
-    "     PUBLIC\n"
+    "   add_library(freertos_kernel_port_headers INTERFACE)\n"
+    "     target_include_directories(freertos_kernel_port_headers INTERFACE \n"
     "      .)\n"
     "   target_link_libraries(freertos_kernel_port\n"
     "     PRIVATE\n"
+    "       freertos_kernel_port_headers\n"
     "       freertos_kernel_include)")
 endif()
 
-########################################################################
-# Overall Compile Options
-# Note the compile option strategy is to error on everything and then
-# Per library opt-out of things that are warnings/errors.
-# This ensures that no matter what strategy for compilation you take, the
-# builds will still occur.
-#
-# Only tested with GNU and Clang.
-# Other options are https://cmake.org/cmake/help/latest/variable/CMAKE_LANG_COMPILER_ID.html#variable:CMAKE_%3CLANG%3E_COMPILER_ID
-# Naming of compilers translation map:
-#
-#   FreeRTOS    | CMake
-#   -------------------
-#   CCS         | ?TBD?
-#   GCC         | GNU, Clang, *Clang Others?
-#   IAR         | IAR
-#   Keil        | ARMCC
-#   MSVC        | MSVC # Note only for MinGW?
-#   Renesas     | ?TBD?
-
-add_compile_options(
-    ### Gnu/Clang C Options
-    $<$<COMPILE_LANG_AND_ID:C,GNU>:-fdiagnostics-color=always>
-    $<$<COMPILE_LANG_AND_ID:C,Clang>:-fcolor-diagnostics>
-
-    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wall>
-    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wextra>
-    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wpedantic>
-    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Werror>
-    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Weverything>
-
-    # TODO: Add in other Compilers here.
-)
-
+add_library(freertos_kernel STATIC)
 
 ########################################################################
 add_subdirectory(include)
 add_subdirectory(portable)
 
-add_library(freertos_kernel STATIC
+target_sources(freertos_kernel PRIVATE
     croutine.c
     event_groups.c
     list.c
@@ -275,15 +249,24 @@ add_library(freertos_kernel STATIC
     stream_buffer.c
     tasks.c
     timers.c
-
-    # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file
-    $<IF:$<BOOL:$<FILTER:${FREERTOS_HEAP},EXCLUDE,^[1-5]$>>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c>
 )
 
+if (DEFINED FREERTOS_HEAP )
+    # User specified a heap implementation add heap implementation to freertos_kernel.
+    target_sources(freertos_kernel PRIVATE
+        # If FREERTOS_HEAP is digit between 1 .. 5 - it is heap number, otherwise - it is path to custom heap source file
+        $<IF:$<BOOL:$<FILTER:${FREERTOS_HEAP},EXCLUDE,^[1-5]$>>,${FREERTOS_HEAP},portable/MemMang/heap_${FREERTOS_HEAP}.c>
+    )
+endif()
+
+
 target_link_libraries(freertos_kernel
     PUBLIC
-        freertos_kernel_port
         freertos_kernel_include
+        freertos_kernel_port_headers
+    PRIVATE
+        freertos_kernel_port
+
 )
 
 ########################################################################

History.txt

@@ -1,5 +1,335 @@
 Documentation and download available at https://www.FreeRTOS.org/
 
+Changes between FreeRTOS V11.1.0 and FreeRTOS V11.2.0 released March 04, 2025
+
+    + Add CC-RH port for Renesas F1Kx devices. We thank @TrongNguyenR for their
+      contribution.
+    + Add Pointer Authentication (PAC) and Branch Target Identification (BTI)
+      support to the ARMv8-M ports. We thank @AhmedIsmail02 for their
+      contribution.
+    + Add Floating Point Unit (FPU) support to the ARM_AARCH64 port. We thank
+      @StefanBalt for their contribution.
+    + Add FPU Safe Application IRQ Handler suport to the ARM_AARCH64_SRE port.
+      We thank @GhMarwen for their contribution.
+    + Add Privileged eXecute Never MPU attribute support to the ARMv8-M ports.
+      We thank @AhmedIsmail02 for their contribution.
+    + Update XMOS xcore.ai port to be compatible with FreeRTOS Kernel version
+      11. We thank @ACascarino for their contribution.
+    + ARM_CRx_No_GIC port updates:
+      - Remove inline assembly and move assembly code to separate portASM.S
+        file.
+      - Add support for Floating Point Unit (FPU).
+      - Add support to allow the application writer to handle SVC calls raised
+        from the application code.
+      - Add support for vApplicationFPUSafeIRQHandler.
+    + POSIX port updates:
+      - Set PTHREAD_MUTEX_ROBUST attribute on the mutex to prevent application
+        hangs when a thread dies while holding a mutex.
+      - Avoid calling pthread_sigmask on non-FreeROS threads when
+        vPortEndScheduler is called from a non-FreeRTOS thread. We thank
+        @johnboiles for their contribution.
+      - Remove unnecessary call to pthread_attr_setstacksize. We thank
+        @hollinsky for their contribution.
+      - Add an assert to catch if vPortYield is called from a non-FreeRTOS
+        thread. We thank @johnboiles for their contribution.
+      - Fix Posix port compilation on FreeBSD. We thank @tymmej for their
+        contribution.
+    + Update the Xtensa port and move it to the Partner-Supported-Ports
+      repository. We thank @ianstcdns for their contribution.
+    + Add vPortGenerateSimulatedInterruptFromWindowsThread API in the MSVC-MingW
+      port to enable native windows thread to synchronize with FreeRTOS task
+      through simulated interrupt.
+    + Update Windows port to use Waitable Timer instead of Sleep to improve tick
+      accuracy. We thank @bknicholls and @leegeth for their contribution.
+    + Update the value of queueQUEUE_TYPE_SET to a unique value (5) to allow
+      tracers to differentiate between queues and queue sets. We thank @schilkp
+      for their contribution.
+    + Add traceSTARTING_SCHEDULER tracing hook to enable tracers to run code on
+      startup. We thank @schilkp for their contribution.
+    + Define vApplicationGetTimerTaskMemory only when configUSE_TIMERS is set to
+      1. We thank @HazardyKnusperkeks for their contribution.
+    + Reset xNextTaskUnblockTime in task notify FromISR APIs to allow the core
+      to enter sleep mode at the earliest possible time when using tickless
+      idle.
+    + Optimize xTaskIncrementTick for SMP by removing xYieldRequiredForCore. We
+      thank @cymizer for their contribution.
+    + Update the SMP scheduler to re-select a core to yield when the core
+      affinity of a ready task is changed.
+    + Update xEventGroupSetBits to read the event bits value to be returned to
+      the caller while the scheduler is suspended. This fixes dereference after
+      the event group is deleted by higher priority task. We thank @skotopes for
+      their contribution.
+    + Optimize certain getter APIs by removing unnecessary calls to
+      task{ENTER|EXIT}_CRITICAL() when the data access is atomic. We thank
+      @GuilhermeGiacomoSimoes for their contribution.
+    + Optimize xTaskNotifyWait and ulTaskNotifyTake APIs to suspend the
+      scheduler only if the task is not already notified, and the caller is
+      willing to wait for the notification. We thank @jefftenney for
+      their contribution.
+    + Fix error checking of prvCreateIdleTasks. We thank @kakkoko for their
+      contribution.
+    + Update SMP lock macros and critical nesting macros to pass core ID as an
+      argument. This reduces the number of accesses to a peripheral register to
+      query core ID. We thank @felixvanoost for their contribution.
+    + Add stack pointer bounds check when configCHECK_FOR_STACK_OVERFLOW is set
+      to 2 to improve reliability of stack overflow detection. We thank
+      @jiladahe1997 for their contribution.
+    + Update run-time stats to include time elapsed since the last context
+      switch for the currently running task.
+    + Add xQueueCreateSetStatic API for static creation of Queue Sets. We thank
+      @kzorer for their contribution.
+    + Update the traceMALLOC() macro to pass the actual size of the allocated
+      block for secure_heap, heap_2, heap_4 and heap_5. We thank @DazzlingOkami
+      for their contribution.
+    + Update heap_1 to use heapADD_WILL_OVERFLOW macro to improve readability.
+      We thank @wdfk-prog for their contribution.
+    + Add pointer protection to the pxNextFreeBlock member of the allocated
+      block's metadata in heap_4 and heap_5 when configENABLE_HEAP_PROTECTOR is
+      set to 1. We thank @Saiiijchan for their contribution.
+    + Allow the application writer to override pointer validation for heap_5
+      when configENABLE_HEAP_PROTECTOR is used. We thank @Saiiijchan for their
+      contribution.
+    + Add xPortResetHeapMinimumEverFreeHeapSize to heap_4.c and heap_5.c.
+      We thank @TomasGalbickaNXP for their contribution.
+    + Add NULL check in the event_create function in the POSIX port. We thank
+      @laroche for their contribution.
+    + Use _GNU_SOURCE macro instead of __USE_GNU in the Posix port. We thank
+      @maxiaogood for their contribution.
+    + Use the new __ARM_FP macro instead of the deprectred __VFP_FP__ macro in
+      GCC/ARM_CM7, GCC/ARM_CM4_MPU, and GCC/ARM_CM4F ports. We thank @haydenridd
+      for their contribution.
+    + Add portMEMORY_BARRIER definition to the Xtensa port. We thank @superroc
+      for their contribution.
+    + Move the hardware include msp430.h to port.c from portmacro.h. We thank
+      @mayl for their contribution.
+    + Update ARM assembly syntax for Cortex-M ports. We thank @laroche for their
+      contribution.
+    + Update the Windows port to records a pending yield in
+      vPortCloseRunningThread to ensure that the next tick interrupt schedules
+      the next task regardless of the value of configUSE_PREEMPTION.
+    + Fix the context switch issue in the RL78 port. We thank @KeitaKashima for
+      their contribution.
+    + Fix compilation issue in ARM CM0 port when using Keil MDK. We thank
+      @TomasGalbickaNXP for their contribution.
+    + Fix IA32 port compilation when configUSE_COMMON_INTERRUPT_ENTRY_POINT is
+      set to 0. We thank @Ryzee119 for their contribution.
+    + Store configMTIMECMP_BASE_ADDRESS in a 64-bit integer for the RISC-V port.
+      We thank @vishwamartur for their contribution.
+    + Fix nested interrupt handling and optimize FPU related context switching
+      for the F1Kx port. We thank @TrongNguyenR for their contribution.
+    + Update the RP2040 port to add support for Raspberry Pi Pico SDK 2.0.0.
+      We thank @kilograham for their contribution.
+    + Fix the return value of portYIELD_FROM_ISR macro for the MSVC-MingW port.
+      We thank @wwhheerree for their contribution.
+    + Optimize vApplicationFPUSafeIRQHandler for the Coretex-A9 port by
+      removing the unnecessarily preserved callee saved registers. We thank
+      @Saiiijchan for their contribution.
+    + Fix the context array size for MPU ports to ensure the saved context
+      location falls within the reserved context area rather than overlapping
+      with the next MPU_SETTINGS structure member.
+    + Update CMake files for RP2040 port to fetch the port from the
+      Community-Supported-Ports repo. We thank @kilograham for their
+      contribution.
+    + Fix CMake file for the GCC ARM_CM0 port to include MPU files. We thank
+      @0mhu for their contribution.
+    + Add an example of human readable table generated by vTaskListTasks() in
+      the function documentation. We thank @wwhheerree for their contribution.
+
+Changes between FreeRTOS V11.0.1 and FreeRTOS V11.1.0 released April 22, 2024
+
+    + Add ARMv7-R port with Memory Protection Unit (MPU) support.
+    + Add Memory Protection Unit (MPU) support to the Cortex-M0 port.
+    + Add stream batching buffer. A stream batching buffer differs from a stream
+      buffer when a task reads from a non-empty buffer:
+      - The task reading from a non-empty stream buffer returns immediately
+        regardless of the amount of data in the buffer.
+      - The task reading from a non-empty steam batching buffer blocks until the
+        amount of data in the buffer exceeds the trigger level or the block time
+        expires.
+      We thank @cperkulator for their contribution.
+    + Add the ability to change task notification index for stream buffers. We
+      thank @glemco for their contribution.
+    + Add xStreamBufferResetFromISR and xMessageBufferResetFromISR APIs to reset
+      stream buffer and message buffer from an Interrupt Service Routine (ISR).
+      We thank @HagaiMoshe for their contribution.
+    + Update all the FreeRTOS APIs to use configSTACK_DEPTH_TYPE for stack type.
+      We thank @feilipu for their contribution.
+    + Update vTaskEndScheduler to delete the timer and idle tasks,
+      once the scheduler is stopped.
+    + Make xTaskGetCurrentTaskHandleForCore() available to the single core
+      scheduler. We thank @Dazza0 for their contribution.
+    + Update uxTaskGetSystemState to not use the pxIndex member of the List_t
+      structure while iterating ready tasks list. The reason is that pxIndex
+      member must only used to select next ready task to run. We thank
+      @gemarcano for their inputs.
+    + Add a config option to the FreeRTOS SMP Kernel to set the default core
+      affinity mask for tasks created without an affinity mask. We thank @go2sh
+      for their contribution.
+    + Add configUSE_EVENT_GROUPS and configUSE_STREAM_BUFFERS configuration
+      constants to control the inclusion of event group and stream buffer
+      functionalities.
+    + Code changes to comply with MISRA C 2012.
+    + Add 64-bit support to the FreeRTOS Windows Simulator port. We thank @watsk
+      and @josesimoes for their contributions.
+    + Add support for 64-bit Microblaze processor to the MicroblazeV9 port. We
+      thank @mubinsyed for their contribution.
+    + Add support for MSP430 Embedded Application Binary Interface (EABI) to
+      the MSP430F449 port to make it work with both MSP430 GCC and MSPGCC
+      compilers. We thank @Forty-Bot for their contribution.
+    + Update xPortIsAuthorizedToAccessBuffer() on FreeRTOS ports with MPU
+      support to grant an unprivileged task access to all the memory before the
+      scheduler is started.
+    + Update the POSIX port to pass the FreeRTOS task name to pthread for
+      readable output in debuggers. We thank @Mixaill for their contribution.
+    + Update the POSIX port to ignore the user specified stack memory and only
+      pass the stack size to the pthread API to avoid errors caused when stack size
+      is smaller than the minimum. We thank @cmorgnaBE for their
+      contribution.
+    + Update the POSIX port to use a timer thread for tick interrupts instead of
+      POSIX timers to address issues with signal handling in non-FreeRTOS
+      pthreads. We thank @cmorgnaBE for their contribution.
+    + Update ARM_TFM port to support TF-Mv2.0.0 release of trusted-firmware-m.
+      We thanks @urutva for their contribution.
+    + Remove redundant constant pools in ARMv8 ports. We thank @urutva for their
+      contribution.
+    + Add APIs to reset the internal state of kernel modules. These APIs are
+      primarily intended to be used in the testing frameworks that restart the
+      scheduler.
+    + Use kernel provided implementations of vApplicationGetIdleTaskMemory() and
+      vApplicationGetTimerTaskMemory() in the RP2040 port. We thank @dpslwk for
+      their contribution.
+    + Fix atomic enter/exit critical section macro definitions in atomic.h for
+      ports that support nested interrupts. We thank @sebunger for their
+      contribution.
+    + Fix compiler warnings in the MSP430F449 port when compiled with the
+      MSP430 GCC compiler. We thank @Forty-Bot for their contribution.
+    + Update the scheduler suspension usage in ulTaskGenericNotifyTake and
+      xTaskGenericNotifyWait() to enhance code readability. We thank @Dazza0 for
+      their contribution.
+    + Add support for latest version of MPU wrappers( mpu_wrappers_v2) in CMake.
+      We thank @IsaacDynamo for their contribution.
+    + Update CMake support to create only one static library containing both the
+      kernel common code and the kernel port code. We thank @barnatahmed for
+      their contribution.
+
+Changes between FreeRTOS V11.0.0 and FreeRTOS V11.0.1 released December 21, 2023
+
+    + Updated the SBOM file.
+
+Changes between FreeRTOS V10.6.2 and FreeRTOS V11.0.0 released December 18, 2023
+
+    + SMP merged into the mainline:  While FreeRTOS introduced Asymmetric
+      Multiprocessing (AMP) support in 2017, FreeRTOS Version 11.0.0 is the
+      first to merge Symmetric Multiprocessing (SMP) support into the mainline
+      release. SMP enables one instance of the FreeRTOS Kernel to schedule tasks
+      across multiple identical processor cores.  We thank Mike Bruno and Jerry
+      McCarthy of XMOS and, Darian Liang, Sudeep Mohanty and Zim Kalinowski of
+      Espressif Systems for their contributions.
+    + Switch MISRA compliance checking from PC Lint to Coverity, and update from
+      MISRA C:2004 to MISRA C:2012.
+    + Add a template FreeRTOSConfig.h, inclusive of an abbreviated explanation of
+      each configuration item. Application writers can use this template as a
+      starting point to create the FreeRTOSConfig.h file for their application.
+    + Add a template FreeRTOS port which can be used as a starting point for
+      developing a new FreeRTOS port.
+    + Add bounds checking and obfuscation to internal heap block pointers in
+      heap_4.c and heap_5.c to help catch pointer corruptions. The application can
+      enable these checks by setting configENABLE_HEAP_PROTECTOR to 1 in their
+      FreeRTOSConfig.h. We thank @oliverlavery for their contribution.
+    + Update vTaskList and vTaskGetRunTimeStats APIs to replace the use of sprintf
+      with snprintf.
+    + Add trace macros to ports that enable tracing the interaction of ISRs with
+      scheduler events. We thank @conara for their contribution.
+    + Add trace macros that enable tracing of entering and exiting all APIs. We
+      thank @Techcore123 for their contribution.
+    + Add uxTaskBasePriorityGet and uxTaskBasePriorityGetFromISR APIs to get the
+      base priority of a task. The base priority of a task is the priority that
+      was last assigned to the task - which due to priority inheritance, may not
+      be the current priority of the task.
+    + Add pdTICKS_TO_MS macro to convert time in FreeRTOS ticks to time in
+      milliseconds. We thank @Dazza0 for their contribution.
+    + Add default implementations of vApplicationGetIdleTaskMemory and
+      vApplicationGetTimerTaskMemory. The application can enable these default
+      implementations by setting configKERNEL_PROVIDED_STATIC_MEMORY to 1 in their
+      FreeRTOSConfig.h. We thank @mdnr-g for their contribution.
+    + Update vTaskGetInfo to include start and end of the stack whenever both
+      values are available. We thank @vinceburns for their contribution.
+    + Prevent tasks waiting for a notification from being resumed by calls to
+      vTaskResume or vTaskResumeFromISR. We thank @Moral-Hao for their
+      contribution.
+    + Add asserts to validate that the application has correctly installed
+      FreeRTOS handlers for PendSV and SVCall interrupts on Cortex-M devices.
+      We thank @jefftenney for their contribution.
+    + Rename ARM_CA53_64_BIT and ARM_CA53_64_BIT_SRE ports to Arm_AARCH64 and
+      Arm_AARCH64_SRE respectively as these ports are applicable to all AArch64
+      architecture. We thank @urutva for their contribution.
+    + Add CMake support to allow the application writer to select the RISC-V
+      chip extension. We thank @JoeBenczarski for their contribution.
+    + Add CMake support to allow the application writer to build an application
+      with static allocation only. We thank @conara for their contribution.
+    + Make taskYIELD available to unprivileged tasks for ARMv8-M ports.
+    + Update Cortex-M23 ports to not use PSPLIM_NS. We thank @urutva for their
+      contribution.
+    + Update the SysTick setup code for ARMv8-M ports to first configure the clock
+      source and then enable SysTick. This is needed to address a bug in QEMU
+      versions older than 7.0.0, which causes an emulation error if SysTick is
+      enabled without first selecting a valid clock source. We thank @jefftenney
+      for their contribution.
+    + Add the port-optimized task selection algorithm optionally available for
+      ARMv7-M ports to the ARMv8-M ports. We thank @jefftenney for their
+      contribution.
+    + Improve the speed of pvPortMalloc in heap_4.c and heap_5.c by removing
+      unnecessary steps while splitting a large memory block into two. We thank
+      @Moral-Hao for their contribution.
+    + Shorten the critical section in pvPortMalloc in heap_2.c, heap_4.c and
+      heap_5.c by moving the size calculation out of the critical section. We thank
+      @Moral-Hao for their contribution.
+    + Update xTaskNotifyWait and ulTaskNotifyTake to remove the non-deterministic
+      operation of traversing a linked link from a critical section. We thank
+      @karver8 for their contribution.
+    + Fix stack end and stack size computation in POSIX port to meet the stack
+      alignment requirements on MacOS. We thank @tegimeki for their contribution.
+    + Update the vTaskPrioritySet implementation to use the new priority when the
+      task has inherited priority from a mutex it is holding, and the new priority
+      is bigger than the inherited priority. We thank @Moral-Hao for their
+      contribution.
+    + Add stack alignment adjustment if stack grows upwards. We thank @ivq for
+      their contribution.
+    + Fix pxTopOfStack calculation in configINIT_TLS_BLOCK when picolib C is
+      selected as the C library implementation to ensure that
+      pxPortInitialiseStack does not overwrite the data in the TLS block portion
+      of the stack. We thank @bebebib-rs for their contribution.
+    + Fix vPortEndScheduler() for the MSVC port so that the function
+      prvProcessSimulatedInterrupts is not stuck in an infinite loop when the
+      scheduler is stopped. We thank @Ju1He1 for their contribution.
+    + Add the Pull Request (PR) Process explaining the stages a PR goes through.
+
+Changes between FreeRTOS V10.6.1 and FreeRTOS V10.6.2 released November 29, 2023
+
+	+ Add the following improvements to the new MPU wrapper (mpu_wrappers_v2.c)
+	  introduced in version 10.6.0:
+	  - Introduce Access Control List (ACL) feature to allow the application
+	    writer to control an unprivileged task’s access to kernel objects.
+	  - Update the system call entry mechanism to only require one Supervisor
+	    Call (SVC) instruction.
+	  - Wrap parameters for system calls with more than four parameters in a
+	    struct to avoid special handling during system call entry.
+	  - Fix 2 possible integer overflows.
+	  - Convert some asserts to run time parameter checks.
+
+Changes between FreeRTOS V10.6.0 and FreeRTOS V10.6.1 released August 17, 2023
+
+	+ Add runtime parameter checks to functions in mpu_wrappers_v2.c file.
+	  The same checks are already performed in API implementations using
+	  asserts.
+	  We thank the following people for their inputs in these changes:
+	  - Lan Luo, Zixia Liu of School of Computer Science and Technology,
+	    Anhui University of Technology, China.
+	  - Xinwen Fu of Department of Computer Science, University of
+	    Massachusetts Lowell, USA.
+	  - Xinhui Shao, Yumeng Wei, Huaiyu Yan, Zhen Ling of School of
+	    Computer Science and Engineering, Southeast University, China.
+
 Changes between FreeRTOS V10.5.1 and FreeRTOS 10.6.0 released July 13, 2023
 
 	+ Add a new MPU wrapper that places additional restrictions on unprivileged
@@ -61,8 +391,8 @@ Changes between FreeRTOS V10.5.1 and FreeRTOS 10.6.0 released July 13, 2023
 	      China.
 	    - Xinwen Fu of Department of Computer Science, University of
 	      Massachusetts Lowell, USA.
-	    - Yuequi Chen, Zicheng Wang, Minghao Lin of University of Colorado
-	      Boulder, USA.
+	    - Yueqi Chen, Zicheng Wang, Minghao Lin, Jiahe Wang of University of
+	      Colorado Boulder, USA.
 	+ Add Cortex-M35P port. Contributed by @urutva.
 	+ Add embedded extension (RV32E) support to the IAR RISC-V port.
 	+ Add ulTaskGetRunTimeCounter and ulTaskGetRunTimePercent APIs. Contributed by
@@ -333,7 +663,7 @@ Changes between FreeRTOS V10.4.3 and FreeRTOS V10.4.4 released May 28 2021
 	  in more files.
 	+ Other minor updates include adding additional configASSERT() checks and
 	  correcting and improving code comments.
-	+ Go look at the smp branch to see the progress towards the Symetric
+	+ Go look at the smp branch to see the progress towards the Symmetric
 	  Multiprocessing Kernel. https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/smp
 
 Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020
@@ -1820,7 +2150,7 @@ Changes between V6.1.0 and V6.1.1 released January 14 2011
 	  Embedded Workbench.
 	+ Added a new port for the MSP430X core using the IAR Embedded Workbench.
 	+ Updated all the RX62N demo projects that target the Renesas Demonstration
-	  Kit (RDK) to take into account the revered LED wiring on later hardware
+	  Kit (RDK) to take into account the reversed LED wiring on later hardware
 	  revisions, and the new J-Link debug interface DLL.
 	+ Updated all the RX62N demo projects so the IO page served by the example
 	  embedded web server works with all web browsers.
@@ -2979,7 +3309,7 @@ Changes between V1.2.3 and V1.2.4
 	  xSerialPortInitMinimal() and the function xPortInit() has been renamed
 	  to xSerialPortInit().
 	+ The function sSerialPutChar() has been renamed cSerialPutChar() and
-	  the function return type chaned to portCHAR.
+	  the function return type changed to portCHAR.
 	+ The integer and flop tasks now include calls to tskYIELD(), allowing
 	  them to be used with the cooperative scheduler.
 	+ All the demo applications now use the integer and comtest tasks when the
@@ -3113,7 +3443,7 @@ Changes between V1.01 and V1.2.0
 	  ports to allocate a different maximum number of priorities.
 	+ By default the trace facility is off, previously USE_TRACE_FACILITY
 	  was defined.
-	+ comtest.c now uses a psuedo random delay between sends.  This allows for
+	+ comtest.c now uses a pseudo random delay between sends.  This allows for
 	  better testing as the interrupts do not arrive at regular intervals.
 	+ Minor change to the Flashlite serial port driver.  The driver is written
 	  to demonstrate the scheduler and is not written to be efficient.

MISRA.md

@@ -0,0 +1,145 @@
+# MISRA Compliance
+
+FreeRTOS-Kernel conforms to [MISRA C:2012](https://www.misra.org.uk/misra-c)
+guidelines, with the deviations listed below. Compliance is checked with
+Coverity static analysis version 2023.6.1. Since the FreeRTOS kernel is
+designed for small-embedded devices, it needs to have a very small memory
+footprint and has to be efficient. To achieve that and to increase the
+performance, it deviates from some MISRA rules. The specific deviations,
+suppressed inline, are listed below.
+
+Additionally, [MISRA configuration file](examples/coverity/coverity_misra.config)
+contains project wide deviations.
+
+### Suppressed with Coverity Comments
+To find the violation references in the source files run grep on the source code
+with ( Assuming rule 8.4 violation; with justification in point 1 ):
+```
+grep 'MISRA Ref 8.4.1' . -rI
+```
+
+#### Dir 4.7
+MISRA C:2012 Dir 4.7: If a function returns error information, then that error
+information shall be tested.
+
+_Ref 4.7.1_
+ - `taskENTER_CRITICAL_FROM_ISR` returns the interrupt mask and not any error
+    information. Therefore, there is no need test the return value.
+
+#### Rule 8.4
+
+MISRA C:2012 Rule 8.4: A compatible declaration shall be visible when an
+object or function with external linkage is defined.
+
+_Ref 8.4.1_
+ - pxCurrentTCB(s) is defined with external linkage but it is only referenced
+   from the assembly code in the port files. Therefore, adding a declaration in
+   header file is not useful as the assembly code will still need to declare it
+   separately.
+
+_Ref 8.4.2_
+ - xQueueRegistry is defined with external linkage because it is accessed by the
+   kernel unit tests. It is not meant to be directly accessed by the application
+   and therefore, not declared in a header file.
+
+#### Rule 8.6
+
+MISRA C:2012 Rule 8.6: An identifier with external linkage shall have exactly
+one external definition.
+
+_Ref 8.6.1_
+ - This rule prohibits an identifier with external linkage to have multiple
+   definitions or no definition. FreeRTOS hook functions are implemented in
+   the application and therefore, have no definition in the Kernel code.
+
+#### Rule 11.1
+MISRA C:2012 Rule 11.1: Conversions shall not be performed between a pointer to
+function and any other type.
+
+_Ref 11.1.1_
+ - The pointer to function is casted into void to avoid unused parameter
+   compiler warning when Stream Buffer's Tx and Rx Completed callback feature is
+   not used.
+
+#### Rule 11.3
+
+MISRA C:2012 Rule 11.3: A cast shall not be performed between a pointer to
+object type and a pointer to a different object type.
+
+_Ref 11.3.1_
+ - This rule prohibits casting a pointer to object into a pointer to a
+   different object because it may result in an incorrectly aligned pointer,
+   leading to undefined behavior. Even if the casting produces a correctly
+   aligned pointer, the behavior may be still undefined if the pointer is
+   used to access an object. FreeRTOS deliberately creates external aliases
+   for all the kernel object types (StaticEventGroup_t, StaticQueue_t,
+   StaticStreamBuffer_t, StaticTimer_t and StaticTask_t) for data hiding
+   purposes. The internal object types and the corresponding external
+   aliases are guaranteed to have the same size and alignment which is
+   checked using configASSERT.
+
+
+#### Rule 11.5
+
+MISRA C:2012 Rule 11.5: A conversion should not be performed from pointer to
+void into pointer to object.
+This rule prohibits conversion of a pointer to void into a pointer to
+object because it may result in an incorrectly aligned pointer leading
+to undefined behavior.
+
+_Ref 11.5.1_
+ - The memory blocks returned by pvPortMalloc() are guaranteed to meet the
+   architecture alignment requirements specified by portBYTE_ALIGNMENT.
+   The casting of the pointer to void returned by pvPortMalloc() is,
+   therefore, safe because it is guaranteed to be aligned.
+
+_Ref 11.5.2_
+ - The conversion from a pointer to void into a pointer to EventGroup_t is
+   safe because it is a pointer to EventGroup_t, which is returned to the
+   application at the time of event group creation for data hiding
+   purposes.
+
+_Ref 11.5.3_
+ - The conversion from a pointer to void in list macros for list item owner
+   is safe because the type of the pointer stored and retrieved is the
+   same.
+
+_Ref 11.5.4_
+ - The conversion from a pointer to void into a pointer to EventGroup_t is
+   safe because it is a pointer to EventGroup_t, which is passed as a
+   parameter to the xTimerPendFunctionCallFromISR API when the callback is
+   pended.
+
+_Ref 11.5.5_
+ - The conversion from a pointer to void into a pointer to uint8_t is safe
+   because data storage buffers are implemented as uint8_t arrays for the
+   ease of sizing, alignment and access.
+
+#### Rule 14.3
+
+MISRA C-2012 Rule 14.3: Controlling expressions shall not be invariant.
+
+_Ref 14.3_
+ - The `configMAX_TASK_NAME_LEN` , `taskRESERVED_TASK_NAME_LENGTH` and `SIZE_MAX`
+   are evaluated to constants at compile time and may vary based on the build
+   configuration.
+
+#### Rule 18.1
+
+MISRA C-2012 Rule 18.1: A pointer resulting from arithmetic on a pointer operand
+shall address an element of the same array as that pointer operand.
+
+_Ref 18.1_
+ - Array access remains within bounds since either the null terminator in
+   the IDLE task name will break the loop, or the loop will break normally
+   if the array size is smaller than the IDLE task name length.
+
+#### Rule 21.6
+
+MISRA C-2012 Rule 21.6: The Standard Library input/output functions shall not
+be used.
+
+_Ref 21.6.1_
+ - The Standard Library function snprintf is used in vTaskListTasks and
+   vTaskGetRunTimeStatistics APIs, both of which are utility functions only and
+   are not considered part of core kernel implementation.

README.md

@@ -1,18 +1,45 @@
 [![CMock Unit Tests](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml/badge.svg?branch=main&event=push)](https://github.com/FreeRTOS/FreeRTOS-Kernel/actions/workflows/unit-tests.yml?query=branch%3Amain+event%3Apush+workflow%3A%22CMock+Unit+Tests%22++)
 [![codecov](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel/badge.svg?branch=main)](https://codecov.io/gh/FreeRTOS/FreeRTOS-Kernel)
+
 ## Getting started
-This repository contains FreeRTOS kernel source/header files and kernel ports only. This repository is referenced as a submodule in [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) repository, which contains pre-configured demo application projects under ```FreeRTOS/Demo``` directory.
 
-The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects.  That way you will have the correct FreeRTOS source files included, and the correct include paths configured.  Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files.  See the [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links.
+This repository contains FreeRTOS kernel source/header files and kernel
+ports only. This repository is referenced as a submodule in
+[FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS)
+repository, which contains pre-configured demo application projects under
+```FreeRTOS/Demo``` directory.
 
-Additionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.FreeRTOS.org/features.html), and [API Reference](https://www.FreeRTOS.org/a00106.html).
+The easiest way to use FreeRTOS is to start with one of the pre-configured demo
+application projects.  That way you will have the correct FreeRTOS source files
+included, and the correct include paths configured. Once a demo application is
+building and executing you can remove the demo application files, and start to
+add in your own application source files.  See the
+[FreeRTOS Kernel Quick Start Guide](https://www.freertos.org/Documentation/01-FreeRTOS-quick-start/01-Beginners-guide/02-Quick-start-guide)
+for detailed instructions and other useful links.
+
+Additionally, for FreeRTOS kernel feature information refer to the
+[Developer Documentation](https://www.freertos.org/Documentation/02-Kernel/02-Kernel-features/00-Developer-docs),
+and [API Reference](https://www.freertos.org/Documentation/02-Kernel/04-API-references/01-Task-creation/00-TaskHandle).
+
+Also for contributing and creating a Pull Request please refer to
+[the instructions here](.github/CONTRIBUTING.md#contributing-via-pull-request).
+
+**FreeRTOS-Kernel V11.1.0
+[source code](https://github.com/FreeRTOS/FreeRTOS-Kernel/tree/V11.1.0) is part
+of the
+[FreeRTOS 202406.00 LTS](https://github.com/FreeRTOS/FreeRTOS-LTS/tree/202406-LTS)
+release.**
 
 ### Getting help
-If you have any questions or need assistance troubleshooting your FreeRTOS project, we have an active community that can help on the [FreeRTOS Community Support Forum](https://forums.freertos.org).
+
+If you have any questions or need assistance troubleshooting your FreeRTOS project,
+we have an active community that can help on the
+[FreeRTOS Community Support Forum](https://forums.freertos.org).
 
 ## To consume FreeRTOS-Kernel
 
 ### Consume with CMake
+
 If using CMake, it is recommended to use this repository using FetchContent.
 Add the following into your project's main or a subdirectory's `CMakeLists.txt`:
 
@@ -25,8 +52,16 @@ FetchContent_Declare( freertos_kernel
 )
 ```
 
+In case you prefer to add it as a git submodule, do:
+
+```bash
+git submodule add https://github.com/FreeRTOS/FreeRTOS-Kernel.git <path of the submodule>
+git submodule update --init
+```
+
 - Add a freertos_config library (typically an INTERFACE library) The following assumes the directory structure:
   - `include/FreeRTOSConfig.h`
+
 ```cmake
 add_library(freertos_config INTERFACE)
 
@@ -41,6 +76,12 @@ target_compile_definitions(freertos_config
 )
 ```
 
+In case you installed FreeRTOS-Kernel as a submodule, you will have to add it as a subdirectory:
+
+```cmake
+add_subdirectory(${FREERTOS_PATH})
+```
+
 - Configure the FreeRTOS-Kernel and make it available
   - this particular example supports a native and cross-compiled build option.
 
@@ -56,18 +97,29 @@ endif()
 FetchContent_MakeAvailable(freertos_kernel)
 ```
 
+- In case of cross compilation, you should also add the following to `freertos_config`:
+
+```cmake
+target_compile_definitions(freertos_config INTERFACE ${definitions})
+target_compile_options(freertos_config INTERFACE ${options})
+```
+
 ### Consuming stand-alone - Cloning this repository
 
 To clone using HTTPS:
+
 ```
 git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git
 ```
+
 Using SSH:
+
 ```
 git clone git@github.com:FreeRTOS/FreeRTOS-Kernel.git
 ```
 
 ## Repository structure
+
 - The root of this repository contains the three files that are common to
 every port - list.c, queue.c and tasks.c.  The kernel is contained within these
 three files.  croutine.c implements the optional co-routine functionality - which
@@ -78,23 +130,63 @@ See the readme file in the ```./portable``` directory for more information.
 
 - The ```./include``` directory contains the real time kernel header files.
 
+- The ```./template_configuration``` directory contains a sample `FreeRTOSConfig.h` to help jumpstart a new project.
+See the [FreeRTOSConfig.h](examples/template_configuration/FreeRTOSConfig.h) file for instructions.
+
 ### Code Formatting
-FreeRTOS files are formatted using the "uncrustify" tool. The configuration file used by uncrustify can be found in the [.github/uncrustify.cfg](.github/uncrustify.cfg) file.
+
+FreeRTOS files are formatted using the
+"[uncrustify](https://github.com/uncrustify/uncrustify)" tool.
+The configuration file used by uncrustify can be found in the
+[FreeRTOS/CI-CD-GitHub-Actions's](https://github.com/FreeRTOS/CI-CD-Github-Actions)
+[uncrustify.cfg](https://github.com/FreeRTOS/CI-CD-Github-Actions/tree/main/formatting)
+file.
 
 ### Line Endings
-File checked into the FreeRTOS-Kernel repository use unix-style LF line endings for the best compatbility with git.
 
-For optmial compatibility with Microsoft Windows tools, it is best to enable the git autocrlf feature. You can eanble this setting for the current repository using the following command:
+File checked into the FreeRTOS-Kernel repository use unix-style LF line endings
+for the best compatibility with git.
+
+For optimal compatibility with Microsoft Windows tools, it is best to enable
+the git autocrlf feature. You can enable this setting for the current
+repository using the following command:
+
 ```
 git config core.autocrlf true
 ```
 
 ### Git History Optimizations
-Some commits in this repository perform large refactors which touch many lines and lead to unwanted behavior when using the `git blame` command. You can configure git to ignore the list of large refactor commits in this repository with the followig command:
+
+Some commits in this repository perform large refactors which touch many lines
+and lead to unwanted behavior when using the `git blame` command. You can
+configure git to ignore the list of large refactor commits in this repository
+with the following command:
+
 ```
 git config blame.ignoreRevsFile .git-blame-ignore-revs
 ```
 
-### Spelling
-*lexicon.txt* contains words that are not traditionally found in an English dictionary. It is used by the spellchecker to verify the various jargon, variable names, and other odd words used in the FreeRTOS code base. If your pull request fails to pass the spelling and you believe this is a mistake, then add the word to *lexicon.txt*.
-Note that only the FreeRTOS Kernel source files are checked for proper spelling, the portable section is ignored.
+### Spelling and Formatting
+
+We recommend using [Visual Studio Code](https://code.visualstudio.com),
+commonly referred to as VSCode, when working on the FreeRTOS-Kernel.
+The FreeRTOS-Kernel also uses [cSpell](https://cspell.org/) as part of its
+spelling check. The config file for which can be found at [cspell.config.yaml](cspell.config.yaml)
+There is additionally a
+[cSpell plugin for VSCode](https://marketplace.visualstudio.com/items?itemName=streetsidesoftware.code-spell-checker)
+that can be used as well.
+*[.cSpellWords.txt](.github/.cSpellWords.txt)* contains words that are not
+traditionally found in an English dictionary. It is used by the spellchecker
+to verify the various jargon, variable names, and other odd words used in the
+FreeRTOS code base are correct. If your pull request fails to pass the spelling
+and you believe this is a mistake, then add the word to
+*[.cSpellWords.txt](.github/.cSpellWords.txt)*. When adding a word please
+then sort the list, which can be done by running the bash command:
+`sort -u .cSpellWords.txt -o .cSpellWords.txt`
+Note that only the FreeRTOS-Kernel Source Files, [include](include),
+[portable/MemMang](portable/MemMang), and [portable/Common](portable/Common)
+files are checked for proper spelling, and formatting at this time.
+
+## Third Party Tools
+Visit [this link](.github/third_party_tools.md) for detailed information about
+third-party tools with FreeRTOS support.

croutine.c

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -30,7 +30,7 @@
 #include "task.h"
 #include "croutine.h"
 
-/* Remove the whole file is co-routines are not being used. */
+/* Remove the whole file if co-routines are not being used. */
 #if ( configUSE_CO_ROUTINES != 0 )
 
 /*
@@ -43,17 +43,19 @@
 
 
 /* Lists for ready and blocked co-routines. --------------------*/
-    static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */
-    static List_t xDelayedCoRoutineList1;                                   /*< Delayed co-routines. */
-    static List_t xDelayedCoRoutineList2;                                   /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
-    static List_t * pxDelayedCoRoutineList = NULL;                          /*< Points to the delayed co-routine list currently being used. */
-    static List_t * pxOverflowDelayedCoRoutineList = NULL;                  /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
-    static List_t xPendingReadyCoRoutineList;                               /*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+    static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /**< Prioritised ready co-routines. */
+    static List_t xDelayedCoRoutineList1;                                   /**< Delayed co-routines. */
+    static List_t xDelayedCoRoutineList2;                                   /**< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+    static List_t * pxDelayedCoRoutineList = NULL;                          /**< Points to the delayed co-routine list currently being used. */
+    static List_t * pxOverflowDelayedCoRoutineList = NULL;                  /**< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+    static List_t xPendingReadyCoRoutineList;                               /**< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
 
 /* Other file private variables. --------------------------------*/
     CRCB_t * pxCurrentCoRoutine = NULL;
-    static UBaseType_t uxTopCoRoutineReadyPriority = 0;
-    static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+    static UBaseType_t uxTopCoRoutineReadyPriority = ( UBaseType_t ) 0U;
+    static TickType_t xCoRoutineTickCount = ( TickType_t ) 0U;
+    static TickType_t xLastTickCount = ( TickType_t ) 0U;
+    static TickType_t xPassedTicks = ( TickType_t ) 0U;
 
 /* The initial state of the co-routine when it is created. */
     #define corINITIAL_STATE    ( 0 )
@@ -107,7 +109,12 @@
         BaseType_t xReturn;
         CRCB_t * pxCoRoutine;
 
+        traceENTER_xCoRoutineCreate( pxCoRoutineCode, uxPriority, uxIndex );
+
         /* Allocate the memory that will store the co-routine control block. */
+        /* MISRA Ref 11.5.1 [Malloc memory assignment] */
+        /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
+        /* coverity[misra_c_2012_rule_11_5_violation] */
         pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
 
         if( pxCoRoutine )
@@ -156,6 +163,8 @@
             xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
         }
 
+        traceRETURN_xCoRoutineCreate( xReturn );
+
         return xReturn;
     }
 /*-----------------------------------------------------------*/
@@ -165,6 +174,8 @@
     {
         TickType_t xTimeToWake;
 
+        traceENTER_vCoRoutineAddToDelayedList( xTicksToDelay, pxEventList );
+
         /* Calculate the time to wake - this may overflow but this is
          * not a problem. */
         xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
@@ -196,6 +207,8 @@
              * function must be called with interrupts disabled. */
             vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
         }
+
+        traceRETURN_vCoRoutineAddToDelayedList();
     }
 /*-----------------------------------------------------------*/
 
@@ -283,6 +296,8 @@
 
     void vCoRoutineSchedule( void )
     {
+        traceENTER_vCoRoutineSchedule();
+
         /* Only run a co-routine after prvInitialiseCoRoutineLists() has been
          * called.  prvInitialiseCoRoutineLists() is called automatically when a
          * co-routine is created. */
@@ -313,6 +328,8 @@
             /* Call the co-routine. */
             ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
         }
+
+        traceRETURN_vCoRoutineSchedule();
     }
 /*-----------------------------------------------------------*/
 
@@ -341,6 +358,8 @@
         CRCB_t * pxUnblockedCRCB;
         BaseType_t xReturn;
 
+        traceENTER_xCoRoutineRemoveFromEventList( pxEventList );
+
         /* This function is called from within an interrupt.  It can only access
          * event lists and the pending ready list.  This function assumes that a
          * check has already been made to ensure pxEventList is not empty. */
@@ -357,7 +376,30 @@
             xReturn = pdFALSE;
         }
 
+        traceRETURN_xCoRoutineRemoveFromEventList( xReturn );
+
         return xReturn;
     }
+/*-----------------------------------------------------------*/
+
+/*
+ * Reset state in this file. This state is normally initialized at start up.
+ * This function must be called by the application before restarting the
+ * scheduler.
+ */
+    void vCoRoutineResetState( void )
+    {
+        /* Lists for ready and blocked co-routines. */
+        pxDelayedCoRoutineList = NULL;
+        pxOverflowDelayedCoRoutineList = NULL;
+
+        /* Other file private variables. */
+        pxCurrentCoRoutine = NULL;
+        uxTopCoRoutineReadyPriority = ( UBaseType_t ) 0U;
+        xCoRoutineTickCount = ( TickType_t ) 0U;
+        xLastTickCount = ( TickType_t ) 0U;
+        xPassedTicks = ( TickType_t ) 0U;
+    }
+/*-----------------------------------------------------------*/
 
 #endif /* configUSE_CO_ROUTINES == 0 */

cspell.config.yaml

@@ -0,0 +1,31 @@
+---
+$schema: https://raw.githubusercontent.com/streetsidesoftware/cspell/main/cspell.schema.json
+version: '0.2'
+# Allows things like stringLength
+allowCompoundWords: true
+
+# Read files not to spell check from the git ignore
+useGitignore: true
+
+#  Language settings for C
+languageSettings:
+  - caseSensitive: false
+    enabled: true
+    languageId: c
+    locale: "*"
+
+# Add a dictionary, and the path to the word list
+dictionaryDefinitions:
+  - name: freertos-words
+    path: '.github/.cSpellWords.txt'
+    addWords: true
+
+dictionaries:
+  - freertos-words
+
+# Paths and files to ignore
+ignorePaths:
+  - 'dependency'
+  - 'docs'
+  - 'ThirdParty'
+  - 'History.txt'

examples/README.md

@@ -0,0 +1,17 @@
+# README for FreeRTOS-Kernel/examples
+
+The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects.
+See [FreeRTOS/FreeRTOS/Demo](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS/Demo) to find a list of pre-configured demos on multiple platforms which demonstrate the working of the FreeRTOS-Kernel.
+This directory aims to further facilitate the beginners in building their first FreeRTOS project.
+
+
+## Directory Structure:
+
+* The [cmake_example](./cmake_example) directory contains a minimal FreeRTOS example project, which uses the configuration file in the template_configuration directory listed below. This will provide you with a starting point for building your applications using FreeRTOS-Kernel.
+* The [coverity](./coverity) directory contains a project to run [Synopsys Coverity](https://www.synopsys.com/software-integrity/static-analysis-tools-sast/coverity.html) for checking MISRA compliance. This directory contains further readme files and links to documentation.
+* The [template_configuration](./template_configuration) directory contains a sample configuration file FreeRTOSConfig.h which helps you in preparing your application configuration
+
+
+## Additional examples
+
+Additional examples of the kernel being used in real life applications in tandem with many other libraries (i.e. FreeRTOS+TCP, coreMQTT, coreHTTP etc.) can be found [here](https://github.com/FreeRTOS/FreeRTOS/tree/main/FreeRTOS-Plus/Demo).

examples/cmake_example/CMakeLists.txt

@@ -0,0 +1,74 @@
+cmake_minimum_required(VERSION 3.15)
+project(example)
+
+set(FREERTOS_KERNEL_PATH "../../")
+
+# Add the freertos_config for FreeRTOS-Kernel
+add_library(freertos_config INTERFACE)
+
+target_include_directories(freertos_config
+    INTERFACE
+    "../template_configuration"
+)
+
+if (DEFINED FREERTOS_SMP_EXAMPLE AND FREERTOS_SMP_EXAMPLE STREQUAL "1")
+    message(STATUS "Build FreeRTOS SMP example")
+    # Adding the following configurations to build SMP template port
+    add_compile_options( -DconfigNUMBER_OF_CORES=2 -DconfigUSE_PASSIVE_IDLE_HOOK=0 )
+endif()
+
+# Select the heap port.  values between 1-4 will pick a heap.
+set(FREERTOS_HEAP "4" CACHE STRING "" FORCE)
+
+# Select the native compile PORT
+set(FREERTOS_PORT "TEMPLATE" CACHE STRING "" FORCE)
+
+# Adding the FreeRTOS-Kernel subdirectory
+add_subdirectory(${FREERTOS_KERNEL_PATH} FreeRTOS-Kernel)
+
+########################################################################
+# Overall Compile Options
+# Note the compile option strategy is to error on everything and then
+# Per library opt-out of things that are warnings/errors.
+# This ensures that no matter what strategy for compilation you take, the
+# builds will still occur.
+#
+# Only tested with GNU and Clang.
+# Other options are https://cmake.org/cmake/help/latest/variable/CMAKE_LANG_COMPILER_ID.html#variable:CMAKE_%3CLANG%3E_COMPILER_ID
+# Naming of compilers translation map:
+#
+#   FreeRTOS    | CMake
+#   -------------------
+#   CCS         | ?TBD?
+#   GCC         | GNU, Clang, *Clang Others?
+#   IAR         | IAR
+#   Keil        | ARMCC
+#   MSVC        | MSVC # Note only for MinGW?
+#   Renesas     | ?TBD?
+
+target_compile_options(freertos_kernel PRIVATE
+    ### Gnu/Clang C Options
+    $<$<COMPILE_LANG_AND_ID:C,GNU>:-fdiagnostics-color=always>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-fcolor-diagnostics>
+
+    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wall>
+    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wextra>
+    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wpedantic>
+    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Werror>
+    $<$<COMPILE_LANG_AND_ID:C,Clang,GNU>:-Wconversion>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Weverything>
+
+    # Suppressions required to build clean with clang.
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-unused-macros>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-padded>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-missing-variable-declarations>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-covered-switch-default>
+    $<$<COMPILE_LANG_AND_ID:C,Clang>:-Wno-cast-align> )
+
+add_executable(${PROJECT_NAME}
+    main.c
+)
+
+target_link_libraries(${PROJECT_NAME} freertos_kernel freertos_config)
+
+set_property(TARGET freertos_kernel PROPERTY C_STANDARD 90)

examples/cmake_example/main.c

@@ -0,0 +1,104 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * This is a simple main that will start the FreeRTOS-Kernel and run a periodic task
+ * that only delays if compiled with the template port, this project will do nothing.
+ * For more information on getting started please look here:
+ * https://www.freertos.org/Documentation/01-FreeRTOS-quick-start/01-Beginners-guide/02-Quick-start-guide
+ */
+
+/* FreeRTOS includes. */
+#include <FreeRTOS.h>
+#include <task.h>
+#include <queue.h>
+#include <timers.h>
+#include <semphr.h>
+
+/* Standard includes. */
+#include <stdio.h>
+
+/*-----------------------------------------------------------*/
+
+static void exampleTask( void * parameters ) __attribute__( ( noreturn ) );
+
+/*-----------------------------------------------------------*/
+
+static void exampleTask( void * parameters )
+{
+    /* Unused parameters. */
+    ( void ) parameters;
+
+    for( ; ; )
+    {
+        /* Example Task Code */
+        vTaskDelay( 100 ); /* delay 100 ticks */
+    }
+}
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+    static StaticTask_t exampleTaskTCB;
+    static StackType_t exampleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+    ( void ) printf( "Example FreeRTOS Project\n" );
+
+    ( void ) xTaskCreateStatic( exampleTask,
+                                "example",
+                                configMINIMAL_STACK_SIZE,
+                                NULL,
+                                configMAX_PRIORITIES - 1U,
+                                &( exampleTaskStack[ 0 ] ),
+                                &( exampleTaskTCB ) );
+
+    /* Start the scheduler. */
+    vTaskStartScheduler();
+
+    for( ; ; )
+    {
+        /* Should not reach here. */
+    }
+
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+    void vApplicationStackOverflowHook( TaskHandle_t xTask,
+                                        char * pcTaskName )
+    {
+        /* Check pcTaskName for the name of the offending task,
+         * or pxCurrentTCB if pcTaskName has itself been corrupted. */
+        ( void ) xTask;
+        ( void ) pcTaskName;
+    }
+
+#endif /* #if ( configCHECK_FOR_STACK_OVERFLOW > 0 ) */
+/*-----------------------------------------------------------*/

examples/coverity/CMakeLists.txt

@@ -0,0 +1,46 @@
+cmake_minimum_required(VERSION 3.15)
+
+project(coverity)
+
+set(FREERTOS_KERNEL_PATH "../..")
+FILE(GLOB FREERTOS_KERNEL_SOURCE ${FREERTOS_KERNEL_PATH}/*.c)
+FILE(GLOB FREERTOS_PORT_CODE ${FREERTOS_KERNEL_PATH}/portable/template/*.c)
+
+# Coverity incorrectly infers the type of pdTRUE and pdFALSE as boolean because
+# of their names. This generates multiple false positive warnings about type
+# mismatch. Replace pdTRUE with pdPASS and pdFALSE with pdFAIL to avoid these
+# false positive warnings. This workaround will not be needed after Coverity
+# fixes the issue of incorrectly inferring the type of pdTRUE and pdFALSE as
+# boolean.
+add_custom_target(fix_source ALL
+                  COMMAND sed -i -b -e 's/pdFALSE/pdFAIL/g' -e 's/pdTRUE/pdPASS/g' ${FREERTOS_KERNEL_SOURCE} ${FREERTOS_PORT_CODE}
+                  DEPENDS ${FREERTOS_KERNEL_SOURCE} ${FREERTOS_PORT_CODE})
+
+# Add the freertos_config for FreeRTOS-Kernel.
+add_library(freertos_config INTERFACE)
+
+target_include_directories(freertos_config
+                           INTERFACE
+                           ./)
+
+if (DEFINED FREERTOS_SMP_EXAMPLE AND FREERTOS_SMP_EXAMPLE STREQUAL "1")
+    message(STATUS "Build FreeRTOS SMP example")
+    # Adding the following configurations to build SMP template port
+    add_compile_options( -DconfigNUMBER_OF_CORES=2 -DconfigUSE_PASSIVE_IDLE_HOOK=0 )
+endif()
+
+# Select the heap. Values between 1-5 will pick a heap.
+set(FREERTOS_HEAP "3" CACHE STRING "" FORCE)
+
+# Select the FreeRTOS port.
+set(FREERTOS_PORT "TEMPLATE" CACHE STRING "" FORCE)
+
+# Add the FreeRTOS-Kernel subdirectory.
+add_subdirectory(${FREERTOS_KERNEL_PATH} FreeRTOS-Kernel)
+
+add_executable(${PROJECT_NAME}
+               ../cmake_example/main.c)
+
+add_dependencies(${PROJECT_NAME} fix_source)
+
+target_link_libraries(${PROJECT_NAME} freertos_kernel freertos_config)

examples/coverity/FreeRTOSConfig.h

@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/******************************************************************************/
+/* Hardware description related definitions. **********************************/
+/******************************************************************************/
+
+#define configCPU_CLOCK_HZ    ( ( unsigned long ) 20000000 )
+
+/******************************************************************************/
+/* Scheduling behaviour related definitions. **********************************/
+/******************************************************************************/
+
+#define configTICK_RATE_HZ                         ( 100U )
+#define configUSE_PREEMPTION                       1
+#define configUSE_TIME_SLICING                     1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
+#define configUSE_TICKLESS_IDLE                    1
+#define configMAX_PRIORITIES                       5U
+#define configMINIMAL_STACK_SIZE                   128U
+#define configMAX_TASK_NAME_LEN                    4U
+#define configTICK_TYPE_WIDTH_IN_BITS              TICK_TYPE_WIDTH_64_BITS
+#define configIDLE_SHOULD_YIELD                    1
+#define configTASK_NOTIFICATION_ARRAY_ENTRIES      1U
+#define configQUEUE_REGISTRY_SIZE                  0U
+#define configENABLE_BACKWARD_COMPATIBILITY        1
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS    0
+#define configSTACK_DEPTH_TYPE                     size_t
+#define configMESSAGE_BUFFER_LENGTH_TYPE           size_t
+#define configUSE_NEWLIB_REENTRANT                 0
+
+/******************************************************************************/
+/* Software timer related definitions. ****************************************/
+/******************************************************************************/
+
+#define configUSE_TIMERS                1
+#define configTIMER_TASK_PRIORITY       ( configMAX_PRIORITIES - 1U )
+#define configTIMER_TASK_STACK_DEPTH    configMINIMAL_STACK_SIZE
+#define configTIMER_QUEUE_LENGTH        10U
+
+/******************************************************************************/
+/* Memory allocation related definitions. *************************************/
+/******************************************************************************/
+
+#define configSUPPORT_STATIC_ALLOCATION              1
+#define configSUPPORT_DYNAMIC_ALLOCATION             1
+#define configTOTAL_HEAP_SIZE                        4096U
+#define configAPPLICATION_ALLOCATED_HEAP             1
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0
+#define configUSE_MINI_LIST_ITEM                     0
+
+/******************************************************************************/
+/* Interrupt nesting behaviour configuration. *********************************/
+/******************************************************************************/
+
+#define configKERNEL_INTERRUPT_PRIORITY          0U
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY     0U
+#define configMAX_API_CALL_INTERRUPT_PRIORITY    0U
+
+/******************************************************************************/
+/* Hook and callback function related definitions. ****************************/
+/******************************************************************************/
+
+#define configUSE_IDLE_HOOK                   0
+#define configUSE_TICK_HOOK                   0
+#define configUSE_MALLOC_FAILED_HOOK          0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK    0
+#define configCHECK_FOR_STACK_OVERFLOW        0
+
+/******************************************************************************/
+/* Run time and task stats gathering related definitions. *********************/
+/******************************************************************************/
+
+#define configGENERATE_RUN_TIME_STATS           0
+#define configUSE_TRACE_FACILITY                0
+#define configUSE_STATS_FORMATTING_FUNCTIONS    0
+#define configKERNEL_PROVIDED_STATIC_MEMORY     1
+
+/******************************************************************************/
+/* Definitions that include or exclude functionality. *************************/
+/******************************************************************************/
+
+#define configUSE_TASK_NOTIFICATIONS           1
+#define configUSE_MUTEXES                      1
+#define configUSE_RECURSIVE_MUTEXES            1
+#define configUSE_COUNTING_SEMAPHORES          1
+#define configUSE_QUEUE_SETS                   1
+#define configUSE_APPLICATION_TASK_TAG         1
+#define INCLUDE_vTaskPrioritySet               1
+#define INCLUDE_uxTaskPriorityGet              1
+#define INCLUDE_vTaskDelete                    1
+#define INCLUDE_vTaskSuspend                   1
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         1
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    1
+#define INCLUDE_xTaskGetIdleTaskHandle         1
+#define INCLUDE_eTaskGetState                  1
+#define INCLUDE_xTimerPendFunctionCall         1
+#define INCLUDE_xTaskAbortDelay                1
+#define INCLUDE_xTaskGetHandle                 1
+#define INCLUDE_xTaskResumeFromISR             1
+
+#endif /* FREERTOS_CONFIG_H */

examples/coverity/README.md

@@ -0,0 +1,64 @@
+# MISRA Compliance for FreeRTOS-Kernel
+FreeRTOS-Kernel is MISRA C:2012 compliant. This directory contains a project to
+run [Synopsys Coverity](https://www.blackduck.com/static-analysis-tools-sast/coverity.html)
+for checking MISRA compliance.
+
+> **Note**
+Coverity version 2023.6.1 incorrectly infers the type of `pdTRUE` and `pdFALSE`
+as boolean because of their names, resulting in multiple false positive warnings
+about type mismatch. We replace `pdTRUE` with `pdPASS` and `pdFALSE` with
+`pdFAIL` to avoid these false positive warnings. This workaround will not be
+needed after Coverity fixes the issue of incorrectly inferring the type of
+`pdTRUE` and `pdFALSE` as boolean.
+
+Deviations from the MISRA C:2012 guidelines are documented in
+[MISRA.md](../../MISRA.md) and [coverity_misra.config](coverity_misra.config)
+files.
+
+## Getting Started
+### Prerequisites
+Coverity can be run on any platform mentioned [here](https://documentation.blackduck.com/bundle/coverity-docs/page/deploy-install-guide/topics/supported_platforms_for_coverity_analysis.html).
+The following are the prerequisites to generate coverity report:
+
+1. CMake version > 3.13.0 (You can check whether you have this by typing `cmake --version`).
+2. GCC compiler.
+    - See download and installation instructions [here](https://gcc.gnu.org/install/).
+3. Clone the repo using the following command:
+    - `git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git ./FreeRTOS-Kernel`
+
+### Generating Report
+Go to the root directory of the FreeRTOS-Kernel repo and run the following
+commands in a terminal:
+1. Update the compiler configuration in Coverity:
+  ~~~
+  cov-configure --force --compiler cc --comptype gcc
+  ~~~
+2. Create the build files using CMake in a `build` directory:
+
+Single core FreeRTOS:
+  ~~~
+  cmake -B build -S examples/coverity
+  ~~~
+
+SMP FreeRTOS:
+  ~~~
+  cmake -B build -S examples/coverity -DFREERTOS_SMP_EXAMPLE=1
+  ~~~
+3. Build the (pseudo) application:
+  ~~~
+  cd build/
+  cov-build --emit-complementary-info --dir cov-out make coverity
+  ~~~
+4. Go to the Coverity output directory (`cov-out`) and begin Coverity static
+   analysis:
+  ~~~
+  cov-analyze --dir ./cov-out \
+    --coding-standard-config ../examples/coverity/coverity_misra.config \
+    --tu-pattern "file('[A-Za-z_]+\.c') && ( ! file('main.c') ) && ( ! file('port.c') )"
+  ~~~
+5. Generate the HTML report:
+  ~~~
+  cov-format-errors --dir ./cov-out --html-output html-output
+  ~~~
+
+HTML report should now be generated in a directory named `html-output`.

examples/coverity/coverity_misra.config

@@ -0,0 +1,95 @@
+{
+    "version" : "2.0",
+    "standard" : "c2012",
+    "title": "Coverity MISRA Configuration",
+    "deviations" : [
+        {
+            "deviation": "Rule 1.2",
+            "reason": "Allow use of __attribute__ for necessary functions placement in specific memory regions."
+        },
+        {
+            "deviation": "Rule 3.1",
+            "reason": "We post HTTP links in code comments which contain // inside comments blocks."
+        },
+        {
+            "deviation": "Rule 14.4",
+            "reason": "do while( 0 ) pattern is used in macros to prevent extra semi-colon."
+        },
+        {
+            "deviation": "Directive 4.4",
+            "reason": "Code snippet is used in comment to help explanation."
+        },
+        {
+            "deviation": "Directive 4.5",
+            "reason": "Allow names that MISRA considers ambiguous."
+        },
+        {
+            "deviation": "Directive 4.6",
+            "reason": "Allow port to use primitive type with typedefs."
+        },
+        {
+            "deviation": "Directive 4.8",
+            "reason": "HeapRegion_t and HeapStats_t are used only in heap files but declared in portable.h which is included in multiple source files. As a result, these definitions appear in multiple source files where they are not used."
+        },
+        {
+            "deviation": "Directive 4.9",
+            "reason": "FreeRTOS-Kernel is optimised to work on small micro-controllers. To achieve that, function-like macros are used."
+        },
+        {
+            "deviation": "Rule 2.3",
+            "reason": "FreeRTOS defines types which is used in application."
+        },
+        {
+            "deviation": "Rule 2.4",
+            "reason": "Allow to define unused tag."
+        },
+        {
+            "deviation": "Rule 2.5",
+            "reason": "Allow to define unused macro."
+        },
+        {
+            "deviation": "Rule 5.9",
+            "reason": "Allow to define identifier with the same name in structure and global variable."
+        },
+        {
+            "deviation": "Rule 8.7",
+            "reason": "API functions are not used by the library outside of the files they are defined; however, they must be externally visible in order to be used by an application."
+        },
+        {
+            "deviation": "Rule 8.9",
+            "reason": "Allow to object to be defined in wider scope for debug purpose."
+        },
+        {
+            "deviation": "Rule 8.13",
+            "reason": "Allow to not to use const-qualified type for callback function."
+        },
+        {
+            "deviation": "Rule 11.4",
+            "reason": "Allow to convert between a pointer to object and an interger type for stack alignment."
+        },
+        {
+            "deviation": "Rule 15.4",
+            "reason": "Allow to use multiple break statements in a loop."
+        },
+        {
+            "deviation": "Rule 15.5",
+            "reason": "Allow to use multiple points of exit."
+        },
+        {
+            "deviation": "Rule 17.8",
+            "reason": "Allow to update the parameters of a function."
+        },
+        {
+            "deviation": "Rule 18.4",
+            "reason": "Allow to use pointer arithmetic."
+        },
+        {
+            "deviation": "Rule 19.2",
+            "reason": "Allow to use union."
+        },
+        {
+            "deviation": "Rule 20.5",
+            "reason": "Allow to use #undef for MPU wrappers."
+        }
+    ]
+}

examples/template_configuration/FreeRTOSConfig.h

@@ -0,0 +1,665 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*******************************************************************************
+ * This file provides an example FreeRTOSConfig.h header file, inclusive of an
+ * abbreviated explanation of each configuration item.  Online and reference
+ * documentation provides more information.
+ * https://www.freertos.org/a00110.html
+ *
+ * Constant values enclosed in square brackets ('[' and ']') must be completed
+ * before this file will build.
+ *
+ * Use the FreeRTOSConfig.h supplied with the RTOS port in use rather than this
+ * generic file, if one is available.
+ ******************************************************************************/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/******************************************************************************/
+/* Hardware description related definitions. **********************************/
+/******************************************************************************/
+
+/* In most cases, configCPU_CLOCK_HZ must be set to the frequency of the clock
+ * that drives the peripheral used to generate the kernels periodic tick
+ * interrupt. The default value is set to 20MHz and matches the QEMU demo
+ * settings.  Your application will certainly need a different value so set this
+ * correctly. This is very often, but not always, equal to the main system clock
+ * frequency. */
+#define configCPU_CLOCK_HZ    ( ( unsigned long ) 20000000 )
+
+/* configSYSTICK_CLOCK_HZ is an optional parameter for ARM Cortex-M ports only.
+ *
+ * By default ARM Cortex-M ports generate the RTOS tick interrupt from the
+ * Cortex-M SysTick timer. Most Cortex-M MCUs run the SysTick timer at the same
+ * frequency as the MCU itself - when that is the case configSYSTICK_CLOCK_HZ is
+ * not needed and should be left undefined. If the SysTick timer is clocked at a
+ * different frequency to the MCU core then set configCPU_CLOCK_HZ to the MCU
+ * clock frequency, as normal, and configSYSTICK_CLOCK_HZ to the SysTick clock
+ * frequency.  Not used if left undefined.
+ * The default value is undefined (commented out).  If you need this value bring
+ * it back and set it to a suitable value. */
+
+/*
+ #define configSYSTICK_CLOCK_HZ                  [Platform specific]
+ */
+
+/******************************************************************************/
+/* Scheduling behaviour related definitions. **********************************/
+/******************************************************************************/
+
+/* configTICK_RATE_HZ sets frequency of the tick interrupt in Hz, normally
+ * calculated from the configCPU_CLOCK_HZ value. */
+#define configTICK_RATE_HZ                         100
+
+/* Set configUSE_PREEMPTION to 1 to use pre-emptive scheduling.  Set
+ * configUSE_PREEMPTION to 0 to use co-operative scheduling.
+ * See https://www.freertos.org/single-core-amp-smp-rtos-scheduling.html. */
+#define configUSE_PREEMPTION                       1
+
+/* Set configUSE_TIME_SLICING to 1 to have the scheduler switch between Ready
+ * state tasks of equal priority on every tick interrupt.  Set
+ * configUSE_TIME_SLICING to 0 to prevent the scheduler switching between Ready
+ * state tasks just because there was a tick interrupt.  See
+ * https://freertos.org/single-core-amp-smp-rtos-scheduling.html. */
+#define configUSE_TIME_SLICING                     0
+
+/* Set configUSE_PORT_OPTIMISED_TASK_SELECTION to 1 to select the next task to
+ * run using an algorithm optimised to the instruction set of the target
+ * hardware - normally using a count leading zeros assembly instruction.  Set to
+ * 0 to select the next task to run using a generic C algorithm that works for
+ * all FreeRTOS ports.  Not all FreeRTOS ports have this option.  Defaults to 0
+ * if left undefined. */
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
+
+/* Set configUSE_TICKLESS_IDLE to 1 to use the low power tickless mode.  Set to
+ * 0 to keep the tick interrupt running at all times.  Not all FreeRTOS ports
+ * support tickless mode. See
+ * https://www.freertos.org/low-power-tickless-rtos.html Defaults to 0 if left
+ * undefined. */
+#define configUSE_TICKLESS_IDLE                    0
+
+/* configMAX_PRIORITIES Sets the number of available task priorities.  Tasks can
+ * be assigned priorities of 0 to (configMAX_PRIORITIES - 1).  Zero is the
+ * lowest priority. */
+#define configMAX_PRIORITIES                       5
+
+/* configMINIMAL_STACK_SIZE defines the size of the stack used by the Idle task
+ * (in words, not in bytes!).  The kernel does not use this constant for any
+ * other purpose.  Demo applications use the constant to make the demos somewhat
+ * portable across hardware architectures. */
+#define configMINIMAL_STACK_SIZE                   128
+
+/* configMAX_TASK_NAME_LEN sets the maximum length (in characters) of a task's
+ * human readable name.  Includes the NULL terminator. */
+#define configMAX_TASK_NAME_LEN                    16
+
+/* Time is measured in 'ticks' - which is the number of times the tick interrupt
+ * has executed since the RTOS kernel was started.
+ * The tick count is held in a variable of type TickType_t.
+ *
+ * configTICK_TYPE_WIDTH_IN_BITS controls the type (and therefore bit-width) of
+ * TickType_t:
+ *
+ * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_16_BITS causes
+ * TickType_t to be defined (typedef'ed) as an unsigned 16-bit type.
+ *
+ * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_32_BITS causes
+ * TickType_t to be defined (typedef'ed) as an unsigned 32-bit type.
+ *
+ * Defining configTICK_TYPE_WIDTH_IN_BITS as TICK_TYPE_WIDTH_64_BITS causes
+ * TickType_t to be defined (typedef'ed) as an unsigned 64-bit type. */
+#define configTICK_TYPE_WIDTH_IN_BITS              TICK_TYPE_WIDTH_64_BITS
+
+/* Set configIDLE_SHOULD_YIELD to 1 to have the Idle task yield to an
+ * application task if there is an Idle priority (priority 0) application task
+ * that can run.  Set to 0 to have the Idle task use all of its timeslice.
+ * Default to 1 if left undefined. */
+#define configIDLE_SHOULD_YIELD                    1
+
+/* Each task has an array of task notifications.
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array. See https://www.freertos.org/RTOS-task-notifications.html  Defaults to
+ * 1 if left undefined. */
+#define configTASK_NOTIFICATION_ARRAY_ENTRIES      1
+
+/* configQUEUE_REGISTRY_SIZE sets the maximum number of queues and semaphores
+ * that can be referenced from the queue registry.  Only required when using a
+ * kernel aware debugger.  Defaults to 0 if left undefined. */
+#define configQUEUE_REGISTRY_SIZE                  0
+
+/* Set configENABLE_BACKWARD_COMPATIBILITY to 1 to map function names and
+ * datatypes from old version of FreeRTOS to their latest equivalent.  Defaults
+ * to 1 if left undefined. */
+#define configENABLE_BACKWARD_COMPATIBILITY        0
+
+/* Each task has its own array of pointers that can be used as thread local
+ * storage.  configNUM_THREAD_LOCAL_STORAGE_POINTERS set the number of indexes
+ * in the array.  See
+ * https://www.freertos.org/thread-local-storage-pointers.html Defaults to 0 if
+ * left undefined. */
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS    0
+
+/* When configUSE_MINI_LIST_ITEM is set to 0, MiniListItem_t and ListItem_t are
+ * both the same. When configUSE_MINI_LIST_ITEM is set to 1, MiniListItem_t
+ * contains 3 fewer fields than ListItem_t which saves some RAM at the cost of
+ * violating strict aliasing rules which some compilers depend on for
+ * optimization. Defaults to 1 if left undefined. */
+#define configUSE_MINI_LIST_ITEM                   1
+
+/* Sets the type used by the parameter to xTaskCreate() that specifies the stack
+ * size of the task being created.  The same type is used to return information
+ * about stack usage in various other API calls.  Defaults to size_t if left
+ * undefined. */
+#define configSTACK_DEPTH_TYPE                     size_t
+
+/* configMESSAGE_BUFFER_LENGTH_TYPE sets the type used to store the length of
+ * each message written to a FreeRTOS message buffer (the length is also written
+ * to the message buffer.  Defaults to size_t if left undefined - but that may
+ * waste space if messages never go above a length that could be held in a
+ * uint8_t. */
+#define configMESSAGE_BUFFER_LENGTH_TYPE           size_t
+
+/* If configHEAP_CLEAR_MEMORY_ON_FREE is set to 1, then blocks of memory
+ * allocated using pvPortMalloc() will be cleared (i.e. set to zero) when freed
+ * using vPortFree(). Defaults to 0 if left undefined. */
+#define configHEAP_CLEAR_MEMORY_ON_FREE            1
+
+/* vTaskList and vTaskGetRunTimeStats APIs take a buffer as a parameter and
+ * assume that the length of the buffer is configSTATS_BUFFER_MAX_LENGTH.
+ * Defaults to 0xFFFF if left undefined. New applications are recommended to use
+ * vTaskListTasks and vTaskGetRunTimeStatistics APIs instead and supply the
+ * length of the buffer explicitly to avoid memory corruption. */
+#define configSTATS_BUFFER_MAX_LENGTH              0xFFFF
+
+/* Set configUSE_NEWLIB_REENTRANT to 1 to have a newlib reent structure
+ * allocated for each task.  Set to 0 to not support newlib reent structures.
+ * Default to 0 if left undefined.
+ *
+ * Note Newlib support has been included by popular demand, but is not used or
+ * tested by the FreeRTOS maintainers themselves. FreeRTOS is not responsible
+ * for resulting newlib operation. User must be familiar with newlib and must
+ * provide system-wide implementations of the necessary stubs. Note that (at the
+ * time of writing) the current newlib design implements a system-wide malloc()
+ * that must be provided with locks. */
+#define configUSE_NEWLIB_REENTRANT                 0
+
+/******************************************************************************/
+/* Software timer related definitions. ****************************************/
+/******************************************************************************/
+
+/* Set configUSE_TIMERS to 1 to include software timer functionality in the
+ * build.  Set to 0 to exclude software timer functionality from the build.  The
+ * FreeRTOS/source/timers.c source file must be included in the build if
+ * configUSE_TIMERS is set to 1.  Default to 0 if left undefined.  See
+ * https://www.freertos.org/RTOS-software-timer.html. */
+#define configUSE_TIMERS                1
+
+/* configTIMER_TASK_PRIORITY sets the priority used by the timer task.  Only
+ * used if configUSE_TIMERS is set to 1.  The timer task is a standard FreeRTOS
+ * task, so its priority is set like any other task.  See
+ * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html  Only
+ * used if configUSE_TIMERS is set to 1. */
+#define configTIMER_TASK_PRIORITY       ( configMAX_PRIORITIES - 1 )
+
+/* configTIMER_TASK_STACK_DEPTH sets the size of the stack allocated to the
+ * timer task (in words, not in bytes!).  The timer task is a standard FreeRTOS
+ * task.  See
+ * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html Only
+ * used if configUSE_TIMERS is set to 1. */
+#define configTIMER_TASK_STACK_DEPTH    configMINIMAL_STACK_SIZE
+
+/* configTIMER_QUEUE_LENGTH sets the length of the queue (the number of discrete
+ * items the queue can hold) used to send commands to the timer task.  See
+ * https://www.freertos.org/RTOS-software-timer-service-daemon-task.html  Only
+ * used if configUSE_TIMERS is set to 1. */
+#define configTIMER_QUEUE_LENGTH        10
+
+/******************************************************************************/
+/* Event Group related definitions. *******************************************/
+/******************************************************************************/
+
+/* Set configUSE_EVENT_GROUPS to 1 to include event group functionality in the
+ * build. Set to 0 to exclude event group functionality from the build. The
+ * FreeRTOS/source/event_groups.c source file must be included in the build if
+ * configUSE_EVENT_GROUPS is set to 1. Defaults to 1 if left undefined. */
+
+#define configUSE_EVENT_GROUPS    1
+
+/******************************************************************************/
+/* Stream Buffer related definitions. *****************************************/
+/******************************************************************************/
+
+/* Set configUSE_STREAM_BUFFERS to 1 to include stream buffer functionality in
+ * the build. Set to 0 to exclude event group functionality from the build. The
+ * FreeRTOS/source/stream_buffer.c source file must be included in the build if
+ * configUSE_STREAM_BUFFERS is set to 1. Defaults to 1 if left undefined. */
+
+#define configUSE_STREAM_BUFFERS    1
+
+/******************************************************************************/
+/* Memory allocation related definitions. *************************************/
+/******************************************************************************/
+
+/* Set configSUPPORT_STATIC_ALLOCATION to 1 to include FreeRTOS API functions
+ * that create FreeRTOS objects (tasks, queues, etc.) using statically allocated
+ * memory in the build.  Set to 0 to exclude the ability to create statically
+ * allocated objects from the build.  Defaults to 0 if left undefined.  See
+ * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html. */
+#define configSUPPORT_STATIC_ALLOCATION              1
+
+/* Set configSUPPORT_DYNAMIC_ALLOCATION to 1 to include FreeRTOS API functions
+ * that create FreeRTOS objects (tasks, queues, etc.) using dynamically
+ * allocated memory in the build.  Set to 0 to exclude the ability to create
+ * dynamically allocated objects from the build.  Defaults to 1 if left
+ * undefined.  See
+ * https://www.freertos.org/Static_Vs_Dynamic_Memory_Allocation.html. */
+#define configSUPPORT_DYNAMIC_ALLOCATION             1
+
+/* Sets the total size of the FreeRTOS heap, in bytes, when heap_1.c, heap_2.c
+ * or heap_4.c are included in the build.  This value is defaulted to 4096 bytes
+ * but it must be tailored to each application.  Note the heap will appear in
+ * the .bss section.  See https://www.freertos.org/a00111.html. */
+#define configTOTAL_HEAP_SIZE                        4096
+
+/* Set configAPPLICATION_ALLOCATED_HEAP to 1 to have the application allocate
+ * the array used as the FreeRTOS heap.  Set to 0 to have the linker allocate
+ * the array used as the FreeRTOS heap.  Defaults to 0 if left undefined. */
+#define configAPPLICATION_ALLOCATED_HEAP             0
+
+/* Set configSTACK_ALLOCATION_FROM_SEPARATE_HEAP to 1 to have task stacks
+ * allocated from somewhere other than the FreeRTOS heap.  This is useful if you
+ * want to ensure stacks are held in fast memory.  Set to 0 to have task stacks
+ * come from the standard FreeRTOS heap.  The application writer must provide
+ * implementations for pvPortMallocStack() and vPortFreeStack() if set to 1.
+ * Defaults to 0 if left undefined. */
+#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0
+
+/* Set configENABLE_HEAP_PROTECTOR to 1 to enable bounds checking and
+ * obfuscation to internal heap block pointers in heap_4.c and heap_5.c to help
+ * catch pointer corruptions. Defaults to 0 if left undefined. */
+#define configENABLE_HEAP_PROTECTOR                  0
+
+/******************************************************************************/
+/* Interrupt nesting behaviour configuration. *********************************/
+/******************************************************************************/
+
+/* configKERNEL_INTERRUPT_PRIORITY sets the priority of the tick and context
+ * switch performing interrupts.  Not supported by all FreeRTOS ports.  See
+ * https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific to
+ * ARM Cortex-M devices. */
+#define configKERNEL_INTERRUPT_PRIORITY          0
+
+/* configMAX_SYSCALL_INTERRUPT_PRIORITY sets the interrupt priority above which
+ * FreeRTOS API calls must not be made.  Interrupts above this priority are
+ * never disabled, so never delayed by RTOS activity.  The default value is set
+ * to the highest interrupt priority (0).  Not supported by all FreeRTOS ports.
+ * See https://www.freertos.org/RTOS-Cortex-M3-M4.html for information specific
+ * to ARM Cortex-M devices. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY     0
+
+/* Another name for configMAX_SYSCALL_INTERRUPT_PRIORITY - the name used depends
+ * on the FreeRTOS port. */
+#define configMAX_API_CALL_INTERRUPT_PRIORITY    0
+
+/******************************************************************************/
+/* Hook and callback function related definitions. ****************************/
+/******************************************************************************/
+
+/* Set the following configUSE_* constants to 1 to include the named hook
+ * functionality in the build.  Set to 0 to exclude the hook functionality from
+ * the build.  The application writer is responsible for providing the hook
+ * function for any set to 1.  See https://www.freertos.org/a00016.html. */
+#define configUSE_IDLE_HOOK                   0
+#define configUSE_TICK_HOOK                   0
+#define configUSE_MALLOC_FAILED_HOOK          0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK    0
+
+/* Set configUSE_SB_COMPLETED_CALLBACK to 1 to have send and receive completed
+ * callbacks for each instance of a stream buffer or message buffer. When the
+ * option is set to 1, APIs xStreamBufferCreateWithCallback() and
+ * xStreamBufferCreateStaticWithCallback() (and likewise APIs for message
+ * buffer) can be used to create a stream buffer or message buffer instance
+ * with application provided callbacks. Defaults to 0 if left undefined. */
+#define configUSE_SB_COMPLETED_CALLBACK       0
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 1 or 2 for FreeRTOS to check for a
+ * stack overflow at the time of a context switch.  Set to 0 to not look for a
+ * stack overflow.  If configCHECK_FOR_STACK_OVERFLOW is 1 then the check only
+ * looks for the stack pointer being out of bounds when a task's context is
+ * saved to its stack - this is fast but somewhat ineffective.  If
+ * configCHECK_FOR_STACK_OVERFLOW is 2 then the check looks for a pattern
+ * written to the end of a task's stack having been overwritten.  This is
+ * slower, but will catch most (but not all) stack overflows.  The application
+ * writer must provide the stack overflow callback when
+ * configCHECK_FOR_STACK_OVERFLOW is set to 1. See
+ * https://www.freertos.org/Stacks-and-stack-overflow-checking.html  Defaults to
+ * 0 if left undefined. */
+#define configCHECK_FOR_STACK_OVERFLOW        2
+
+/******************************************************************************/
+/* Run time and task stats gathering related definitions. *********************/
+/******************************************************************************/
+
+/* Set configGENERATE_RUN_TIME_STATS to 1 to have FreeRTOS collect data on the
+ * processing time used by each task.  Set to 0 to not collect the data.  The
+ * application writer needs to provide a clock source if set to 1.  Defaults to
+ * 0 if left undefined.  See https://www.freertos.org/rtos-run-time-stats.html.
+ */
+#define configGENERATE_RUN_TIME_STATS           0
+
+/* Set configUSE_TRACE_FACILITY to include additional task structure members
+ * are used by trace and visualisation functions and tools.  Set to 0 to exclude
+ * the additional information from the structures. Defaults to 0 if left
+ * undefined. */
+#define configUSE_TRACE_FACILITY                0
+
+/* Set to 1 to include the vTaskList() and vTaskGetRunTimeStats() functions in
+ * the build.  Set to 0 to exclude these functions from the build.  These two
+ * functions introduce a dependency on string formatting functions that would
+ * otherwise not exist - hence they are kept separate.  Defaults to 0 if left
+ * undefined. */
+#define configUSE_STATS_FORMATTING_FUNCTIONS    0
+
+/******************************************************************************/
+/* Co-routine related definitions. ********************************************/
+/******************************************************************************/
+
+/* Set configUSE_CO_ROUTINES to 1 to include co-routine functionality in the
+ * build, or 0 to omit co-routine functionality from the build. To include
+ * co-routines, croutine.c must be included in the project. Defaults to 0 if
+ * left undefined. */
+#define configUSE_CO_ROUTINES              0
+
+/* configMAX_CO_ROUTINE_PRIORITIES defines the number of priorities available
+ * to the application co-routines. Any number of co-routines can share the same
+ * priority. Defaults to 0 if left undefined. */
+#define configMAX_CO_ROUTINE_PRIORITIES    1
+
+/******************************************************************************/
+/* Debugging assistance. ******************************************************/
+/******************************************************************************/
+
+/* configASSERT() has the same semantics as the standard C assert().  It can
+ * either be defined to take an action when the assertion fails, or not defined
+ * at all (i.e. comment out or delete the definitions) to completely remove
+ * assertions.  configASSERT() can be defined to anything you want, for example
+ * you can call a function if an assert fails that passes the filename and line
+ * number of the failing assert (for example, "vAssertCalled( __FILE__, __LINE__
+ * )" or it can simple disable interrupts and sit in a loop to halt all
+ * execution on the failing line for viewing in a debugger. */
+#define configASSERT( x )         \
+    if( ( x ) == 0 )              \
+    {                             \
+        taskDISABLE_INTERRUPTS(); \
+        for( ; ; )                \
+        ;                         \
+    }
+
+/******************************************************************************/
+/* FreeRTOS MPU specific definitions. *****************************************/
+/******************************************************************************/
+
+/* If configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS is set to 1 then
+ * the application writer can provide functions that execute in privileged mode.
+ * See:
+ * https://www.freertos.org/a00110.html#configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+ * Defaults to 0 if left undefined.  Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port. */
+#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS    0
+
+/* Set configTOTAL_MPU_REGIONS to the number of MPU regions implemented on your
+ * target hardware.  Normally 8 or 16.  Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port.  Defaults to 8 if left
+ * undefined. */
+#define configTOTAL_MPU_REGIONS                                   8
+
+/* configTEX_S_C_B_FLASH allows application writers to override the default
+ * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits
+ * for the MPU region covering Flash.  Defaults to 0x07UL (which means TEX=000,
+ * S=1, C=1, B=1) if left undefined.  Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port. */
+#define configTEX_S_C_B_FLASH                                     0x07UL
+
+/* configTEX_S_C_B_SRAM allows application writers to override the default
+ * values for the for TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits
+ * for the MPU region covering RAM. Defaults to 0x07UL (which means TEX=000,
+ * S=1, C=1, B=1) if left undefined.  Only used by the FreeRTOS Cortex-M MPU
+ * ports, not the standard ARMv7-M Cortex-M port. */
+#define configTEX_S_C_B_SRAM                                      0x07UL
+
+/* Set configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY to 0 to prevent any privilege
+ * escalations originating from outside of the kernel code itself.  Set to 1 to
+ * allow application tasks to raise privilege.  Defaults to 1 if left undefined.
+ * Only used by the FreeRTOS Cortex-M MPU ports, not the standard ARMv7-M
+ * Cortex-M port. */
+#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY               1
+
+/* Set configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS to 1 to allow unprivileged
+ * tasks enter critical sections (effectively mask interrupts). Set to 0 to
+ * prevent unprivileged tasks entering critical sections.  Defaults to 1 if left
+ * undefined.  Only used by the FreeRTOS Cortex-M MPU ports, not the standard
+ * ARMv7-M Cortex-M port. */
+#define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS                0
+
+/* FreeRTOS Kernel version 10.6.0 introduced a new v2 MPU wrapper, namely
+ * mpu_wrappers_v2.c. Set configUSE_MPU_WRAPPERS_V1 to 0 to use the new v2 MPU
+ * wrapper. Set configUSE_MPU_WRAPPERS_V1 to 1 to use the old v1 MPU wrapper
+ * (mpu_wrappers.c). Defaults to 0 if left undefined. */
+#define configUSE_MPU_WRAPPERS_V1                                 0
+
+/* When using the v2 MPU wrapper, set configPROTECTED_KERNEL_OBJECT_POOL_SIZE to
+ * the total number of kernel objects, which includes tasks, queues, semaphores,
+ * mutexes, event groups, timers, stream buffers and message buffers, in your
+ * application. The application will not be able to have more than
+ * configPROTECTED_KERNEL_OBJECT_POOL_SIZE kernel objects at any point of
+ * time. */
+#define configPROTECTED_KERNEL_OBJECT_POOL_SIZE                   10
+
+/* When using the v2 MPU wrapper, set configSYSTEM_CALL_STACK_SIZE to the size
+ * of the system call stack in words. Each task has a statically allocated
+ * memory buffer of this size which is used as the stack to execute system
+ * calls. For example, if configSYSTEM_CALL_STACK_SIZE is defined as 128 and
+ * there are 10 tasks in the application, the total amount of memory used for
+ * system call stacks is 128 * 10 = 1280 words. */
+#define configSYSTEM_CALL_STACK_SIZE                              128
+
+/* When using the v2 MPU wrapper, set configENABLE_ACCESS_CONTROL_LIST to 1 to
+ * enable Access Control List (ACL) feature. When ACL is enabled, an
+ * unprivileged task by default does not have access to any kernel object other
+ * than itself. The application writer needs to explicitly grant the
+ * unprivileged task access to the kernel objects it needs using the APIs
+ * provided for the same. Defaults to 0 if left undefined. */
+#define configENABLE_ACCESS_CONTROL_LIST                          1
+
+/******************************************************************************/
+/* SMP( Symmetric MultiProcessing ) Specific Configuration definitions. *******/
+/******************************************************************************/
+
+/* Set configNUMBER_OF_CORES to the number of available processor cores.
+ * Defaults to 1 if left undefined. */
+
+/*
+ #define configNUMBER_OF_CORES                     [Num of available cores]
+ */
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set
+ * configRUN_MULTIPLE_PRIORITIES to 0 to allow multiple tasks to run
+ * simultaneously only if they do not have equal priority, thereby maintaining
+ * the paradigm of a lower priority task never running if a higher priority task
+ * is able to run. If configRUN_MULTIPLE_PRIORITIES is set to 1, multiple tasks
+ * with different priorities may run simultaneously - so a higher and lower
+ * priority task may run on different cores at the same time. */
+#define configRUN_MULTIPLE_PRIORITIES             0
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set
+ * configUSE_CORE_AFFINITY to 1 to enable core affinity feature. When core
+ * affinity feature is enabled, the vTaskCoreAffinitySet and
+ * vTaskCoreAffinityGet APIs can be used to set and retrieve which cores a task
+ * can run on. If configUSE_CORE_AFFINITY is set to 0 then the FreeRTOS
+ * scheduler is free to run any task on any available core. */
+#define configUSE_CORE_AFFINITY                   0
+
+/* When using SMP with core affinity feature enabled, set
+ * configTASK_DEFAULT_CORE_AFFINITY to change the default core affinity mask for
+ * tasks created without an affinity mask specified. Setting the define to 1
+ * would make such tasks run on core 0 and setting it to (1 <<
+ * portGET_CORE_ID()) would make such tasks run on the current core. This config
+ * value is useful, if swapping tasks between cores is not supported (e.g.
+ * Tricore) or if legacy code should be controlled. Defaults to tskNO_AFFINITY
+ * if left undefined. */
+#define configTASK_DEFAULT_CORE_AFFINITY          tskNO_AFFINITY
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), if
+ * configUSE_TASK_PREEMPTION_DISABLE is set to 1, individual tasks can be set to
+ * either pre-emptive or co-operative mode using the vTaskPreemptionDisable and
+ * vTaskPreemptionEnable APIs. */
+#define configUSE_TASK_PREEMPTION_DISABLE         0
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one), set
+ * configUSE_PASSIVE_IDLE_HOOK to 1 to allow the application writer to use
+ * the passive idle task hook to add background functionality without the
+ * overhead of a separate task. Defaults to 0 if left undefined. */
+#define configUSE_PASSIVE_IDLE_HOOK               0
+
+/* When using SMP (i.e. configNUMBER_OF_CORES is greater than one),
+ * configTIMER_SERVICE_TASK_CORE_AFFINITY allows the application writer to set
+ * the core affinity of the RTOS Daemon/Timer Service task. Defaults to
+ * tskNO_AFFINITY if left undefined. */
+#define configTIMER_SERVICE_TASK_CORE_AFFINITY    tskNO_AFFINITY
+
+/******************************************************************************/
+/* ARMv8-M secure side port related definitions. ******************************/
+/******************************************************************************/
+
+/* secureconfigMAX_SECURE_CONTEXTS define the maximum number of tasks that can
+ *  call into the secure side of an ARMv8-M chip.  Not used by any other ports.
+ */
+#define secureconfigMAX_SECURE_CONTEXTS        5
+
+/* Defines the kernel provided implementation of
+ * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory()
+ * to provide the memory that is used by the Idle task and Timer task
+ * respectively. The application can provide it's own implementation of
+ * vApplicationGetIdleTaskMemory() and vApplicationGetTimerTaskMemory() by
+ * setting configKERNEL_PROVIDED_STATIC_MEMORY to 0 or leaving it undefined. */
+#define configKERNEL_PROVIDED_STATIC_MEMORY    1
+
+/******************************************************************************/
+/* ARMv8-M port Specific Configuration definitions. ***************************/
+/******************************************************************************/
+
+/* Set configENABLE_TRUSTZONE to 1 when running FreeRTOS on the non-secure side
+ * to enable the TrustZone support in FreeRTOS ARMv8-M ports which allows the
+ * non-secure FreeRTOS tasks to call the (non-secure callable) functions
+ * exported from secure side. */
+#define configENABLE_TRUSTZONE            1
+
+/* If the application writer does not want to use TrustZone, but the hardware
+ * does not support disabling TrustZone then the entire application (including
+ * the FreeRTOS scheduler) can run on the secure side without ever branching to
+ * the non-secure side. To do that, in addition to setting
+ * configENABLE_TRUSTZONE to 0, also set configRUN_FREERTOS_SECURE_ONLY to 1. */
+#define configRUN_FREERTOS_SECURE_ONLY    1
+
+/* Set configENABLE_MPU to 1 to enable the Memory Protection Unit (MPU), or 0
+ * to leave the Memory Protection Unit disabled. */
+#define configENABLE_MPU                  1
+
+/* Set configENABLE_FPU to 1 to enable the Floating Point Unit (FPU), or 0
+ * to leave the Floating Point Unit disabled. */
+#define configENABLE_FPU                  1
+
+/* Set configENABLE_MVE to 1 to enable the M-Profile Vector Extension (MVE)
+ * support, or 0 to leave the MVE support disabled. This option is only
+ * applicable to Cortex-M55 and Cortex-M85 ports as M-Profile Vector Extension
+ * (MVE) is available only on these architectures. configENABLE_MVE must be left
+ * undefined, or defined to 0 for the Cortex-M23,Cortex-M33 and Cortex-M35P
+ * ports. */
+#define configENABLE_MVE                  1
+
+/******************************************************************************/
+/* ARMv7-M and ARMv8-M port Specific Configuration definitions. ***************/
+/******************************************************************************/
+
+/* Set configCHECK_HANDLER_INSTALLATION to 1 to enable additional asserts to
+ * verify that the application has correctly installed FreeRTOS interrupt
+ * handlers.
+ *
+ * An application can install FreeRTOS interrupt handlers in one of the
+ * following ways:
+ *   1. Direct Routing  -  Install the functions vPortSVCHandler and
+ * xPortPendSVHandler for SVC call and PendSV interrupts respectively.
+ *   2. Indirect Routing - Install separate handlers for SVC call and PendSV
+ *                         interrupts and route program control from those
+ * handlers to vPortSVCHandler and xPortPendSVHandler functions. The
+ * applications that use Indirect Routing must set
+ * configCHECK_HANDLER_INSTALLATION to 0.
+ *
+ * Defaults to 1 if left undefined. */
+#define configCHECK_HANDLER_INSTALLATION    1
+
+/******************************************************************************/
+/* Definitions that include or exclude functionality. *************************/
+/******************************************************************************/
+
+/* Set the following configUSE_* constants to 1 to include the named feature in
+ * the build, or 0 to exclude the named feature from the build. */
+#define configUSE_TASK_NOTIFICATIONS           1
+#define configUSE_MUTEXES                      1
+#define configUSE_RECURSIVE_MUTEXES            1
+#define configUSE_COUNTING_SEMAPHORES          1
+#define configUSE_QUEUE_SETS                   0
+#define configUSE_APPLICATION_TASK_TAG         0
+
+/* USE_POSIX_ERRNO enables the task global FreeRTOS_errno variable which will
+ * contain the most recent error for that task. */
+#define configUSE_POSIX_ERRNO                  0
+
+/* Set the following INCLUDE_* constants to 1 to include the named API function,
+ * or 0 to exclude the named API function.  Most linkers will remove unused
+ * functions even when the constant is 1. */
+#define INCLUDE_vTaskPrioritySet               1
+#define INCLUDE_uxTaskPriorityGet              1
+#define INCLUDE_vTaskDelete                    1
+#define INCLUDE_vTaskSuspend                   1
+#define INCLUDE_vTaskDelayUntil                1
+#define INCLUDE_vTaskDelay                     1
+#define INCLUDE_xTaskGetSchedulerState         1
+#define INCLUDE_xTaskGetCurrentTaskHandle      1
+#define INCLUDE_uxTaskGetStackHighWaterMark    0
+#define INCLUDE_xTaskGetIdleTaskHandle         0
+#define INCLUDE_eTaskGetState                  0
+#define INCLUDE_xTimerPendFunctionCall         0
+#define INCLUDE_xTaskAbortDelay                0
+#define INCLUDE_xTaskGetHandle                 0
+#define INCLUDE_xTaskResumeFromISR             1
+
+#endif /* FREERTOS_CONFIG_H */

examples/template_configuration/readme.md

@@ -0,0 +1,7 @@
+# Configuration support for FreeRTOS
+
+## Overview
+
+Every FreeRTOS project requires FreeRTOSConfig.h located in their include path.  In this folder you will find a sample FreeRTOSConfig.h that will assist you in preparing the configuration for your application.
+
+The FreeRTOSConfig.h in this folder is used in the minimal_freertos_example project provided and it not guaranteed to have the same configuration between updates.

include/StackMacros.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *

include/atomic.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -33,6 +33,14 @@
  * This file implements atomic functions by disabling interrupts globally.
  * Implementations with architecture specific atomic instructions can be
  * provided under each compiler directory.
+ *
+ * The atomic interface can be used in FreeRTOS tasks on all FreeRTOS ports. It
+ * can also be used in Interrupt Service Routines (ISRs) on FreeRTOS ports that
+ * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 1). The
+ * atomic interface must not be used in ISRs on FreeRTOS ports that do not
+ * support nested interrupts (i.e. portHAS_NESTED_INTERRUPTS is set to 0)
+ * because ISRs on these ports cannot be interrupted and therefore, do not need
+ * atomics in ISRs.
  */
 
 #ifndef ATOMIC_H
@@ -59,7 +67,7 @@
  * ATOMIC_ENTER_CRITICAL().
  *
  */
-#if defined( portSET_INTERRUPT_MASK_FROM_ISR )
+#if ( portHAS_NESTED_INTERRUPTS == 1 )
 
 /* Nested interrupt scheme is supported in this port. */
     #define ATOMIC_ENTER_CRITICAL() \

include/croutine.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -47,8 +47,8 @@
 typedef void * CoRoutineHandle_t;
 
 /* Defines the prototype to which co-routine functions must conform. */
-typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t,
-                                   UBaseType_t );
+typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t xHandle,
+                                   UBaseType_t uxIndex );
 
 typedef struct corCoRoutineControlBlock
 {
@@ -746,6 +746,13 @@ void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
  */
 BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList );
 
+
+/*
+ * This function resets the internal state of the coroutine module. It must be
+ * called by the application before restarting the scheduler.
+ */
+void vCoRoutineResetState( void ) PRIVILEGED_FUNCTION;
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }

include/deprecated_definitions.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *

include/event_groups.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -36,6 +36,26 @@
 /* FreeRTOS includes. */
 #include "timers.h"
 
+/* The following bit fields convey control information in a task's event list
+ * item value.  It is important they don't clash with the
+ * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
+#if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint16_t ) 0x0100U )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint16_t ) 0x0200U )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint16_t ) 0x0400U )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint16_t ) 0xff00U )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_32_BITS )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint32_t ) 0x01000000U )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint32_t ) 0x02000000U )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint32_t ) 0x04000000U )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint32_t ) 0xff000000U )
+#elif ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_64_BITS )
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    ( ( uint64_t ) 0x0100000000000000U )
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    ( ( uint64_t ) 0x0200000000000000U )
+    #define eventWAIT_FOR_ALL_BITS           ( ( uint64_t ) 0x0400000000000000U )
+    #define eventEVENT_BITS_CONTROL_BYTES    ( ( uint64_t ) 0xff00000000000000U )
+#endif /* if ( configTICK_TYPE_WIDTH_IN_BITS == TICK_TYPE_WIDTH_16_BITS ) */
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     extern "C" {
@@ -119,6 +139,9 @@ typedef TickType_t               EventBits_t;
  * each event group has 56 usable bits (bit 0 to bit 53). The EventBits_t type
  * is used to store event bits within an event group.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupCreate()
+ * to be available.
+ *
  * @return If the event group was created then a handle to the event group is
  * returned.  If there was insufficient FreeRTOS heap available to create the
  * event group then NULL is returned.  See https://www.FreeRTOS.org/a00111.html
@@ -176,6 +199,9 @@ typedef TickType_t               EventBits_t;
  * each event group has 56 usable bits (bit 0 to bit 53).  The EventBits_t type
  * is used to store event bits within an event group.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupCreateStatic()
+ * to be available.
+ *
  * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
  * StaticEventGroup_t, which will be then be used to hold the event group's data
  * structures, removing the need for the memory to be allocated dynamically.
@@ -218,6 +244,9 @@ typedef TickType_t               EventBits_t;
  *
  * This function cannot be called from an interrupt.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupWaitBits()
+ * to be available.
+ *
  * @param xEventGroup The event group in which the bits are being tested.  The
  * event group must have previously been created using a call to
  * xEventGroupCreate().
@@ -311,6 +340,9 @@ EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
  * Clear bits within an event group.  This function cannot be called from an
  * interrupt.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupClearBits()
+ * to be available.
+ *
  * @param xEventGroup The event group in which the bits are to be cleared.
  *
  * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
@@ -441,6 +473,9 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
  * Setting bits in an event group will automatically unblock tasks that are
  * blocked waiting for the bits.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupSetBits()
+ * to be available.
+ *
  * @param xEventGroup The event group in which the bits are to be set.
  *
  * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
@@ -448,14 +483,11 @@ EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
  * and bit 0 set uxBitsToSet to 0x09.
  *
  * @return The value of the event group at the time the call to
- * xEventGroupSetBits() returns.  There are two reasons why the returned value
- * might have the bits specified by the uxBitsToSet parameter cleared.  First,
- * if setting a bit results in a task that was waiting for the bit leaving the
- * blocked state then it is possible the bit will be cleared automatically
- * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
- * unblocked (or otherwise Ready state) task that has a priority above that of
- * the task that called xEventGroupSetBits() will execute and may change the
- * event group value before the call to xEventGroupSetBits() returns.
+ * xEventGroupSetBits() returns.  Returned value might have the bits specified
+ * by the uxBitsToSet parameter cleared if setting a bit results in a task
+ * that was waiting for the bit leaving the blocked state then it is possible
+ * the bit will be cleared automatically (see the xClearBitOnExit parameter
+ * of xEventGroupWaitBits()).
  *
  * Example usage:
  * @code{c}
@@ -605,6 +637,9 @@ EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
  * this case all the bits specified by uxBitsToWait will be automatically
  * cleared before the function returns.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupSync()
+ * to be available.
+ *
  * @param xEventGroup The event group in which the bits are being tested.  The
  * event group must have previously been created using a call to
  * xEventGroupCreate().
@@ -723,6 +758,9 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
  * Returns the current value of the bits in an event group.  This function
  * cannot be used from an interrupt.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetBits()
+ * to be available.
+ *
  * @param xEventGroup The event group being queried.
  *
  * @return The event group bits at the time xEventGroupGetBits() was called.
@@ -740,6 +778,9 @@ EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
  *
  * A version of xEventGroupGetBits() that can be called from an ISR.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetBitsFromISR()
+ * to be available.
+ *
  * @param xEventGroup The event group being queried.
  *
  * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
@@ -759,6 +800,9 @@ EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEG
  * xEventGroupCreate().  Tasks that are blocked on the event group will be
  * unblocked and obtain 0 as the event group's value.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for vEventGroupDelete()
+ * to be available.
+ *
  * @param xEventGroup The event group being deleted.
  */
 void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
@@ -773,6 +817,9 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
  * Retrieve a pointer to a statically created event groups's data structure
  * buffer. It is the same buffer that is supplied at the time of creation.
  *
+ * The configUSE_EVENT_GROUPS configuration constant must be set to 1 for xEventGroupGetStaticBuffer()
+ * to be available.
+ *
  * @param xEventGroup The event group for which to retrieve the buffer.
  *
  * @param ppxEventGroupBuffer Used to return a pointer to the event groups's
@@ -787,9 +834,9 @@ void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
 
 /* For internal use only. */
 void vEventGroupSetBitsCallback( void * pvEventGroup,
-                                 const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
+                                 uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
 void vEventGroupClearBitsCallback( void * pvEventGroup,
-                                   const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+                                   uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
 
 
 #if ( configUSE_TRACE_FACILITY == 1 )

include/list.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -151,7 +151,7 @@ struct xLIST_ITEM
     struct xLIST * configLIST_VOLATILE pxContainer;     /**< Pointer to the list in which this list item is placed (if any). */
     listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE          /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
 };
-typedef struct xLIST_ITEM ListItem_t;                   /* For some reason lint wants this as two separate definitions. */
+typedef struct xLIST_ITEM ListItem_t;
 
 #if ( configUSE_MINI_LIST_ITEM == 1 )
     struct xMINI_LIST_ITEM
@@ -172,7 +172,7 @@ typedef struct xLIST_ITEM ListItem_t;                   /* For some reason lint
 typedef struct xLIST
 {
     listFIRST_LIST_INTEGRITY_CHECK_VALUE      /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-    volatile UBaseType_t uxNumberOfItems;
+    configLIST_VOLATILE UBaseType_t uxNumberOfItems;
     ListItem_t * configLIST_VOLATILE pxIndex; /**< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
     MiniListItem_t xListEnd;                  /**< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
     listSECOND_LIST_INTEGRITY_CHECK_VALUE     /**< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
@@ -282,7 +282,8 @@ typedef struct xLIST
  * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
  * \ingroup LinkedList
  */
-#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )                                           \
+#if ( configNUMBER_OF_CORES == 1 )
+    #define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )                                       \
     do {                                                                                       \
         List_t * const pxConstList = ( pxList );                                               \
         /* Increment the index to the next item and return the item, ensuring */               \
@@ -294,6 +295,13 @@ typedef struct xLIST
         }                                                                                      \
         ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;                                         \
     } while( 0 )
+#else /* #if ( configNUMBER_OF_CORES == 1 ) */
+
+/* This function is not required in SMP. FreeRTOS SMP scheduler doesn't use
+ * pxIndex and it should always point to the xListEnd. Not defining this macro
+ * here to prevent updating pxIndex.
+ */
+#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
 /*
  * Version of uxListRemove() that does not return a value.  Provided as a slight
@@ -314,19 +322,19 @@ typedef struct xLIST
 #define listREMOVE_ITEM( pxItemToRemove ) \
     do {                                  \
         /* The list item knows which list it is in.  Obtain the list from the list \
-         * item. */                                                              \
-        List_t * const pxList = ( pxItemToRemove )->pxContainer;                 \
-                                                                                 \
-        ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; \
-        ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext;     \
-        /* Make sure the index is left pointing to a valid item. */              \
-        if( pxList->pxIndex == ( pxItemToRemove ) )                              \
-        {                                                                        \
-            pxList->pxIndex = ( pxItemToRemove )->pxPrevious;                    \
-        }                                                                        \
-                                                                                 \
-        ( pxItemToRemove )->pxContainer = NULL;                                  \
-        ( pxList->uxNumberOfItems )--;                                           \
+         * item. */                                                                                 \
+        List_t * const pxList = ( pxItemToRemove )->pxContainer;                                    \
+                                                                                                    \
+        ( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious;                    \
+        ( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext;                        \
+        /* Make sure the index is left pointing to a valid item. */                                 \
+        if( pxList->pxIndex == ( pxItemToRemove ) )                                                 \
+        {                                                                                           \
+            pxList->pxIndex = ( pxItemToRemove )->pxPrevious;                                       \
+        }                                                                                           \
+                                                                                                    \
+        ( pxItemToRemove )->pxContainer = NULL;                                                     \
+        ( ( pxList )->uxNumberOfItems ) = ( UBaseType_t ) ( ( ( pxList )->uxNumberOfItems ) - 1U ); \
     } while( 0 )
 
 /*
@@ -363,17 +371,17 @@ typedef struct xLIST
                                                                                 \
         /* Insert a new list item into ( pxList ), but rather than sort the list, \
          * makes the new list item the last item to be removed by a call to \
-         * listGET_OWNER_OF_NEXT_ENTRY(). */                 \
-        ( pxNewListItem )->pxNext = pxIndex;                 \
-        ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; \
-                                                             \
-        pxIndex->pxPrevious->pxNext = ( pxNewListItem );     \
-        pxIndex->pxPrevious = ( pxNewListItem );             \
-                                                             \
-        /* Remember which list the item is in. */            \
-        ( pxNewListItem )->pxContainer = ( pxList );         \
-                                                             \
-        ( ( pxList )->uxNumberOfItems )++;                   \
+         * listGET_OWNER_OF_NEXT_ENTRY(). */                                                        \
+        ( pxNewListItem )->pxNext = pxIndex;                                                        \
+        ( pxNewListItem )->pxPrevious = pxIndex->pxPrevious;                                        \
+                                                                                                    \
+        pxIndex->pxPrevious->pxNext = ( pxNewListItem );                                            \
+        pxIndex->pxPrevious = ( pxNewListItem );                                                    \
+                                                                                                    \
+        /* Remember which list the item is in. */                                                   \
+        ( pxNewListItem )->pxContainer = ( pxList );                                                \
+                                                                                                    \
+        ( ( pxList )->uxNumberOfItems ) = ( UBaseType_t ) ( ( ( pxList )->uxNumberOfItems ) + 1U ); \
     } while( 0 )
 
 /*

include/message_buffer.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -43,12 +43,12 @@
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * timeout to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Message buffers hold variable length messages.  To enable that, when a
  * message is written to the message buffer an additional sizeof( size_t ) bytes
@@ -100,6 +100,8 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
  * FreeRTOSConfig.h for xMessageBufferCreate() to be available.
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferCreate() to be available.
  *
  * @param xBufferSizeBytes The total number of bytes (not messages) the message
  * buffer will be able to hold at any one time.  When a message is written to
@@ -156,11 +158,11 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * \ingroup MessageBufferManagement
  */
 #define xMessageBufferCreate( xBufferSizeBytes ) \
-    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, NULL, NULL )
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, sbTYPE_MESSAGE_BUFFER, NULL, NULL )
 
 #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
     #define xMessageBufferCreateWithCallback( xBufferSizeBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
-    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, pdTRUE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( size_t ) 0, sbTYPE_MESSAGE_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
 #endif
 
 /**
@@ -168,12 +170,15 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * @code{c}
  * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
- *                                                uint8_t *pucMessageBufferStorageArea,
- *                                                StaticMessageBuffer_t *pxStaticMessageBuffer );
+ *                                                   uint8_t *pucMessageBufferStorageArea,
+ *                                                   StaticMessageBuffer_t *pxStaticMessageBuffer );
  * @endcode
  * Creates a new message buffer using statically allocated memory.  See
  * xMessageBufferCreate() for a version that uses dynamically allocated memory.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferCreateStatic() to be available.
+ *
  * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
  * pucMessageBufferStorageArea parameter.  When a message is written to the
  * message buffer an additional sizeof( size_t ) bytes are also written to store
@@ -238,11 +243,11 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * \ingroup MessageBufferManagement
  */
 #define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \
-    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL )
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, sbTYPE_MESSAGE_BUFFER, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), NULL, NULL )
 
 #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
     #define xMessageBufferCreateStaticWithCallback( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
-    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, pdTRUE, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), 0, sbTYPE_MESSAGE_BUFFER, ( pucMessageBufferStorageArea ), ( pxStaticMessageBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
 #endif
 
 /**
@@ -258,6 +263,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * buffer and storage area buffer. These are the same buffers that are supplied
  * at the time of creation.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferGetStaticBuffers() to be available.
+ *
  * @param xMessageBuffer The message buffer for which to retrieve the buffers.
  *
  * @param ppucMessageBufferStorageArea Used to return a pointer to the
@@ -281,9 +289,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * @code{c}
  * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
- *                         const void *pvTxData,
- *                         size_t xDataLengthBytes,
- *                         TickType_t xTicksToWait );
+ *                            const void *pvTxData,
+ *                            size_t xDataLengthBytes,
+ *                            TickType_t xTicksToWait );
  * @endcode
  *
  * Sends a discrete message to the message buffer.  The message can be any
@@ -298,17 +306,20 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xMessageBufferSend() to write to a message buffer from a task.  Use
  * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
  * service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSend() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer to which a message is
  * being sent.
  *
@@ -381,9 +392,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * @code{c}
  * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
- *                                const void *pvTxData,
- *                                size_t xDataLengthBytes,
- *                                BaseType_t *pxHigherPriorityTaskWoken );
+ *                                   const void *pvTxData,
+ *                                   size_t xDataLengthBytes,
+ *                                   BaseType_t *pxHigherPriorityTaskWoken );
  * @endcode
  *
  * Interrupt safe version of the API function that sends a discrete message to
@@ -398,17 +409,20 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xMessageBufferSend() to write to a message buffer from a task.  Use
  * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
  * service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSendFromISR() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer to which a message is
  * being sent.
  *
@@ -486,9 +500,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * @code{c}
  * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
- *                            void *pvRxData,
- *                            size_t xBufferLengthBytes,
- *                            TickType_t xTicksToWait );
+ *                               void *pvRxData,
+ *                               size_t xBufferLengthBytes,
+ *                               TickType_t xTicksToWait );
  * @endcode
  *
  * Receives a discrete message from a message buffer.  Messages can be of
@@ -502,17 +516,20 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
  * xMessageBufferReceiveFromISR() to read from a message buffer from an
  * interrupt service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReceive() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer from which a message
  * is being received.
  *
@@ -576,9 +593,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * @code{c}
  * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
- *                                   void *pvRxData,
- *                                   size_t xBufferLengthBytes,
- *                                   BaseType_t *pxHigherPriorityTaskWoken );
+ *                                      void *pvRxData,
+ *                                      size_t xBufferLengthBytes,
+ *                                      BaseType_t *pxHigherPriorityTaskWoken );
  * @endcode
  *
  * An interrupt safe version of the API function that receives a discrete
@@ -593,17 +610,20 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
  * xMessageBufferReceiveFromISR() to read from a message buffer from an
  * interrupt service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReceiveFromISR() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer from which a message
  * is being received.
  *
@@ -687,6 +707,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * A message buffer handle must not be used after the message buffer has been
  * deleted.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * vMessageBufferDelete() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer to be deleted.
  *
  */
@@ -703,6 +726,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * cannot accept any more messages, of any size, until space is made available
  * by a message being removed from the message buffer.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferIsFull() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer being queried.
  *
  * @return If the message buffer referenced by xMessageBuffer is full then
@@ -719,6 +745,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * Tests to see if a message buffer is empty (does not contain any messages).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferIsEmpty() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer being queried.
  *
  * @return If the message buffer referenced by xMessageBuffer is empty then
@@ -739,6 +768,13 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  *
  * A message buffer can only be reset if there are no tasks blocked on it.
  *
+ * Use xMessageBufferReset() to reset a message buffer from a task.
+ * Use xMessageBufferResetFromISR() to reset a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReset() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer being reset.
  *
  * @return If the message buffer was reset then pdPASS is returned.  If the
@@ -753,6 +789,38 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
     xStreamBufferReset( xMessageBuffer )
 
 
+/**
+ * message_buffer.h
+ * @code{c}
+ * BaseType_t xMessageBufferResetFromISR( MessageBufferHandle_t xMessageBuffer );
+ * @endcode
+ *
+ * An interrupt safe version of the API function that resets the message buffer.
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * Use xMessageBufferReset() to reset a message buffer from a task.
+ * Use xMessageBufferResetFromISR() to reset a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferResetFromISR() to be available.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferResetFromISR xMessageBufferResetFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferResetFromISR( xMessageBuffer ) \
+    xStreamBufferResetFromISR( xMessageBuffer )
+
 /**
  * message_buffer.h
  * @code{c}
@@ -760,6 +828,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * @endcode
  * Returns the number of bytes of free space in the message buffer.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSpaceAvailable() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer being queried.
  *
  * @return The number of bytes that can be written to the message buffer before
@@ -786,6 +857,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
  * passed into xMessageBufferReceive() was too small to hold the next message.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferNextLengthBytes() to be available.
+ *
  * @param xMessageBuffer The handle of the message buffer being queried.
  *
  * @return The length (in bytes) of the next message in the message buffer, or 0
@@ -795,7 +869,7 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * \ingroup MessageBufferManagement
  */
 #define xMessageBufferNextLengthBytes( xMessageBuffer ) \
-    xStreamBufferNextMessageLengthBytes( xMessageBuffer ) PRIVILEGED_FUNCTION;
+    xStreamBufferNextMessageLengthBytes( xMessageBuffer )
 
 /**
  * message_buffer.h
@@ -817,6 +891,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
  * additional information.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferSendCompletedFromISR() to be available.
+ *
  * @param xMessageBuffer The handle of the stream buffer to which data was
  * written.
  *
@@ -858,6 +935,9 @@ typedef StreamBufferHandle_t MessageBufferHandle_t;
  * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
  * additional information.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xMessageBufferReceiveCompletedFromISR() to be available.
+ *
  * @param xMessageBuffer The handle of the stream buffer from which data was
  * read.
  *

include/mpu_prototypes.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -38,6 +38,42 @@
 #ifndef MPU_PROTOTYPES_H
 #define MPU_PROTOTYPES_H
 
+typedef struct xTaskGenericNotifyParams
+{
+    TaskHandle_t xTaskToNotify;
+    UBaseType_t uxIndexToNotify;
+    uint32_t ulValue;
+    eNotifyAction eAction;
+    uint32_t * pulPreviousNotificationValue;
+} xTaskGenericNotifyParams_t;
+
+typedef struct xTaskGenericNotifyWaitParams
+{
+    UBaseType_t uxIndexToWaitOn;
+    uint32_t ulBitsToClearOnEntry;
+    uint32_t ulBitsToClearOnExit;
+    uint32_t * pulNotificationValue;
+    TickType_t xTicksToWait;
+} xTaskGenericNotifyWaitParams_t;
+
+typedef struct xTimerGenericCommandFromTaskParams
+{
+    TimerHandle_t xTimer;
+    BaseType_t xCommandID;
+    TickType_t xOptionalValue;
+    BaseType_t * pxHigherPriorityTaskWoken;
+    TickType_t xTicksToWait;
+} xTimerGenericCommandFromTaskParams_t;
+
+typedef struct xEventGroupWaitBitsParams
+{
+    EventGroupHandle_t xEventGroup;
+    EventBits_t uxBitsToWaitFor;
+    BaseType_t xClearOnExit;
+    BaseType_t xWaitForAllBits;
+    TickType_t xTicksToWait;
+} xEventGroupWaitBitsParams_t;
+
 /* MPU versions of task.h API functions. */
 void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
@@ -53,7 +89,6 @@ void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
 TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
 void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
@@ -77,11 +112,13 @@ BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
                                    uint32_t ulValue,
                                    eNotifyAction eAction,
                                    uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyEntry( const xTaskGenericNotifyParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
                                        uint32_t ulBitsToClearOnEntry,
                                        uint32_t ulBitsToClearOnExit,
                                        uint32_t * pulNotificationValue,
                                        TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyWaitEntry( const xTaskGenericNotifyWaitParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
                                       BaseType_t xClearCountOnExit,
                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
@@ -99,35 +136,72 @@ BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
 /* Privileged only wrappers for Task APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
-BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
-                            const char * const pcName,
-                            const uint16_t usStackDepth,
-                            void * const pvParameters,
-                            UBaseType_t uxPriority,
-                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
-TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
-                                    const char * const pcName,
-                                    const uint32_t ulStackDepth,
-                                    void * const pvParameters,
-                                    UBaseType_t uxPriority,
-                                    StackType_t * const puxStackBuffer,
-                                    StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
-void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
-void MPU_vTaskPrioritySet( TaskHandle_t xTask,
-                           UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
-TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;
-BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
-                                             void * pvParameter ) PRIVILEGED_FUNCTION;
+#if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+
+    BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
+                                const char * const pcName,
+                                const configSTACK_DEPTH_TYPE uxStackDepth,
+                                void * const pvParameters,
+                                UBaseType_t uxPriority,
+                                TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+    TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                        const char * const pcName,
+                                        const configSTACK_DEPTH_TYPE uxStackDepth,
+                                        void * const pvParameters,
+                                        UBaseType_t uxPriority,
+                                        StackType_t * const puxStackBuffer,
+                                        StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskPrioritySet( TaskHandle_t xTask,
+                               UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+    TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                                 void * pvParameter ) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskGetRunTimeStatistics( char * pcWriteBuffer,
+                                        size_t uxBufferLength ) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskListTasks( char * pcWriteBuffer,
+                             size_t uxBufferLength ) FREERTOS_SYSTEM_CALL;
+    void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+
+#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
+                                const char * const pcName,
+                                const configSTACK_DEPTH_TYPE uxStackDepth,
+                                void * const pvParameters,
+                                UBaseType_t uxPriority,
+                                TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+    TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                        const char * const pcName,
+                                        const configSTACK_DEPTH_TYPE uxStackDepth,
+                                        void * const pvParameters,
+                                        UBaseType_t uxPriority,
+                                        StackType_t * const puxStackBuffer,
+                                        StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+    void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+    void MPU_vTaskPrioritySet( TaskHandle_t xTask,
+                               UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+    TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;
+    BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                                 void * pvParameter ) PRIVILEGED_FUNCTION;
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
                                       TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
                                             TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
-void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
-                              const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
+                                  const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskGetStaticBuffers( TaskHandle_t xTask,
                                       StackType_t ** ppuxStackBuffer,
                                       StaticTask_t ** ppxTaskBuffer ) PRIVILEGED_FUNCTION;
 UBaseType_t MPU_uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t MPU_uxTaskBasePriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+UBaseType_t MPU_uxTaskBasePriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
 TaskHookFunction_t MPU_xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
@@ -175,28 +249,64 @@ uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 /* Privileged only wrappers for Queue APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
-void MPU_vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
-                                           StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
-                                                 const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
-                                                       const UBaseType_t uxInitialCount,
-                                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
-                                       const UBaseType_t uxItemSize,
-                                       const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
-                                             const UBaseType_t uxItemSize,
-                                             uint8_t * pucQueueStorage,
-                                             StaticQueue_t * pxStaticQueue,
-                                             const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
-BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                    QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
-                                   BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+#if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+
+    void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                               StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                     const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                           const UBaseType_t uxInitialCount,
+                                                           StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
+                                           const UBaseType_t uxItemSize,
+                                           const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+    QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                                 const UBaseType_t uxItemSize,
+                                                 uint8_t * pucQueueStorage,
+                                                 StaticQueue_t * pxStaticQueue,
+                                                 const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+    QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+    QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+                                                uint8_t * pucQueueStorage,
+                                                StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                        QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
+                                       BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+
+#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    void MPU_vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                               StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                     const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                           const UBaseType_t uxInitialCount,
+                                                           StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
+                                           const UBaseType_t uxItemSize,
+                                           const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+    QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                                 const UBaseType_t uxItemSize,
+                                                 uint8_t * pucQueueStorage,
+                                                 StaticQueue_t * pxStaticQueue,
+                                                 const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+    QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+    QueueSetHandle_t MPU_xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+                                                uint8_t * pucQueueStorage,
+                                                StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+    BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                        QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+    BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
+                                       BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
 BaseType_t MPU_xQueueGenericGetStaticBuffers( QueueHandle_t xQueue,
                                               uint8_t ** ppucQueueStorage,
                                               StaticQueue_t ** ppxStaticQueue ) PRIVILEGED_FUNCTION;
@@ -223,14 +333,15 @@ void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
                            void * pvNewID ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
-                                     const BaseType_t xCommandID,
-                                     const TickType_t xOptionalValue,
-                                     BaseType_t * const pxHigherPriorityTaskWoken,
-                                     const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                             const BaseType_t xCommandID,
+                                             const TickType_t xOptionalValue,
+                                             BaseType_t * const pxHigherPriorityTaskWoken,
+                                             const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommandFromTaskEntry( const xTimerGenericCommandFromTaskParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
-                              const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+                              const BaseType_t xAutoReload ) FREERTOS_SYSTEM_CALL;
 BaseType_t MPU_xTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
 TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
@@ -241,17 +352,22 @@ TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
  * with all the APIs. */
 TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
                                 const TickType_t xTimerPeriodInTicks,
-                                const UBaseType_t uxAutoReload,
+                                const BaseType_t xAutoReload,
                                 void * const pvTimerID,
                                 TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
 TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
                                       const TickType_t xTimerPeriodInTicks,
-                                      const UBaseType_t uxAutoReload,
+                                      const BaseType_t xAutoReload,
                                       void * const pvTimerID,
                                       TimerCallbackFunction_t pxCallbackFunction,
                                       StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xTimerGetStaticBuffer( TimerHandle_t xTimer,
                                       StaticTimer_t ** ppxTimerBuffer ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+                                            const BaseType_t xCommandID,
+                                            const TickType_t xOptionalValue,
+                                            BaseType_t * const pxHigherPriorityTaskWoken,
+                                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
 /* MPU versions of event_group.h API functions. */
 EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
@@ -259,6 +375,7 @@ EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
                                      const BaseType_t xClearOnExit,
                                      const BaseType_t xWaitForAllBits,
                                      TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBitsEntry( const xEventGroupWaitBitsParams_t * pxParams ) FREERTOS_SYSTEM_CALL;
 EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
                                       const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
 EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
@@ -271,14 +388,25 @@ EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
     UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
     void MPU_vEventGroupSetNumber( void * xEventGroup,
                                    UBaseType_t uxEventGroupNumber ) FREERTOS_SYSTEM_CALL;
-#endif /* ( configUSE_TRACE_FACILITY == 1 )*/
+#endif /* #if ( configUSE_TRACE_FACILITY == 1 ) */
 
 /* Privileged only wrappers for Event Group APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
-EventGroupHandle_t MPU_xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
-EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+#if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+
+    EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+    EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+    void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    EventGroupHandle_t MPU_xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+    EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+    void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
 BaseType_t MPU_xEventGroupGetStaticBuffer( EventGroupHandle_t xEventGroup,
                                            StaticEventGroup_t ** ppxEventGroupBuffer ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
@@ -308,20 +436,42 @@ size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuff
 /* Privileged only wrappers for Stream Buffer APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
-StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
-                                                     size_t xTriggerLevelBytes,
-                                                     BaseType_t xIsMessageBuffer,
-                                                     StreamBufferCallbackFunction_t pxSendCompletedCallback,
-                                                     StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-                                                           size_t xTriggerLevelBytes,
-                                                           BaseType_t xIsMessageBuffer,
-                                                           uint8_t * const pucStreamBufferStorageArea,
-                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,
-                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,
-                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+
+    StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                         size_t xTriggerLevelBytes,
+                                                         BaseType_t xStreamBufferType,
+                                                         StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                         StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL;
+    StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                               size_t xTriggerLevelBytes,
+                                                               BaseType_t xStreamBufferType,
+                                                               uint8_t * const pucStreamBufferStorageArea,
+                                                               StaticStreamBuffer_t * const pxStaticStreamBuffer,
+                                                               StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                               StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) FREERTOS_SYSTEM_CALL;
+    void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+    BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+#else /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
+    StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                         size_t xTriggerLevelBytes,
+                                                         BaseType_t xStreamBufferType,
+                                                         StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                         StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+    StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                               size_t xTriggerLevelBytes,
+                                                               BaseType_t xStreamBufferType,
+                                                               uint8_t * const pucStreamBufferStorageArea,
+                                                               StaticStreamBuffer_t * const pxStaticStreamBuffer,
+                                                               StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                               StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+    void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+    BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
 BaseType_t MPU_xStreamBufferGetStaticBuffers( StreamBufferHandle_t xStreamBuffers,
                                               uint8_t * ppucStreamBufferStorageArea,
                                               StaticStreamBuffer_t * ppxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
@@ -337,5 +487,6 @@ BaseType_t MPU_xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBu
                                                   BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
 BaseType_t MPU_xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
                                                      BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+BaseType_t MPU_xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 
 #endif /* MPU_PROTOTYPES_H */

include/mpu_syscall_numbers.h

@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel <DEVELOPMENT BRANCH>
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef MPU_SYSCALL_NUMBERS_H
+#define MPU_SYSCALL_NUMBERS_H
+
+/* Numbers assigned to various system calls. */
+#define SYSTEM_CALL_xTaskGenericNotify                     0
+#define SYSTEM_CALL_xTaskGenericNotifyWait                 1
+#define SYSTEM_CALL_xTimerGenericCommandFromTask           2
+#define SYSTEM_CALL_xEventGroupWaitBits                    3
+#define SYSTEM_CALL_xTaskDelayUntil                        4
+#define SYSTEM_CALL_xTaskAbortDelay                        5
+#define SYSTEM_CALL_vTaskDelay                             6
+#define SYSTEM_CALL_uxTaskPriorityGet                      7
+#define SYSTEM_CALL_eTaskGetState                          8
+#define SYSTEM_CALL_vTaskGetInfo                           9
+#define SYSTEM_CALL_xTaskGetIdleTaskHandle                 10
+#define SYSTEM_CALL_vTaskSuspend                           11
+#define SYSTEM_CALL_vTaskResume                            12
+#define SYSTEM_CALL_xTaskGetTickCount                      13
+#define SYSTEM_CALL_uxTaskGetNumberOfTasks                 14
+#define SYSTEM_CALL_ulTaskGetRunTimeCounter                15
+#define SYSTEM_CALL_ulTaskGetRunTimePercent                16
+#define SYSTEM_CALL_ulTaskGetIdleRunTimePercent            17
+#define SYSTEM_CALL_ulTaskGetIdleRunTimeCounter            18
+#define SYSTEM_CALL_vTaskSetApplicationTaskTag             19
+#define SYSTEM_CALL_xTaskGetApplicationTaskTag             20
+#define SYSTEM_CALL_vTaskSetThreadLocalStoragePointer      21
+#define SYSTEM_CALL_pvTaskGetThreadLocalStoragePointer     22
+#define SYSTEM_CALL_uxTaskGetSystemState                   23
+#define SYSTEM_CALL_uxTaskGetStackHighWaterMark            24
+#define SYSTEM_CALL_uxTaskGetStackHighWaterMark2           25
+#define SYSTEM_CALL_xTaskGetCurrentTaskHandle              26
+#define SYSTEM_CALL_xTaskGetSchedulerState                 27
+#define SYSTEM_CALL_vTaskSetTimeOutState                   28
+#define SYSTEM_CALL_xTaskCheckForTimeOut                   29
+#define SYSTEM_CALL_ulTaskGenericNotifyTake                30
+#define SYSTEM_CALL_xTaskGenericNotifyStateClear           31
+#define SYSTEM_CALL_ulTaskGenericNotifyValueClear          32
+#define SYSTEM_CALL_xQueueGenericSend                      33
+#define SYSTEM_CALL_uxQueueMessagesWaiting                 34
+#define SYSTEM_CALL_uxQueueSpacesAvailable                 35
+#define SYSTEM_CALL_xQueueReceive                          36
+#define SYSTEM_CALL_xQueuePeek                             37
+#define SYSTEM_CALL_xQueueSemaphoreTake                    38
+#define SYSTEM_CALL_xQueueGetMutexHolder                   39
+#define SYSTEM_CALL_xQueueTakeMutexRecursive               40
+#define SYSTEM_CALL_xQueueGiveMutexRecursive               41
+#define SYSTEM_CALL_xQueueSelectFromSet                    42
+#define SYSTEM_CALL_xQueueAddToSet                         43
+#define SYSTEM_CALL_vQueueAddToRegistry                    44
+#define SYSTEM_CALL_vQueueUnregisterQueue                  45
+#define SYSTEM_CALL_pcQueueGetName                         46
+#define SYSTEM_CALL_pvTimerGetTimerID                      47
+#define SYSTEM_CALL_vTimerSetTimerID                       48
+#define SYSTEM_CALL_xTimerIsTimerActive                    49
+#define SYSTEM_CALL_xTimerGetTimerDaemonTaskHandle         50
+#define SYSTEM_CALL_pcTimerGetName                         51
+#define SYSTEM_CALL_vTimerSetReloadMode                    52
+#define SYSTEM_CALL_xTimerGetReloadMode                    53
+#define SYSTEM_CALL_uxTimerGetReloadMode                   54
+#define SYSTEM_CALL_xTimerGetPeriod                        55
+#define SYSTEM_CALL_xTimerGetExpiryTime                    56
+#define SYSTEM_CALL_xEventGroupClearBits                   57
+#define SYSTEM_CALL_xEventGroupSetBits                     58
+#define SYSTEM_CALL_xEventGroupSync                        59
+#define SYSTEM_CALL_uxEventGroupGetNumber                  60
+#define SYSTEM_CALL_vEventGroupSetNumber                   61
+#define SYSTEM_CALL_xStreamBufferSend                      62
+#define SYSTEM_CALL_xStreamBufferReceive                   63
+#define SYSTEM_CALL_xStreamBufferIsFull                    64
+#define SYSTEM_CALL_xStreamBufferIsEmpty                   65
+#define SYSTEM_CALL_xStreamBufferSpacesAvailable           66
+#define SYSTEM_CALL_xStreamBufferBytesAvailable            67
+#define SYSTEM_CALL_xStreamBufferSetTriggerLevel           68
+#define SYSTEM_CALL_xStreamBufferNextMessageLengthBytes    69
+#define NUM_SYSTEM_CALLS                                   70  /* Total number of system calls. */
+
+#endif /* MPU_SYSCALL_NUMBERS_H */

include/mpu_wrappers.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -57,7 +57,6 @@
         #define vTaskResume                           MPU_vTaskResume
         #define xTaskGetTickCount                     MPU_xTaskGetTickCount
         #define uxTaskGetNumberOfTasks                MPU_uxTaskGetNumberOfTasks
-        #define pcTaskGetName                         MPU_pcTaskGetName
         #define uxTaskGetStackHighWaterMark           MPU_uxTaskGetStackHighWaterMark
         #define uxTaskGetStackHighWaterMark2          MPU_uxTaskGetStackHighWaterMark2
         #define vTaskSetApplicationTaskTag            MPU_vTaskSetApplicationTaskTag
@@ -86,6 +85,18 @@
 /* Privileged only wrappers for Task APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
+        #if ( configUSE_MPU_WRAPPERS_V1 == 1 )
+
+/* These are not needed in v2 because they do not take a task
+ * handle and therefore, no lookup is needed. Needed in v1 because
+ * these are available as system calls in v1. */
+            #define vTaskGetRunTimeStatistics            MPU_vTaskGetRunTimeStatistics
+            #define vTaskListTasks                       MPU_vTaskListTasks
+            #define vTaskSuspendAll                      MPU_vTaskSuspendAll
+            #define xTaskCatchUpTicks                    MPU_xTaskCatchUpTicks
+            #define xTaskResumeAll                       MPU_xTaskResumeAll
+        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 1 ) */
+
         #define xTaskCreate                              MPU_xTaskCreate
         #define xTaskCreateStatic                        MPU_xTaskCreateStatic
         #define vTaskDelete                              MPU_vTaskDelete
@@ -94,11 +105,14 @@
         #define xTaskCallApplicationTaskHook             MPU_xTaskCallApplicationTaskHook
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            #define pcTaskGetName                        MPU_pcTaskGetName
             #define xTaskCreateRestricted                MPU_xTaskCreateRestricted
             #define xTaskCreateRestrictedStatic          MPU_xTaskCreateRestrictedStatic
             #define vTaskAllocateMPURegions              MPU_vTaskAllocateMPURegions
             #define xTaskGetStaticBuffers                MPU_xTaskGetStaticBuffers
             #define uxTaskPriorityGetFromISR             MPU_uxTaskPriorityGetFromISR
+            #define uxTaskBasePriorityGet                MPU_uxTaskBasePriorityGet
+            #define uxTaskBasePriorityGetFromISR         MPU_uxTaskBasePriorityGetFromISR
             #define xTaskResumeFromISR                   MPU_xTaskResumeFromISR
             #define xTaskGetApplicationTaskTagFromISR    MPU_xTaskGetApplicationTaskTagFromISR
             #define xTaskGenericNotifyFromISR            MPU_xTaskGenericNotifyFromISR
@@ -136,6 +150,7 @@
         #define xQueueGenericCreateStatic              MPU_xQueueGenericCreateStatic
         #define xQueueGenericReset                     MPU_xQueueGenericReset
         #define xQueueCreateSet                        MPU_xQueueCreateSet
+        #define xQueueCreateSetStatic                  MPU_xQueueCreateSetStatic
         #define xQueueRemoveFromSet                    MPU_xQueueRemoveFromSet
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -156,21 +171,25 @@
         #define vTimerSetTimerID                  MPU_vTimerSetTimerID
         #define xTimerIsTimerActive               MPU_xTimerIsTimerActive
         #define xTimerGetTimerDaemonTaskHandle    MPU_xTimerGetTimerDaemonTaskHandle
-        #define xTimerGenericCommand              MPU_xTimerGenericCommand
+        #define xTimerGenericCommandFromTask      MPU_xTimerGenericCommandFromTask
         #define pcTimerGetName                    MPU_pcTimerGetName
         #define vTimerSetReloadMode               MPU_vTimerSetReloadMode
         #define uxTimerGetReloadMode              MPU_uxTimerGetReloadMode
         #define xTimerGetPeriod                   MPU_xTimerGetPeriod
         #define xTimerGetExpiryTime               MPU_xTimerGetExpiryTime
 
+        #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
+            #define xTimerGetReloadMode           MPU_xTimerGetReloadMode
+        #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
+
 /* Privileged only wrappers for Timer APIs. These are needed so that
  * the application can use opaque handles maintained in mpu_wrappers.c
  * with all the APIs. */
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
-            #define xTimerGetReloadMode      MPU_xTimerGetReloadMode
-            #define xTimerCreate             MPU_xTimerCreate
-            #define xTimerCreateStatic       MPU_xTimerCreateStatic
-            #define xTimerGetStaticBuffer    MPU_xTimerGetStaticBuffer
+            #define xTimerCreate                   MPU_xTimerCreate
+            #define xTimerCreateStatic             MPU_xTimerCreateStatic
+            #define xTimerGetStaticBuffer          MPU_xTimerGetStaticBuffer
+            #define xTimerGenericCommandFromISR    MPU_xTimerGenericCommandFromISR
         #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
 /* Map standard event_group.h API functions to the MPU equivalents. */
@@ -224,24 +243,43 @@
             #define xStreamBufferReceiveFromISR             MPU_xStreamBufferReceiveFromISR
             #define xStreamBufferSendCompletedFromISR       MPU_xStreamBufferSendCompletedFromISR
             #define xStreamBufferReceiveCompletedFromISR    MPU_xStreamBufferReceiveCompletedFromISR
+            #define xStreamBufferResetFromISR               MPU_xStreamBufferResetFromISR
         #endif /* #if ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
- * macro so applications can place data in privileged access sections
- * (useful when using statically allocated objects). */
-        #define PRIVILEGED_FUNCTION
-        #define PRIVILEGED_DATA    __attribute__( ( section( "privileged_data" ) ) )
-        #define FREERTOS_SYSTEM_CALL
+        #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) )
 
-    #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+            #define vGrantAccessToTask( xTask, xTaskToGrantAccess )                        vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToGrantAccess ) )
+            #define vRevokeAccessToTask( xTask, xTaskToRevokeAccess )                      vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xTaskToRevokeAccess ) )
 
-/* Ensure API functions go in the privileged execution section. */
-        #define PRIVILEGED_FUNCTION     __attribute__( ( section( "privileged_functions" ) ) )
-        #define PRIVILEGED_DATA         __attribute__( ( section( "privileged_data" ) ) )
-        #define FREERTOS_SYSTEM_CALL    __attribute__( ( section( "freertos_system_calls" ) ) )
+            #define vGrantAccessToSemaphore( xTask, xSemaphoreToGrantAccess )              vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xSemaphoreToGrantAccess ) )
+            #define vRevokeAccessToSemaphore( xTask, xSemaphoreToRevokeAccess )            vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xSemaphoreToRevokeAccess ) )
+
+            #define vGrantAccessToQueue( xTask, xQueueToGrantAccess )                      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueToGrantAccess ) )
+            #define vRevokeAccessToQueue( xTask, xQueueToRevokeAccess )                    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueToRevokeAccess ) )
+
+            #define vGrantAccessToQueueSet( xTask, xQueueSetToGrantAccess )                vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueSetToGrantAccess ) )
+            #define vRevokeAccessToQueueSet( xTask, xQueueSetToRevokeAccess )              vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xQueueSetToRevokeAccess ) )
+
+            #define vGrantAccessToEventGroup( xTask, xEventGroupToGrantAccess )            vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xEventGroupToGrantAccess ) )
+            #define vRevokeAccessToEventGroup( xTask, xEventGroupToRevokeAccess )          vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xEventGroupToRevokeAccess ) )
+
+            #define vGrantAccessToStreamBuffer( xTask, xStreamBufferToGrantAccess )        vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xStreamBufferToGrantAccess ) )
+            #define vRevokeAccessToStreamBuffer( xTask, xStreamBufferToRevokeAccess )      vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xStreamBufferToRevokeAccess ) )
+
+            #define vGrantAccessToMessageBuffer( xTask, xMessageBufferToGrantAccess )      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xMessageBufferToGrantAccess ) )
+            #define vRevokeAccessToMessageBuffer( xTask, xMessageBufferToRevokeAccess )    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xMessageBufferToRevokeAccess ) )
+
+            #define vGrantAccessToTimer( xTask, xTimerToGrantAccess )                      vGrantAccessToKernelObject( ( xTask ), ( int32_t ) ( xTimerToGrantAccess ) )
+            #define vRevokeAccessToTimer( xTask, xTimerToRevokeAccess )                    vRevokeAccessToKernelObject( ( xTask ), ( int32_t ) ( xTimerToRevokeAccess ) )
+
+        #endif /* #if ( ( configUSE_MPU_WRAPPERS_V1 == 0 ) && ( configENABLE_ACCESS_CONTROL_LIST == 1 ) ) */
 
     #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
 
+    #define PRIVILEGED_FUNCTION     __attribute__( ( section( "privileged_functions" ) ) )
+    #define PRIVILEGED_DATA         __attribute__( ( section( "privileged_data" ) ) )
+    #define FREERTOS_SYSTEM_CALL    __attribute__( ( section( "freertos_system_calls" ) ) )
+
 #else /* portUSING_MPU_WRAPPERS */
 
     #define PRIVILEGED_FUNCTION

include/newlib-freertos.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *

include/picolibc-freertos.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -58,18 +58,19 @@
 #endif
 
 /* Allocate thread local storage block off the end of the
-* stack. The _tls_size() function returns the size (in
-* bytes) of the total TLS area used by the application */
+ * stack. The picolibcTLS_SIZE macro returns the size (in
+ * bytes) of the total TLS area used by the application.
+ * Calculate the top of stack address. */
 #if ( portSTACK_GROWTH < 0 )
 
-    #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )                             \
-    do {                                                                                \
-        pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) \
-                                             - picolibcTLS_SIZE ) & ~                   \
-                                           configMAX( picolibcSTACK_ALIGNMENT_MASK,     \
-                                                      picolibcTLS_ALIGNMENT_MASK ) );   \
-        xTLSBlock = pxTopOfStack;                                                       \
-        _init_tls( xTLSBlock );                                                         \
+    #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )                                  \
+    do {                                                                                     \
+        xTLSBlock = ( void * ) ( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) -              \
+                                   picolibcTLS_SIZE ) &                                      \
+                                 ~picolibcTLS_ALIGNMENT_MASK );                              \
+        pxTopOfStack = ( StackType_t * ) ( ( ( ( portPOINTER_SIZE_TYPE ) xTLSBlock ) - 1 ) & \
+                                           ~picolibcSTACK_ALIGNMENT_MASK );                  \
+        _init_tls( xTLSBlock );                                                              \
     } while( 0 )
 #else /* portSTACK_GROWTH */
     #define configINIT_TLS_BLOCK( xTLSBlock, pxTopOfStack )                                          \

include/portable.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -85,19 +85,31 @@
     #define portARCH_NAME    NULL
 #endif
 
+#ifndef portBASE_TYPE_ENTER_CRITICAL
+    #define portBASE_TYPE_ENTER_CRITICAL()    taskENTER_CRITICAL()
+#endif
+
+#ifndef portBASE_TYPE_EXIT_CRITICAL
+    #define portBASE_TYPE_EXIT_CRITICAL()    taskEXIT_CRITICAL()
+#endif
+
+#ifndef configSTACK_DEPTH_TYPE
+    #define configSTACK_DEPTH_TYPE    StackType_t
+#endif
+
 #ifndef configSTACK_ALLOCATION_FROM_SEPARATE_HEAP
     /* Defaults to 0 for backward compatibility. */
     #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP    0
 #endif
 
+#include "mpu_wrappers.h"
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     extern "C" {
 #endif
 /* *INDENT-ON* */
 
-#include "mpu_wrappers.h"
-
 /*
  * Setup the stack of a new task so it is ready to be placed under the
  * scheduler control.  The registers have to be placed on the stack in
@@ -174,13 +186,14 @@ void vPortGetHeapStats( HeapStats_t * pxHeapStats );
 /*
  * Map to the memory management routines required for the port.
  */
-void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void * pvPortMalloc( size_t xWantedSize ) PRIVILEGED_FUNCTION;
 void * pvPortCalloc( size_t xNum,
                      size_t xSize ) PRIVILEGED_FUNCTION;
 void vPortFree( void * pv ) PRIVILEGED_FUNCTION;
 void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
 size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
 size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+void xPortResetHeapMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
 
 #if ( configSTACK_ALLOCATION_FROM_SEPARATE_HEAP == 1 )
     void * pvPortMallocStack( size_t xSize ) PRIVILEGED_FUNCTION;
@@ -190,6 +203,12 @@ size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
     #define vPortFreeStack       vPortFree
 #endif
 
+/*
+ * This function resets the internal state of the heap module. It must be called
+ * by the application before restarting the scheduler.
+ */
+void vPortHeapResetState( void ) PRIVILEGED_FUNCTION;
+
 #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
 
 /**
@@ -200,7 +219,7 @@ size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
  *
  * This hook function is called when allocation failed.
  */
-    void vApplicationMallocFailedHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+    void vApplicationMallocFailedHook( void );
 #endif
 
 /*
@@ -228,7 +247,7 @@ void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
     void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
                                     const struct xMEMORY_REGION * const xRegions,
                                     StackType_t * pxBottomOfStack,
-                                    uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+                                    configSTACK_DEPTH_TYPE uxStackDepth ) PRIVILEGED_FUNCTION;
 #endif
 
 /**
@@ -247,6 +266,21 @@ void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
                                                 uint32_t ulAccessRequested ) PRIVILEGED_FUNCTION;
 #endif
 
+/**
+ * @brief Checks if the calling task is authorized to access the given kernel object.
+ *
+ * @param lInternalIndexOfKernelObject The index of the kernel object in the kernel
+ *                                     object handle pool.
+ *
+ * @return pdTRUE if the calling task is authorized to access the kernel object,
+ *         pdFALSE otherwise.
+ */
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
+
+    BaseType_t xPortIsAuthorizedToAccessKernelObject( int32_t lInternalIndexOfKernelObject ) PRIVILEGED_FUNCTION;
+
+#endif
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }

include/projdefs.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -33,13 +33,20 @@
  * Defines the prototype to which task functions must conform.  Defined in this
  * file to ensure the type is known before portable.h is included.
  */
-typedef void (* TaskFunction_t)( void * );
+typedef void (* TaskFunction_t)( void * arg );
 
 /* Converts a time in milliseconds to a time in ticks.  This macro can be
  * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
  * definition here is not suitable for your application. */
 #ifndef pdMS_TO_TICKS
-    #define pdMS_TO_TICKS( xTimeInMs )    ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )
+    #define pdMS_TO_TICKS( xTimeInMs )    ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInMs ) * ( uint64_t ) configTICK_RATE_HZ ) / ( uint64_t ) 1000U ) )
+#endif
+
+/* Converts a time in ticks to a time in milliseconds.  This macro can be
+ * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+ * definition here is not suitable for your application. */
+#ifndef pdTICKS_TO_MS
+    #define pdTICKS_TO_MS( xTimeInTicks )    ( ( TickType_t ) ( ( ( uint64_t ) ( xTimeInTicks ) * ( uint64_t ) 1000U ) / ( uint64_t ) configTICK_RATE_HZ ) )
 #endif
 
 #define pdFALSE                                  ( ( BaseType_t ) 0 )

include/queue.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -34,14 +34,14 @@
     #error "include FreeRTOS.h" must appear in source files before "include queue.h"
 #endif
 
+#include "task.h"
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     extern "C" {
 #endif
 /* *INDENT-ON* */
 
-#include "task.h"
-
 /**
  * Type by which queues are referenced.  For example, a call to xQueueCreate()
  * returns an QueueHandle_t variable that can then be used as a parameter to
@@ -71,11 +71,11 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
 
 /* For internal use only.  These definitions *must* match those in queue.c. */
 #define queueQUEUE_TYPE_BASE                  ( ( uint8_t ) 0U )
-#define queueQUEUE_TYPE_SET                   ( ( uint8_t ) 0U )
 #define queueQUEUE_TYPE_MUTEX                 ( ( uint8_t ) 1U )
 #define queueQUEUE_TYPE_COUNTING_SEMAPHORE    ( ( uint8_t ) 2U )
 #define queueQUEUE_TYPE_BINARY_SEMAPHORE      ( ( uint8_t ) 3U )
 #define queueQUEUE_TYPE_RECURSIVE_MUTEX       ( ( uint8_t ) 4U )
+#define queueQUEUE_TYPE_SET                   ( ( uint8_t ) 5U )
 
 /**
  * queue. h
@@ -109,7 +109,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  * the same size.
  *
  * @return If the queue is successfully create then a handle to the newly
- * created queue is returned.  If the queue cannot be created then 0 is
+ * created queue is returned.  If the queue cannot be created then NULL is
  * returned.
  *
  * Example usage:
@@ -126,7 +126,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *
  *  // Create a queue capable of containing 10 uint32_t values.
  *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
- *  if( xQueue1 == 0 )
+ *  if( xQueue1 == NULL )
  *  {
  *      // Queue was not created and must not be used.
  *  }
@@ -134,7 +134,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *  // Create a queue capable of containing 10 pointers to AMessage structures.
  *  // These should be passed by pointer as they contain a lot of data.
  *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
- *  if( xQueue2 == 0 )
+ *  if( xQueue2 == NULL )
  *  {
  *      // Queue was not created and must not be used.
  *  }
@@ -267,7 +267,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
 /**
  * queue. h
  * @code{c}
- * BaseType_t xQueueSendToToFront(
+ * BaseType_t xQueueSendToFront(
  *                                 QueueHandle_t    xQueue,
  *                                 const void       *pvItemToQueue,
  *                                 TickType_t       xTicksToWait
@@ -292,7 +292,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  * queue is full.  The time is defined in tick periods so the constant
  * portTICK_PERIOD_MS should be used to convert to real time if this is required.
  *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
  *
  * Example usage:
  * @code{c}
@@ -302,7 +302,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *  char ucData[ 20 ];
  * } xMessage;
  *
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
  *
  * void vATask( void *pvParameters )
  * {
@@ -375,7 +375,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  * is full.  The  time is defined in tick periods so the constant
  * portTICK_PERIOD_MS should be used to convert to real time if this is required.
  *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
  *
  * Example usage:
  * @code{c}
@@ -385,7 +385,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *  char ucData[ 20 ];
  * } xMessage;
  *
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
  *
  * void vATask( void *pvParameters )
  * {
@@ -460,7 +460,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  * queue is full.  The time is defined in tick periods so the constant
  * portTICK_PERIOD_MS should be used to convert to real time if this is required.
  *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
  *
  * Example usage:
  * @code{c}
@@ -470,7 +470,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *  char ucData[ 20 ];
  * } xMessage;
  *
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
  *
  * void vATask( void *pvParameters )
  * {
@@ -633,7 +633,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  * item at the back of the queue, or queueSEND_TO_FRONT to place the item
  * at the front of the queue (for high priority messages).
  *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ * @return pdPASS if the item was successfully posted, otherwise errQUEUE_FULL.
  *
  * Example usage:
  * @code{c}
@@ -643,7 +643,7 @@ typedef struct QueueDefinition   * QueueSetMemberHandle_t;
  *  char ucData[ 20 ];
  * } xMessage;
  *
- * uint32_t ulVar = 10UL;
+ * uint32_t ulVar = 10U;
  *
  * void vATask( void *pvParameters )
  * {
@@ -723,8 +723,8 @@ BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
  * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
  * is empty.
  *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise errQUEUE_EMPTY.
  *
  * Example usage:
  * @code{c}
@@ -811,8 +811,8 @@ BaseType_t xQueuePeek( QueueHandle_t xQueue,
  * @param pvBuffer Pointer to the buffer into which the received item will
  * be copied.
  *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise pdFAIL.
  *
  * \defgroup xQueuePeekFromISR xQueuePeekFromISR
  * \ingroup QueueManagement
@@ -852,8 +852,8 @@ BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
  * constant portTICK_PERIOD_MS should be used to convert to real time if this is
  * required.
  *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise errQUEUE_EMPTY.
  *
  * Example usage:
  * @code{c}
@@ -995,10 +995,10 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
  * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
  * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * running task.  If xQueueSendToFrontFromISR() sets this value to pdTRUE then
  * a context switch should be requested before the interrupt is exited.
  *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
  * errQUEUE_FULL.
  *
  * Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1070,7 +1070,7 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
  * a context switch should be requested before the interrupt is exited.
  *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
  * errQUEUE_FULL.
  *
  * Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1185,9 +1185,12 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  *  {
  *      // Writing to the queue caused a task to unblock and the unblocked task
  *      // has a priority higher than or equal to the priority of the currently
- *      // executing task (the task this interrupt interrupted).  Perform a context
+ *      // executing task (the task this interrupt interrupted). Perform a context
  *      // switch so this interrupt returns directly to the unblocked task.
- *      portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+ *      // The macro used is port specific and will be either
+ *      // portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to the documentation
+ *      // page for the port being used.
+ *      portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
  *  }
  * }
  * @endcode
@@ -1232,7 +1235,7 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
  * a context switch should be requested before the interrupt is exited.
  *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
  * errQUEUE_FULL.
  *
  * Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1260,8 +1263,11 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  *  // Now the buffer is empty we can switch context if necessary.
  *  if( xHigherPriorityTaskWoken )
  *  {
- *      // Actual macro used here is port specific.
- *      portYIELD_FROM_ISR ();
+ *       // As xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *       // switch should be requested. The macro used is port specific and
+ *       // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ *       // refer to the documentation page for the port being used.
+ *       portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
  *  }
  * }
  * @endcode
@@ -1312,7 +1318,7 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  * item at the back of the queue, or queueSEND_TO_FRONT to place the item
  * at the front of the queue (for high priority messages).
  *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * @return pdPASS if the data was successfully sent to the queue, otherwise
  * errQUEUE_FULL.
  *
  * Example usage for buffered IO (where the ISR can obtain more than one value
@@ -1337,11 +1343,14 @@ void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
  *
  *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
  *
- *  // Now the buffer is empty we can switch context if necessary.  Note that the
- *  // name of the yield function required is port specific.
+ *  // Now the buffer is empty we can switch context if necessary.
  *  if( xHigherPriorityTaskWokenByPost )
  *  {
- *      portYIELD_FROM_ISR();
+ *       // As xHigherPriorityTaskWokenByPost is now set to pdTRUE then a context
+ *       // switch should be requested. The macro used is port specific and
+ *       // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ *       // refer to the documentation page for the port being used.
+ *       portYIELD_FROM_ISR( xHigherPriorityTaskWokenByPost );
  *  }
  * }
  * @endcode
@@ -1380,8 +1389,8 @@ BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
  * to unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
  * remain unchanged.
  *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
+ * @return pdPASS if an item was successfully received from the queue,
+ * otherwise pdFAIL.
  *
  * Example usage:
  * @code{c}
@@ -1455,6 +1464,8 @@ BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FU
 BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 
+#if ( configUSE_CO_ROUTINES == 1 )
+
 /*
  * The functions defined above are for passing data to and from tasks.  The
  * functions below are the equivalents for passing data to and from
@@ -1464,18 +1475,20 @@ UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEG
  * should not be called directly from application code.  Instead use the macro
  * wrappers defined within croutine.h.
  */
-BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
-                                const void * pvItemToQueue,
-                                BaseType_t xCoRoutinePreviouslyWoken );
-BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
-                                   void * pvBuffer,
-                                   BaseType_t * pxTaskWoken );
-BaseType_t xQueueCRSend( QueueHandle_t xQueue,
-                         const void * pvItemToQueue,
-                         TickType_t xTicksToWait );
-BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
-                            void * pvBuffer,
-                            TickType_t xTicksToWait );
+    BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
+                                    const void * pvItemToQueue,
+                                    BaseType_t xCoRoutinePreviouslyWoken );
+    BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
+                                       void * pvBuffer,
+                                       BaseType_t * pxTaskWoken );
+    BaseType_t xQueueCRSend( QueueHandle_t xQueue,
+                             const void * pvItemToQueue,
+                             TickType_t xTicksToWait );
+    BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
+                                void * pvBuffer,
+                                TickType_t xTicksToWait );
+
+#endif /* if ( configUSE_CO_ROUTINES == 1 ) */
 
 /*
  * For internal use only.  Use xSemaphoreCreateMutex(),
@@ -1483,21 +1496,34 @@ BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
  * these functions directly.
  */
 QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
-                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
-                                             const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
-                                                   const UBaseType_t uxInitialCount,
-                                                   StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                           StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_COUNTING_SEMAPHORES == 1 )
+    QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                 const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                       const UBaseType_t uxInitialCount,
+                                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
+
 BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
                                 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+    TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
- * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
- * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ * For internal use only.  Use xSemaphoreTakeRecursive() or
+ * xSemaphoreGiveRecursive() instead of calling these functions directly.
  */
 BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
                                      TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
@@ -1537,7 +1563,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
  */
 #if ( configQUEUE_REGISTRY_SIZE > 0 )
     void vQueueAddToRegistry( QueueHandle_t xQueue,
-                              const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                              const char * pcQueueName ) PRIVILEGED_FUNCTION;
 #endif
 
 /*
@@ -1566,7 +1592,7 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
  * returned.
  */
 #if ( configQUEUE_REGISTRY_SIZE > 0 )
-    const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 #endif
 
 /*
@@ -1612,14 +1638,14 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
  * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
  * function.
  *
- * A queue set must be explicitly created using a call to xQueueCreateSet()
- * before it can be used.  Once created, standard FreeRTOS queues and semaphores
- * can be added to the set using calls to xQueueAddToSet().
- * xQueueSelectFromSet() is then used to determine which, if any, of the queues
- * or semaphores contained in the set is in a state where a queue read or
- * semaphore take operation would be successful.
+ * A queue set must be explicitly created using a call to xQueueCreateSet() or
+ * xQueueCreateSetStatic() before it can be used.  Once created, standard
+ * FreeRTOS queues and semaphores can be added to the set using calls to
+ * xQueueAddToSet().  xQueueSelectFromSet() is then used to determine which, if
+ * any, of the queues or semaphores contained in the set is in a state where a
+ * queue read or semaphore take operation would be successful.
  *
- * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
+ * Note 1:  See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets
  * for reasons why queue sets are very rarely needed in practice as there are
  * simpler methods of blocking on multiple objects.
  *
@@ -1653,11 +1679,73 @@ BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
  * @return If the queue set is created successfully then a handle to the created
  * queue set is returned.  Otherwise NULL is returned.
  */
-QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * or xQueueCreateSetStatic() before it can be used.  Once created, standard
+ * FreeRTOS queues and semaphores can be added to the set using calls to
+ * xQueueAddToSet().  xQueueSelectFromSet() is then used to determine which, if
+ * any, of the queues or semaphores contained in the set is in a state where a
+ * queue read or semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @param pucQueueStorage pucQueueStorage must point to a uint8_t array that is
+ * at least large enough to hold uxEventQueueLength events.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  If pxQueueBuffer is NULL then NULL is returned.
+ */
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    QueueSetHandle_t xQueueCreateSetStatic( const UBaseType_t uxEventQueueLength,
+                                            uint8_t * pucQueueStorage,
+                                            StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * Adds a queue or semaphore to a queue set that was previously created by a
- * call to xQueueCreateSet().
+ * call to xQueueCreateSet() or xQueueCreateSetStatic().
  *
  * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
  * function.
@@ -1677,8 +1765,10 @@ QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILE
  * queue set because it is already a member of a different queue set then pdFAIL
  * is returned.
  */
-BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                           QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+    BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                               QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
@@ -1697,8 +1787,10 @@ BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
  * then pdPASS is returned.  If the queue was not in the queue set, or the
  * queue (or semaphore) was not empty, then pdFAIL is returned.
  */
-BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
-                                QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+    BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                    QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * xQueueSelectFromSet() selects from the members of a queue set a queue or
@@ -1710,7 +1802,7 @@ BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
  * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
  * function.
  *
- * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
+ * Note 1:  See the documentation on https://www.freertos.org/Documentation/02-Kernel/04-API-references/07-Queue-sets/00-RTOS-queue-sets
  * for reasons why queue sets are very rarely needed in practice as there are
  * simpler methods of blocking on multiple objects.
  *
@@ -1734,13 +1826,17 @@ BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
  * in the queue set that is available, or NULL if no such queue or semaphore
  * exists before before the specified block time expires.
  */
-QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
-                                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+    QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#endif
 
 /*
  * A version of xQueueSelectFromSet() that can be used from an ISR.
  */
-QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#if ( configUSE_QUEUE_SETS == 1 )
+    QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+#endif
 
 /* Not public API functions. */
 void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
@@ -1748,11 +1844,22 @@ void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
                                      const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
 BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
                                BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
-void vQueueSetQueueNumber( QueueHandle_t xQueue,
-                           UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
-UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vQueueSetQueueNumber( QueueHandle_t xQueue,
+                               UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
 UBaseType_t uxQueueGetQueueItemSize( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueLength( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus

include/semphr.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -1193,7 +1193,8 @@ typedef QueueHandle_t SemaphoreHandle_t;
 /**
  * semphr.h
  * @code{c}
- * BaseType_t xSemaphoreGetStaticBuffer( SemaphoreHandle_t xSemaphore );
+ * BaseType_t xSemaphoreGetStaticBuffer( SemaphoreHandle_t xSemaphore,
+ *                                       StaticSemaphore_t ** ppxSemaphoreBuffer );
  * @endcode
  *
  * Retrieve pointer to a statically created binary semaphore, counting semaphore,

include/stack_macros.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,60 +53,78 @@
     #define portSTACK_LIMIT_PADDING    0
 #endif
 
-#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+/* Stack overflow check is not straight forward to implement for MPU ports
+ * because of the following reasons:
+ * 1. The context is stored in TCB and as a result, pxTopOfStack member points
+ *    to the context location in TCB.
+ * 2. System calls are executed on a separate privileged only stack.
+ *
+ * It is still okay because an MPU region is used to protect task stack which
+ * means task stack overflow will trigger an MPU fault for unprivileged tasks.
+ * Additionally, architectures with hardware stack overflow checking support
+ * (such as Armv8-M) will trigger a fault when a task's stack overflows.
+ */
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
 /* Only the current stack state is to be checked. */
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
-    do {                                                                                              \
-        /* Is the currently saved stack pointer within the stack limit? */                            \
-        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )           \
-        {                                                                                             \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
-        }                                                                                             \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                      \
+    do                                                                                          \
+    {                                                                                           \
+        /* Is the currently saved stack pointer within the stack limit? */                      \
+        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING )     \
+        {                                                                                       \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                               \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName ); \
+        }                                                                                       \
     } while( 0 )
 
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
 /* Only the current stack state is to be checked. */
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
-    do {                                                                                              \
-                                                                                                      \
-        /* Is the currently saved stack pointer within the stack limit? */                            \
-        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING )      \
-        {                                                                                             \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
-        }                                                                                             \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
+    do                                                                                           \
+    {                                                                                            \
+        /* Is the currently saved stack pointer within the stack limit? */                       \
+        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \
+        {                                                                                        \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );  \
+        }                                                                                        \
     } while( 0 )
 
 #endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
 /*-----------------------------------------------------------*/
 
-#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
-    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
-    do {                                                                                              \
-        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                       \
-        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;                                        \
-                                                                                                      \
-        if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                      \
-            ( pulStack[ 1 ] != ulCheckValue ) ||                                                      \
-            ( pulStack[ 2 ] != ulCheckValue ) ||                                                      \
-            ( pulStack[ 3 ] != ulCheckValue ) )                                                       \
-        {                                                                                             \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
-        }                                                                                             \
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                       \
+    do                                                                                           \
+    {                                                                                            \
+        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                  \
+        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U;                                  \
+                                                                                                 \
+        if( ( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) || \
+            ( pulStack[ 0 ] != ulCheckValue ) ||                                                 \
+            ( pulStack[ 1 ] != ulCheckValue ) ||                                                 \
+            ( pulStack[ 2 ] != ulCheckValue ) ||                                                 \
+            ( pulStack[ 3 ] != ulCheckValue ) )                                                  \
+        {                                                                                        \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );  \
+        }                                                                                        \
     } while( 0 )
 
 #endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
 /*-----------------------------------------------------------*/
 
-#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) && ( portUSING_MPU_WRAPPERS != 1 ) )
 
     #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                                \
-    do {                                                                                                                                  \
+    do                                                                                                                                    \
+    {                                                                                                                                     \
         int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;                                                                  \
         static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                         tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
@@ -114,13 +132,13 @@
                                                         tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
                                                         tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
                                                                                                                                           \
-                                                                                                                                          \
         pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \
                                                                                                                                           \
-        /* Has the extremity of the task stack ever been written over? */                                                                 \
-        if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )                     \
+        if( ( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) ||                                     \
+            ( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) )                 \
         {                                                                                                                                 \
-            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );                                     \
+            char * pcOverflowTaskName = pxCurrentTCB->pcTaskName;                                                                         \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pcOverflowTaskName );                                           \
         }                                                                                                                                 \
     } while( 0 )
 

include/stdint.readme

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *

include/stream_buffer.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -40,12 +40,12 @@
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section section and set the
- * receive block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  */
 
@@ -62,6 +62,13 @@
 #endif
 /* *INDENT-ON* */
 
+/**
+ * Type of stream buffer. For internal use only.
+ */
+#define sbTYPE_STREAM_BUFFER             ( ( BaseType_t ) 0 )
+#define sbTYPE_MESSAGE_BUFFER            ( ( BaseType_t ) 1 )
+#define sbTYPE_STREAM_BATCHING_BUFFER    ( ( BaseType_t ) 2 )
+
 /**
  * Type by which stream buffers are referenced.  For example, a call to
  * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
@@ -91,6 +98,8 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  *
  * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
  * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferCreate() to be available.
  *
  * @param xBufferSizeBytes The total number of bytes the stream buffer will be
  * able to hold at any one time.
@@ -155,11 +164,11 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  */
 
 #define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \
-    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, NULL, NULL )
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, NULL, NULL )
 
 #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
     #define xStreamBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
-    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
 #endif
 
 /**
@@ -167,15 +176,17 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  *
  * @code{c}
  * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
- *                                              size_t xTriggerLevelBytes,
- *                                              uint8_t *pucStreamBufferStorageArea,
- *                                              StaticStreamBuffer_t *pxStaticStreamBuffer );
+ *                                                 size_t xTriggerLevelBytes,
+ *                                                 uint8_t *pucStreamBufferStorageArea,
+ *                                                 StaticStreamBuffer_t *pxStaticStreamBuffer );
  * @endcode
  * Creates a new stream buffer using statically allocated memory.  See
  * xStreamBufferCreate() for a version that uses dynamically allocated memory.
  *
  * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
- * xStreamBufferCreateStatic() to be available.
+ * xStreamBufferCreateStatic() to be available. configUSE_STREAM_BUFFERS must be
+ * set to 1 in for FreeRTOSConfig.h for xStreamBufferCreateStatic() to be
+ * available.
  *
  * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
  * pucStreamBufferStorageArea parameter.
@@ -253,11 +264,199 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  */
 
 #define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
-    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
 
 #if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
     #define xStreamBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
-    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), pdFALSE, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * StreamBufferHandle_t xStreamBatchingBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+ * @endcode
+ *
+ * Creates a new stream batching buffer using dynamically allocated memory.  See
+ * xStreamBatchingBufferCreateStatic() for a version that uses statically
+ * allocated memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBatchingBufferCreate() to be available.
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBatchingBufferCreate() to be available.
+ *
+ * The difference between a stream buffer and a stream batching buffer is when
+ * a task performs read on a non-empty buffer:
+ * - The task reading from a non-empty stream buffer returns immediately
+ *   regardless of the amount of data in the buffer.
+ * - The task reading from a non-empty steam batching buffer blocks until the
+ *   amount of data in the buffer exceeds the trigger level or the block time
+ *   expires.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream batching buffer
+ * will be able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * batching buffer to unblock a task calling xStreamBufferReceive before the
+ * block time expires.
+ *
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least
+ * equal to trigger level is sent to the stream batching buffer. If the
+ * parameter is NULL, it will use the default implementation provided by
+ * sbSEND_COMPLETED macro. To enable the callback, configUSE_SB_COMPLETED_CALLBACK
+ * must be set to 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes
+ * are read from a stream batching buffer. If the parameter is NULL, it will use
+ * the default implementation provided by sbRECEIVE_COMPLETED macro. To enable
+ * the callback, configUSE_SB_COMPLETED_CALLBACK must be set to 1 in
+ * FreeRTOSConfig.h.
+ *
+ * @return If NULL is returned, then the stream batching buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream batching buffer data structures and storage area.  A non-NULL value
+ * being returned indicates that the stream batching buffer has been created
+ * successfully - the returned value should be stored as the handle to the
+ * created stream batching buffer.
+ *
+ * Example use:
+ * @code{c}
+ *
+ * void vAFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBatchingBuffer;
+ * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+ *
+ *  // Create a stream batching buffer that can hold 100 bytes.  The memory used
+ *  // to hold both the stream batching buffer structure and the data in the stream
+ *  // batching buffer is allocated dynamically.
+ *  xStreamBatchingBuffer = xStreamBatchingBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+ *
+ *  if( xStreamBatchingBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // stream batching buffer.
+ *  }
+ *  else
+ *  {
+ *      // The stream batching buffer was created successfully and can now be used.
+ *  }
+ * }
+ * @endcode
+ * \defgroup xStreamBatchingBufferCreate xStreamBatchingBufferCreate
+ * \ingroup StreamBatchingBufferManagement
+ */
+
+#define xStreamBatchingBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xStreamBatchingBufferCreateWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreate( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
+#endif
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * StreamBufferHandle_t xStreamBatchingBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                                         size_t xTriggerLevelBytes,
+ *                                                         uint8_t *pucStreamBufferStorageArea,
+ *                                                         StaticStreamBuffer_t *pxStaticStreamBuffer );
+ * @endcode
+ * Creates a new stream batching buffer using statically allocated memory.  See
+ * xStreamBatchingBufferCreate() for a version that uses dynamically allocated
+ * memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBatchingBufferCreateStatic() to be available. configUSE_STREAM_BUFFERS
+ * must be set to 1 in for FreeRTOSConfig.h for xStreamBatchingBufferCreateStatic()
+ * to be available.
+ *
+ * The difference between a stream buffer and a stream batching buffer is when
+ * a task performs read on a non-empty buffer:
+ * - The task reading from a non-empty stream buffer returns immediately
+ *   regardless of the amount of data in the buffer.
+ * - The task reading from a non-empty steam batching buffer blocks until the
+ *   amount of data in the buffer exceeds the trigger level or the block time
+ *   expires.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * batching buffer to unblock a task calling xStreamBufferReceive before the
+ * block time expires.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes big.  This is the array to which streams are
+ * copied when they are written to the stream batching buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream batching buffer's
+ * data structure.
+ *
+ * @param pxSendCompletedCallback Callback invoked when number of bytes at least
+ * equal to trigger level is sent to the stream batching buffer. If the parameter
+ * is NULL, it will use the default implementation provided by sbSEND_COMPLETED
+ * macro. To enable the callback, configUSE_SB_COMPLETED_CALLBACK must be set to
+ * 1 in FreeRTOSConfig.h.
+ *
+ * @param pxReceiveCompletedCallback Callback invoked when more than zero bytes
+ * are read from a stream batching buffer. If the parameter is NULL, it will use
+ * the default implementation provided by sbRECEIVE_COMPLETED macro. To enable
+ * the callback, configUSE_SB_COMPLETED_CALLBACK must be set to 1 in
+ * FreeRTOSConfig.h.
+ *
+ * @return If the stream batching buffer is created successfully then a handle
+ * to the created stream batching buffer is returned. If either pucStreamBufferStorageArea
+ * or pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+ * @code{c}
+ *
+ * // Used to dimension the array used to hold the streams.  The available space
+ * // will actually be one less than this, so 999.
+ * #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the streams within the stream
+ * // batching buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the stream batching buffer structure.
+ * StaticStreamBuffer_t xStreamBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBatchingBuffer;
+ * const size_t xTriggerLevel = 1;
+ *
+ *  xStreamBatchingBuffer = xStreamBatchingBufferCreateStatic( sizeof( ucStorageBuffer ),
+ *                                                             xTriggerLevel,
+ *                                                             ucStorageBuffer,
+ *                                                             &xStreamBufferStruct );
+ *
+ *  // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+ *  // parameters were NULL, xStreamBatchingBuffer will not be NULL, and can be
+ *  // used to reference the created stream batching buffer in other stream
+ *  // buffer API calls.
+ *
+ *  // Other code that uses the stream batching buffer can go here.
+ * }
+ *
+ * @endcode
+ * \defgroup xStreamBatchingBufferCreateStatic xStreamBatchingBufferCreateStatic
+ * \ingroup StreamBatchingBufferManagement
+ */
+
+#define xStreamBatchingBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), NULL, NULL )
+
+#if ( configUSE_SB_COMPLETED_CALLBACK == 1 )
+    #define xStreamBatchingBufferCreateStaticWithCallback( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer, pxSendCompletedCallback, pxReceiveCompletedCallback ) \
+    xStreamBufferGenericCreateStatic( ( xBufferSizeBytes ), ( xTriggerLevelBytes ), sbTYPE_STREAM_BATCHING_BUFFER, ( pucStreamBufferStorageArea ), ( pxStaticStreamBuffer ), ( pxSendCompletedCallback ), ( pxReceiveCompletedCallback ) )
 #endif
 
 /**
@@ -273,6 +472,9 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  * buffer and storage area buffer. These are the same buffers that are supplied
  * at the time of creation.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferGetStaticBuffers() to be available.
+ *
  * @param xStreamBuffer The stream buffer for which to retrieve the buffers.
  *
  * @param ppucStreamBufferStorageArea Used to return a pointer to the stream
@@ -297,9 +499,9 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  *
  * @code{c}
  * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
- *                        const void *pvTxData,
- *                        size_t xDataLengthBytes,
- *                        TickType_t xTicksToWait );
+ *                           const void *pvTxData,
+ *                           size_t xDataLengthBytes,
+ *                           TickType_t xTicksToWait );
  * @endcode
  *
  * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
@@ -312,17 +514,20 @@ typedef void (* StreamBufferCallbackFunction_t)( StreamBufferHandle_t xStreamBuf
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
  * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
  * service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSend() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer to which a stream is
  * being sent.
  *
@@ -394,9 +599,9 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
  *
  * @code{c}
  * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
- *                               const void *pvTxData,
- *                               size_t xDataLengthBytes,
- *                               BaseType_t *pxHigherPriorityTaskWoken );
+ *                                  const void *pvTxData,
+ *                                  size_t xDataLengthBytes,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
  * @endcode
  *
  * Interrupt safe version of the API function that sends a stream of bytes to
@@ -410,17 +615,20 @@ size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
  * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
  * service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSendFromISR() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer to which a stream is
  * being sent.
  *
@@ -495,9 +703,9 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
  *
  * @code{c}
  * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
- *                           void *pvRxData,
- *                           size_t xBufferLengthBytes,
- *                           TickType_t xTicksToWait );
+ *                              void *pvRxData,
+ *                              size_t xBufferLengthBytes,
+ *                              TickType_t xTicksToWait );
  * @endcode
  *
  * Receives bytes from a stream buffer.
@@ -510,17 +718,20 @@ size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
  * writer and reader to be different tasks or interrupts, but, unlike other
  * FreeRTOS objects, it is not safe to have multiple different writers or
  * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferReceive()) inside a critical section and set the receive
- * block time to 0.
+ * then the application writer must serialize calls to writing API functions
+ * (such as xStreamBufferSend()).  Likewise, if there are to be multiple
+ * different readers then the application writer must serialize calls to reading
+ * API functions (such as xStreamBufferReceive()).  One way to achieve such
+ * serialization in single core or SMP kernel is to place each API call inside a
+ * critical section and use a block time of 0.
  *
  * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
  * xStreamBufferReceiveFromISR() to read from a stream buffer from an
  * interrupt service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReceive() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer from which bytes are to
  * be received.
  *
@@ -584,9 +795,9 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
  *
  * @code{c}
  * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
- *                                  void *pvRxData,
- *                                  size_t xBufferLengthBytes,
- *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ *                                     void *pvRxData,
+ *                                     size_t xBufferLengthBytes,
+ *                                     BaseType_t *pxHigherPriorityTaskWoken );
  * @endcode
  *
  * An interrupt safe version of the API function that receives bytes from a
@@ -596,6 +807,9 @@ size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
  * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
  * interrupt service routine (ISR).
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReceiveFromISR() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer from which a stream
  * is being received.
  *
@@ -680,6 +894,9 @@ size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
  * A stream buffer handle must not be used after the stream buffer has been
  * deleted.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * vStreamBufferDelete() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer to be deleted.
  *
  * \defgroup vStreamBufferDelete vStreamBufferDelete
@@ -697,6 +914,9 @@ void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTI
  * Queries a stream buffer to see if it is full.  A stream buffer is full if it
  * does not have any free space, and therefore cannot accept any more data.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferIsFull() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being queried.
  *
  * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
@@ -717,6 +937,9 @@ BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_
  * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
  * it does not contain any data.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferIsEmpty() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being queried.
  *
  * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
@@ -739,6 +962,13 @@ BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED
  * are no tasks blocked waiting to either send to or receive from the stream
  * buffer.
  *
+ * Use xStreamBufferReset() to reset a stream buffer from a task.
+ * Use xStreamBufferResetFromISR() to reset a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReset() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being reset.
  *
  * @return If the stream buffer is reset then pdPASS is returned.  If there was
@@ -750,6 +980,38 @@ BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED
  */
 BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * An interrupt safe version of the API function that resets the stream buffer.
+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * Use xStreamBufferReset() to reset a stream buffer from a task.
+ * Use xStreamBufferResetFromISR() to reset a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferResetFromISR() to be available.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferResetFromISR xStreamBufferResetFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferResetFromISR( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
 /**
  * stream_buffer.h
  *
@@ -761,6 +1023,9 @@ BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_F
  * equal to the amount of data that can be sent to the stream buffer before it
  * is full.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSpacesAvailable() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being queried.
  *
  * @return The number of bytes that can be written to the stream buffer before
@@ -782,6 +1047,9 @@ size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVIL
  * the number of bytes that can be read from the stream buffer before the stream
  * buffer would be empty.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferBytesAvailable() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being queried.
  *
  * @return The number of bytes that can be read from the stream buffer before
@@ -816,6 +1084,9 @@ size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILE
  * A trigger level is set when the stream buffer is created, and can be modified
  * using xStreamBufferSetTriggerLevel().
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSetTriggerLevel() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer being updated.
  *
  * @param xTriggerLevel The new trigger level for the stream buffer.
@@ -850,6 +1121,9 @@ BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
  * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
  * additional information.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferSendCompletedFromISR() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer to which data was
  * written.
  *
@@ -891,6 +1165,9 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
  * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
  * additional information.
  *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * xStreamBufferReceiveCompletedFromISR() to be available.
+ *
  * @param xStreamBuffer The handle of the stream buffer from which data was
  * read.
  *
@@ -911,21 +1188,79 @@ BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer
 BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
                                                  BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
 
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer );
+ * @endcode
+ *
+ * Get the task notification index used for the supplied stream buffer which can
+ * be set using vStreamBufferSetStreamBufferNotificationIndex. If the task
+ * notification index for the stream buffer is not changed using
+ * vStreamBufferSetStreamBufferNotificationIndex, this function returns the
+ * default value (tskDEFAULT_INDEX_TO_NOTIFY).
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * uxStreamBufferGetStreamBufferNotificationIndex() to be available.
+ *
+ * @param xStreamBuffer The handle of the stream buffer for which the task
+ * notification index is retrieved.
+ *
+ * @return The task notification index for the stream buffer.
+ *
+ * \defgroup uxStreamBufferGetStreamBufferNotificationIndex uxStreamBufferGetStreamBufferNotificationIndex
+ * \ingroup StreamBufferManagement
+ */
+UBaseType_t uxStreamBufferGetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * @code{c}
+ * void vStreamBufferSetStreamBufferNotificationIndex ( StreamBuffer_t xStreamBuffer, UBaseType_t uxNotificationIndex );
+ * @endcode
+ *
+ * Set the task notification index used for the supplied stream buffer.
+ * Successive calls to stream buffer APIs (like xStreamBufferSend or
+ * xStreamBufferReceive) for this stream buffer will use this new index for
+ * their task notifications.
+ *
+ * If this function is not called, the default index (tskDEFAULT_INDEX_TO_NOTIFY)
+ * is used for task notifications. It is recommended to call this function
+ * before attempting to send or receive data from the stream buffer to avoid
+ * inconsistencies.
+ *
+ * configUSE_STREAM_BUFFERS must be set to 1 in for FreeRTOSConfig.h for
+ * vStreamBufferSetStreamBufferNotificationIndex() to be available.
+ *
+ * @param xStreamBuffer The handle of the stream buffer for which the task
+ * notification index is set.
+ *
+ * @param uxNotificationIndex The task notification index to set.
+ *
+ * \defgroup vStreamBufferSetStreamBufferNotificationIndex vStreamBufferSetStreamBufferNotificationIndex
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferSetStreamBufferNotificationIndex( StreamBufferHandle_t xStreamBuffer,
+                                                    UBaseType_t uxNotificationIndex ) PRIVILEGED_FUNCTION;
+
 /* Functions below here are not part of the public API. */
 StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
                                                  size_t xTriggerLevelBytes,
-                                                 BaseType_t xIsMessageBuffer,
+                                                 BaseType_t xStreamBufferType,
                                                  StreamBufferCallbackFunction_t pxSendCompletedCallback,
                                                  StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
 
-
-StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-                                                       size_t xTriggerLevelBytes,
-                                                       BaseType_t xIsMessageBuffer,
-                                                       uint8_t * const pucStreamBufferStorageArea,
-                                                       StaticStreamBuffer_t * const pxStaticStreamBuffer,
-                                                       StreamBufferCallbackFunction_t pxSendCompletedCallback,
-                                                       StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                           size_t xTriggerLevelBytes,
+                                                           BaseType_t xStreamBufferType,
+                                                           uint8_t * const pucStreamBufferStorageArea,
+                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer,
+                                                           StreamBufferCallbackFunction_t pxSendCompletedCallback,
+                                                           StreamBufferCallbackFunction_t pxReceiveCompletedCallback ) PRIVILEGED_FUNCTION;
+#endif
 
 size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
 

include/timers.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -34,10 +34,8 @@
     #error "include FreeRTOS.h must appear in source files before include timers.h"
 #endif
 
-/*lint -save -e537 This headers are only multiply included if the application code
- * happens to also be including task.h. */
 #include "task.h"
-/*lint -restore */
+
 
 /* *INDENT-OFF* */
 #ifdef __cplusplus
@@ -88,8 +86,8 @@ typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer );
  * Defines the prototype to which functions used with the
  * xTimerPendFunctionCallFromISR() function must conform.
  */
-typedef void (* PendedFunction_t)( void *,
-                                   uint32_t );
+typedef void (* PendedFunction_t)( void * arg1,
+                                   uint32_t arg2 );
 
 /**
  * TimerHandle_t xTimerCreate(  const char * const pcTimerName,
@@ -229,7 +227,7 @@ typedef void (* PendedFunction_t)( void *,
  * @endverbatim
  */
 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-    TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    TimerHandle_t xTimerCreate( const char * const pcTimerName,
                                 const TickType_t xTimerPeriodInTicks,
                                 const BaseType_t xAutoReload,
                                 void * const pvTimerID,
@@ -359,7 +357,7 @@ typedef void (* PendedFunction_t)( void *,
  * @endverbatim
  */
 #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
-    TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    TimerHandle_t xTimerCreateStatic( const char * const pcTimerName,
                                       const TickType_t xTimerPeriodInTicks,
                                       const BaseType_t xAutoReload,
                                       void * const pvTimerID,
@@ -739,14 +737,18 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
  * // The key press event handler.
  * void vKeyPressEventHandler( char cKey )
  * {
- *     // Ensure the LCD back-light is on, then reset the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
- *     // if it cannot be sent immediately.
- *     vSetBacklightState( BACKLIGHT_ON );
- *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     // Reset the timer that is responsible for turning the back-light off after
+ *     // 5 seconds of key inactivity. Wait 10 ticks for the command to be
+ *     // successfully sent if it cannot be sent immediately.
+ *     if( xTimerReset( xBacklightTimer, 10 ) == pdPASS )
  *     {
- *         // The reset command was not executed successfully.  Take appropriate
+ *        // Turn on the LCD back-light. It will be turned off in the
+ *        // vBacklightTimerCallback after 5 seconds of key inactivity.
+ *        vSetBacklightState( BACKLIGHT_ON );
+ *      }
+ *     else
+ *     {
+ *         // The reset command was not executed successfully. Take appropriate
  *         // action here.
  *     }
  *
@@ -755,16 +757,15 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
  *
  * void main( void )
  * {
- * int32_t x;
  *
  *     // Create then start the one-shot timer that is responsible for turning
  *     // the back-light off if no keys are pressed within a 5 second period.
  *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
- *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdMS_TO_TICKS( 5000 ),      // The timer period in ticks.
  *                                     pdFALSE,                    // The timer is a one-shot timer.
  *                                     0,                          // The id is not used by the callback so can take any value.
  *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
- *                                   );
+ *                                    );
  *
  *     if( xBacklightTimer == NULL )
  *     {
@@ -1198,10 +1199,12 @@ TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
  *  }
  * @endverbatim
  */
-BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
-                                          void * pvParameter1,
-                                          uint32_t ulParameter2,
-                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+    BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+                                              void * pvParameter1,
+                                              uint32_t ulParameter2,
+                                              BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
@@ -1235,10 +1238,12 @@ BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
  * timer daemon task, otherwise pdFALSE is returned.
  *
  */
-BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
-                                   void * pvParameter1,
-                                   uint32_t ulParameter2,
-                                   TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+    BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+                                       void * pvParameter1,
+                                       uint32_t ulParameter2,
+                                       TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#endif
 
 /**
  * const char * const pcTimerGetName( TimerHandle_t xTimer );
@@ -1249,7 +1254,7 @@ BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
  *
  * @return The name assigned to the timer specified by the xTimer parameter.
  */
-const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
 
 /**
  * void vTimerSetReloadMode( TimerHandle_t xTimer, const BaseType_t xAutoReload );
@@ -1348,12 +1353,29 @@ TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
  * for use by the kernel only.
  */
 BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
-BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
-                                 const BaseType_t xCommandID,
-                                 const TickType_t xOptionalValue,
-                                 BaseType_t * const pxHigherPriorityTaskWoken,
-                                 const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
 
+/*
+ * Splitting the xTimerGenericCommand into two sub functions and making it a macro
+ * removes a recursion path when called from ISRs. This is primarily for the XCore
+ * XCC port which detects the recursion path and throws an error during compilation
+ * when this is not split.
+ */
+BaseType_t xTimerGenericCommandFromTask( TimerHandle_t xTimer,
+                                         const BaseType_t xCommandID,
+                                         const TickType_t xOptionalValue,
+                                         BaseType_t * const pxHigherPriorityTaskWoken,
+                                         const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+BaseType_t xTimerGenericCommandFromISR( TimerHandle_t xTimer,
+                                        const BaseType_t xCommandID,
+                                        const TickType_t xOptionalValue,
+                                        BaseType_t * const pxHigherPriorityTaskWoken,
+                                        const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#define xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait )         \
+    ( ( xCommandID ) < tmrFIRST_FROM_ISR_COMMAND ?                                                                  \
+      xTimerGenericCommandFromTask( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) : \
+      xTimerGenericCommandFromISR( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait ) )
 #if ( configUSE_TRACE_FACILITY == 1 )
     void vTimerSetTimerNumber( TimerHandle_t xTimer,
                                UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
@@ -1365,7 +1387,7 @@ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
 /**
  * task.h
  * @code{c}
- * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
+ * void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, configSTACK_DEPTH_TYPE * puxTimerTaskStackSize )
  * @endcode
  *
  * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB.  This function is required when
@@ -1373,11 +1395,11 @@ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
  *
  * @param ppxTimerTaskTCBBuffer   A handle to a statically allocated TCB buffer
  * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for the idle task
- * @param pulTimerTaskStackSize   A pointer to the number of elements that will fit in the allocated stack buffer
+ * @param puxTimerTaskStackSize   A pointer to the number of elements that will fit in the allocated stack buffer
  */
     void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
                                          StackType_t ** ppxTimerTaskStackBuffer,
-                                         uint32_t * pulTimerTaskStackSize );
+                                         configSTACK_DEPTH_TYPE * puxTimerTaskStackSize );
 
 #endif
 
@@ -1391,10 +1413,19 @@ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
  *
  * This hook function is called form the timer task once when the task starts running.
  */
+    /* MISRA Ref 8.6.1 [External linkage] */
+    /* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-86 */
+    /* coverity[misra_c_2012_rule_8_6_violation] */
     void vApplicationDaemonTaskStartupHook( void );
 
 #endif
 
+/*
+ * This function resets the internal state of the timer module. It must be called
+ * by the application before restarting the scheduler.
+ */
+void vTimerResetState( void ) PRIVILEGED_FUNCTION;
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }

list.c

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -37,11 +37,10 @@
 #include "FreeRTOS.h"
 #include "list.h"
 
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
- * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
+/* The MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
  * defined for the header files above, but not in this file, in order to
  * generate the correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
 /*-----------------------------------------------------------
 * PUBLIC LIST API documented in list.h
@@ -49,10 +48,12 @@
 
 void vListInitialise( List_t * const pxList )
 {
+    traceENTER_vListInitialise( pxList );
+
     /* The list structure contains a list item which is used to mark the
      * end of the list.  To initialise the list the list end is inserted
      * as the only list entry. */
-    pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+    pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );
 
     listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( &( pxList->xListEnd ) );
 
@@ -62,8 +63,8 @@ void vListInitialise( List_t * const pxList )
 
     /* The list end next and previous pointers point to itself so we know
      * when the list is empty. */
-    pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );     /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-    pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+    pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );
+    pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );
 
     /* Initialize the remaining fields of xListEnd when it is a proper ListItem_t */
     #if ( configUSE_MINI_LIST_ITEM == 0 )
@@ -80,11 +81,15 @@ void vListInitialise( List_t * const pxList )
      * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
     listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
     listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+
+    traceRETURN_vListInitialise();
 }
 /*-----------------------------------------------------------*/
 
 void vListInitialiseItem( ListItem_t * const pxItem )
 {
+    traceENTER_vListInitialiseItem( pxItem );
+
     /* Make sure the list item is not recorded as being on a list. */
     pxItem->pxContainer = NULL;
 
@@ -92,6 +97,8 @@ void vListInitialiseItem( ListItem_t * const pxItem )
      * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
     listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
     listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+
+    traceRETURN_vListInitialiseItem();
 }
 /*-----------------------------------------------------------*/
 
@@ -100,6 +107,8 @@ void vListInsertEnd( List_t * const pxList,
 {
     ListItem_t * const pxIndex = pxList->pxIndex;
 
+    traceENTER_vListInsertEnd( pxList, pxNewListItem );
+
     /* Only effective when configASSERT() is also defined, these tests may catch
      * the list data structures being overwritten in memory.  They will not catch
      * data errors caused by incorrect configuration or use of FreeRTOS. */
@@ -121,7 +130,9 @@ void vListInsertEnd( List_t * const pxList,
     /* Remember which list the item is in. */
     pxNewListItem->pxContainer = pxList;
 
-    ( pxList->uxNumberOfItems )++;
+    ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems + 1U );
+
+    traceRETURN_vListInsertEnd();
 }
 /*-----------------------------------------------------------*/
 
@@ -131,6 +142,8 @@ void vListInsert( List_t * const pxList,
     ListItem_t * pxIterator;
     const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 
+    traceENTER_vListInsert( pxList, pxNewListItem );
+
     /* Only effective when configASSERT() is also defined, these tests may catch
      * the list data structures being overwritten in memory.  They will not catch
      * data errors caused by incorrect configuration or use of FreeRTOS. */
@@ -153,7 +166,7 @@ void vListInsert( List_t * const pxList,
     {
         /* *** NOTE ***********************************************************
         *  If you find your application is crashing here then likely causes are
-        *  listed below.  In addition see https://www.FreeRTOS.org/FAQHelp.html for
+        *  listed below.  In addition see https://www.freertos.org/Why-FreeRTOS/FAQs for
         *  more tips, and ensure configASSERT() is defined!
         *  https://www.FreeRTOS.org/a00110.html#configASSERT
         *
@@ -176,10 +189,12 @@ void vListInsert( List_t * const pxList,
         *      configMAX_SYSCALL_INTERRUPT_PRIORITY.
         **********************************************************************/
 
-        for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+        for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext )
         {
             /* There is nothing to do here, just iterating to the wanted
-             * insertion position. */
+             * insertion position.
+             * IF YOU FIND YOUR CODE STUCK HERE, SEE THE NOTE JUST ABOVE.
+             */
         }
     }
 
@@ -192,16 +207,21 @@ void vListInsert( List_t * const pxList,
      * item later. */
     pxNewListItem->pxContainer = pxList;
 
-    ( pxList->uxNumberOfItems )++;
+    ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems + 1U );
+
+    traceRETURN_vListInsert();
 }
 /*-----------------------------------------------------------*/
 
+
 UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
 {
-/* The list item knows which list it is in.  Obtain the list from the list
- * item. */
+    /* The list item knows which list it is in.  Obtain the list from the list
+     * item. */
     List_t * const pxList = pxItemToRemove->pxContainer;
 
+    traceENTER_uxListRemove( pxItemToRemove );
+
     pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
     pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
 
@@ -219,7 +239,9 @@ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
     }
 
     pxItemToRemove->pxContainer = NULL;
-    ( pxList->uxNumberOfItems )--;
+    ( pxList->uxNumberOfItems ) = ( UBaseType_t ) ( pxList->uxNumberOfItems - 1U );
+
+    traceRETURN_uxListRemove( pxList->uxNumberOfItems );
 
     return pxList->uxNumberOfItems;
 }

manifest.yml

@@ -1,4 +1,4 @@
 name : "FreeRTOS-Kernel"
-version: "v10.5.1"
+version: "V11.0.1+"
 description: "FreeRTOS Kernel."
 license: "MIT"

portable/ARMv8M/ReadMe.txt

@@ -1,4 +1,4 @@
-This directory tree contains the master copy of the FreeeRTOS Armv8-M and
+This directory tree contains the master copy of the FreeRTOS Armv8-M and
 Armv8.1-M ports.
 Do not use the files located here!  These file are copied into separate
 FreeRTOS/Source/portable/[compiler]/ARM_CM[23|33|55|85]_NNN directories prior to each

portable/ARMv8M/copy_files.py

@@ -1,6 +1,6 @@
 #/*
 # * FreeRTOS Kernel <DEVELOPMENT BRANCH>
-# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+# * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 # *
 # * SPDX-License-Identifier: MIT
 # *

portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -46,133 +49,119 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   movs r3, #1                                   \n" /* r3 = 1. */
-        "   orrs r2, r3                                   \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    subs r2, #20                                 \n"
-        "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
-        "    subs r2, #20                                 \n"
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    mov lr, r6                                   \n"
-        "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r2, #48                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r2, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xSecureContextConst2: .word xSecureContext      \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   movs r3, #1                                   \n" /* r3 = 1. */
+            "   orrs r2, r3                                   \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    subs r2, #20                                 \n"
+            "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
+            "    subs r2, #20                                 \n"
+            "    msr psp, r3                                  \n"
+            "    msr control, r5                              \n"
+            "    mov lr, r6                                   \n"
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r2, #48                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r2, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r3, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r3]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r3}                               \n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-        "   ldr  r4, xSecureContextConst2                   \n"
-        "   str  r1, [r4]                                   \n"/* Set xSecureContext to this task's value for the same. */
-        "   msr  psplim, r2                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   bx   r3                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-        "xSecureContextConst2: .word xSecureContext         \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "   ldr  r4, =xSecureContext                        \n"
+            "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -183,17 +172,15 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   tst r0, r1                                      \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-        "   beq running_privileged                          \n"/* If the result of previous AND operation was 0, branch. */
-        "   movs r0, #0                                     \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   tst r0, r1                                      \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "   beq running_privileged                          \n" /* If the result of previous AND operation was 0, branch. */
+        "   movs r0, #0                                     \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   bx lr                                           \n" /* Return. */
         " running_privileged:                               \n"
-        "   movs r0, #1                                     \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
+        "   movs r0, #1                                     \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -205,11 +192,11 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* Read the CONTROL register. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   bics r0, r1                                     \n"/* Clear the bit 0. */
-        "   msr control, r0                                 \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* Read the CONTROL register. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   bics r0, r1                                     \n" /* Clear the bit 0. */
+        "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -221,11 +208,11 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   orrs r0, r1                                     \n"/* r0 = r0 | r1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   orrs r0, r1                                     \n" /* r0 = r0 | r1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -237,18 +224,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -283,328 +267,306 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        " .extern SecureContext_SaveContext               \n"
-        " .extern SecureContext_LoadContext               \n"
-        "                                                 \n"
-        " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
-        " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
-        "                                                 \n"
-        " cbz r0, save_ns_context                         \n" /* No secure context to save. */
-        " save_s_context:                                 \n"
-        "    push {r0-r2, lr}                             \n"
-        "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r0-r3}                                  \n" /* LR is now in r3. */
-        "    mov lr, r3                                   \n" /* Restore LR. */
-        "                                                 \n"
-        " save_ns_context:                                \n"
-        "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
-        "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    mrs r3, psp                                  \n"
-        "    stmia r2!, {r4-r7}                           \n" /* Store r4-r7. */
-        "    mov r4, r8                                   \n" /* r4 = r8. */
-        "    mov r5, r9                                   \n" /* r5 = r9. */
-        "    mov r6, r10                                  \n" /* r6 = r10. */
-        "    mov r7, r11                                  \n" /* r7 = r11. */
-        "    stmia r2!, {r4-r7}                           \n" /* Store r8-r11. */
-        "    ldmia r3!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
-        "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "    ldmia r3!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
-        "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psp                                  \n" /* r3 = PSP. */
-        "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
-        "    mrs r5, control                              \n" /* r5 = CONTROL. */
-        "    mov r6, lr                                   \n" /* r6 = LR. */
-        "    stmia r2!, {r0, r3-r6}                       \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    cpsid i                                      \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    cpsie i                                      \n"
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    subs r2, #20                                 \n"
-        "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
-        "    subs r2, #20                                 \n"
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    mov lr, r6                                   \n"
-        "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
-        "                                                 \n"
-        " restore_s_context:                              \n"
-        "    push {r1-r3, lr}                             \n"
-        "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r1-r4}                                  \n" /* LR is now in r4. */
-        "    mov lr, r4                                   \n"
-        "                                                 \n"
-        " restore_ns_context:                             \n"
-        "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
-        "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r2, #48                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r2, #32                                 \n"
-        "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r2, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xSecureContextConst: .word xSecureContext       \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
+            " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r3}                                  \n" /* LR is now in r3. */
+            "    mov lr, r3                                   \n" /* Restore LR. */
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    mrs r3, psp                                  \n"
+            "    stmia r2!, {r4-r7}                           \n" /* Store r4-r7. */
+            "    mov r4, r8                                   \n" /* r4 = r8. */
+            "    mov r5, r9                                   \n" /* r5 = r9. */
+            "    mov r6, r10                                  \n" /* r6 = r10. */
+            "    mov r7, r11                                  \n" /* r7 = r11. */
+            "    stmia r2!, {r4-r7}                           \n" /* Store r8-r11. */
+            "    ldmia r3!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
+            "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "    ldmia r3!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
+            "    stmia r2!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psp                                  \n" /* r3 = PSP. */
+            "    movs r4, #0                                  \n" /* r4 = 0. 0 is stored in the PSPLIM slot. */
+            "    mrs r5, control                              \n" /* r5 = CONTROL. */
+            "    mov r6, lr                                   \n" /* r6 = LR. */
+            "    stmia r2!, {r0, r3-r6}                       \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    cpsid i                                      \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    cpsie i                                      \n"
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    subs r2, #20                                 \n"
+            "    ldmia r2!, {r0, r3-r6}                       \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
+            "    subs r2, #20                                 \n"
+            "    msr psp, r3                                  \n"
+            "    msr control, r5                              \n"
+            "    mov lr, r6                                   \n"
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r4}                                  \n" /* LR is now in r4. */
+            "    mov lr, r4                                   \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r2!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r3!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r2, #48                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r2, #32                                 \n"
+            "    ldmia r2!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r2, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "   .extern SecureContext_SaveContext               \n"
-        "   .extern SecureContext_LoadContext               \n"
-        "                                                   \n"
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   ldr r0, [r3]                                    \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
-        "   mrs r2, psp                                     \n"/* Read PSP in r2. */
-        "                                                   \n"
-        "   cbz r0, save_ns_context                         \n"/* No secure context to save. */
-        "   push {r0-r2, r14}                               \n"
-        "   bl SecureContext_SaveContext                    \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r0-r3}                                     \n"/* LR is now in r3. */
-        "   mov lr, r3                                      \n"/* LR = r3. */
-        "   lsls r1, r3, #25                                \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl save_ns_context                             \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   subs r2, r2, #12                                \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "   b select_next_task                              \n"
-        "                                                   \n"
-        " save_ns_context:                                  \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   subs r2, r2, #44                                \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3-r7}                      \n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
-        "   mov r4, r8                                      \n"/* r4 = r8. */
-        "   mov r5, r9                                      \n"/* r5 = r9. */
-        "   mov r6, r10                                     \n"/* r6 = r10. */
-        "   mov r7, r11                                     \n"/* r7 = r11. */
-        "   stmia r2!, {r4-r7}                              \n"/* Store the high registers that are not saved automatically. */
-        "                                                   \n"
-        " select_next_task:                                 \n"
-        "   cpsid i                                         \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   cpsie i                                         \n"
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r2, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r2!, {r0, r1, r4}                         \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        "   msr psplim, r1                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   str r0, [r3]                                    \n"/* Restore the task's xSecureContext. */
-        "   cbz r0, restore_ns_context                      \n"/* If there is no secure context for the task, restore the non-secure context. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   push {r2, r4}                                   \n"
-        "   bl SecureContext_LoadContext                    \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r2, r4}                                    \n"
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   lsls r1, r4, #25                                \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl restore_ns_context                          \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        " restore_ns_context:                               \n"
-        "   adds r2, r2, #16                                \n"/* Move to the high registers. */
-        "   ldmia r2!, {r4-r7}                              \n"/* Restore the high registers that are not automatically restored. */
-        "   mov r8, r4                                      \n"/* r8 = r4. */
-        "   mov r9, r5                                      \n"/* r9 = r5. */
-        "   mov r10, r6                                     \n"/* r10 = r6. */
-        "   mov r11, r7                                     \n"/* r11 = r7. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   subs r2, r2, #32                                \n"/* Go back to the low registers. */
-        "   ldmia r2!, {r4-r7}                              \n"/* Restore the low registers that are not automatically restored. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        "xSecureContextConst: .word xSecureContext          \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "   .extern SecureContext_SaveContext               \n"
+            "   .extern SecureContext_LoadContext               \n"
+            "                                                   \n"
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later.*/
+            "   mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                   \n"
+            "   cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            "   push {r0-r2, r14}                               \n"
+            "   bl SecureContext_SaveContext                    \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r0-r3}                                     \n" /* LR is now in r3. */
+            "   mov lr, r3                                      \n" /* LR = r3. */
+            "   lsls r1, r3, #25                                \n" /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl save_ns_context                             \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   subs r2, r2, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   movs r1, #0                                     \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r2!, {r0, r1, r3}                         \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+            "   b select_next_task                              \n"
+            "                                                   \n"
+            " save_ns_context:                                  \n"
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   subs r2, r2, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "   str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "   movs r1, #0                                     \n" /* r1 = 0. 0 is stored in the PSPLIM slot. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r2!, {r0, r1, r3-r7}                      \n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+            "   mov r4, r8                                      \n" /* r4 = r8. */
+            "   mov r5, r9                                      \n" /* r5 = r9. */
+            "   mov r6, r10                                     \n" /* r6 = r10. */
+            "   mov r7, r11                                     \n" /* r7 = r11. */
+            "   stmia r2!, {r4-r7}                              \n" /* Store the high registers that are not saved automatically. */
+            "                                                   \n"
+            " select_next_task:                                 \n"
+            "   cpsid i                                         \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   cpsie i                                         \n"
+            "                                                   \n"
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r2, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                   \n"
+            "   ldmia r2!, {r0, r1, r4}                         \n" /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "   str r0, [r3]                                    \n" /* Restore the task's xSecureContext. */
+            "   cbz r0, restore_ns_context                      \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "   ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r3]                                    \n" /* Read pxCurrentTCB. */
+            "   push {r2, r4}                                   \n"
+            "   bl SecureContext_LoadContext                    \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "   pop {r2, r4}                                    \n"
+            "   mov lr, r4                                      \n" /* LR = r4. */
+            "   lsls r1, r4, #25                                \n" /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "   bpl restore_ns_context                          \n" /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   bx lr                                           \n"
+            "                                                   \n"
+            " restore_ns_context:                               \n"
+            "   adds r2, r2, #16                                \n" /* Move to the high registers. */
+            "   ldmia r2!, {r4-r7}                              \n" /* Restore the high registers that are not automatically restored. */
+            "   mov r8, r4                                      \n" /* r8 = r4. */
+            "   mov r9, r5                                      \n" /* r9 = r5. */
+            "   mov r10, r6                                     \n" /* r10 = r6. */
+            "   mov r11, r7                                     \n" /* r11 = r7. */
+            "   msr psp, r2                                     \n" /* Remember the new top of stack for the task. */
+            "   subs r2, r2, #32                                \n" /* Go back to the low registers. */
+            "   ldmia r2!, {r4-r7}                              \n" /* Restore the low registers that are not automatically restored. */
+            "   bx lr                                           \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "movs r0, #4                    \n"
-        "mov r1, lr                     \n"
-        "tst r0, r1                     \n"
-        "beq stack_on_msp               \n"
-        "stack_on_psp:                  \n"
-        "    mrs r0, psp                \n"
-        "    b route_svc                \n"
-        "stack_on_msp:                  \n"
-        "    mrs r0, msp                \n"
-        "    b route_svc                \n"
-        "                               \n"
-        "route_svc:                     \n"
-        "    ldr r2, [r0, #24]          \n"
-        "    subs r2, #2                \n"
-        "    ldrb r3, [r2, #0]          \n"
-        "    cmp r3, %0                 \n"
-        "    beq system_call_enter      \n"
-        "    cmp r3, %1                 \n"
-        "    beq system_call_enter_1    \n"
-        "    cmp r3, %2                 \n"
-        "    beq system_call_exit       \n"
-        "    b vPortSVCHandler_C        \n"
-        "                               \n"
-        "system_call_enter:             \n"
-        "    b vSystemCallEnter         \n"
-        "system_call_enter_1:           \n"
-        "    b vSystemCallEnter_1       \n"
-        "system_call_exit:              \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "r3", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "movs r0, #4                    \n"
+            "mov r1, lr                     \n"
+            "tst r0, r1                     \n"
+            "beq stack_on_msp               \n"
+            "stack_on_psp:                  \n"
+            "    mrs r0, psp                \n"
+            "    b route_svc                \n"
+            "stack_on_msp:                  \n"
+            "    mrs r0, msp                \n"
+            "    b route_svc                \n"
+            "                               \n"
+            "route_svc:                     \n"
+            "    ldr r3, [r0, #24]          \n"
+            "    subs r3, #2                \n"
+            "    ldrb r2, [r3, #0]          \n"
+            "    cmp r2, %0                 \n"
+            "    blt system_call_enter      \n"
+            "    cmp r2, %1                 \n"
+            "    beq system_call_exit       \n"
+            "    b vPortSVCHandler_C        \n"
+            "                               \n"
+            "system_call_enter:             \n"
+            "    b vSystemCallEnter         \n"
+            "system_call_exit:              \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "r3", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   movs r0, #4                                     \n"
-        "   mov r1, lr                                      \n"
-        "   tst r0, r1                                      \n"
-        "   beq stacking_used_msp                           \n"
-        "   mrs r0, psp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        " stacking_used_msp:                                \n"
-        "   mrs r0, msp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   movs r0, #4                                     \n"
+            "   mov r1, lr                                      \n"
+            "   tst r0, r1                                      \n"
+            "   beq stacking_used_msp                           \n"
+            "   mrs r0, psp                                     \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
+            "   bx r2                                           \n"
+            " stacking_used_msp:                                \n"
+            "   mrs r0, msp                                     \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
+            "   bx r2                                           \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -615,8 +577,8 @@ void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   svc %0                                          \n"/* Secure context is allocated in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
     );
 }
@@ -628,14 +590,14 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r2, [r0]                                    \n"/* The first item in the TCB is the top of the stack. */
-        "   ldr r1, [r2]                                    \n"/* The first item on the stack is the task's xSecureContext. */
-        "   cmp r1, #0                                      \n"/* Raise svc if task's xSecureContext is not NULL. */
-        "   bne free_secure_context                         \n"/* Branch if r1 != 0. */
-        "   bx lr                                           \n"/* There is no secure context (xSecureContext is NULL). */
+        "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
+        "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
+        "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
+        "   bne free_secure_context                         \n" /* Branch if r1 != 0. */
+        "   bx lr                                           \n" /* There is no secure context (xSecureContext is NULL). */
         " free_secure_context:                              \n"
-        "   svc %0                                          \n"/* Secure context is freed in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is freed in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
     );
 }

portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -48,9 +48,10 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -60,6 +61,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif ( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**

portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -36,6 +36,9 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
@@ -46,127 +49,121 @@
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    subs r1, #16                                 \n"
-        "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
-        "    subs r1, #16                                 \n"
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "    mov lr, r5                                   \n"
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r1, #48                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r1, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+            "    subs r1, #16                                 \n"
+            "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
+            "    subs r1, #16                                 \n"
+            "    msr psp, r2                                  \n"
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "    msr psplim, r3                           \n"
+            #endif
+            "    msr control, r4                              \n"
+            "    mov lr, r5                                   \n"
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r1, #48                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r1, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r1, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r1]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r2}                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-        "   msr  psplim, r1                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   bx   r2                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "   msr  psplim, r1                             \n" /* Set this task's PSPLIM value. */
+            #endif
+            "   movs r1, #2                                     \n" /* r1 = 2. */
+            "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -177,17 +174,15 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   tst r0, r1                                      \n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-        "   beq running_privileged                          \n"/* If the result of previous AND operation was 0, branch. */
-        "   movs r0, #0                                     \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   bx lr                                           \n"/* Return. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   tst r0, r1                                      \n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "   beq running_privileged                          \n" /* If the result of previous AND operation was 0, branch. */
+        "   movs r0, #0                                     \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   bx lr                                           \n" /* Return. */
         " running_privileged:                               \n"
-        "   movs r0, #1                                     \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
+        "   movs r0, #1                                     \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -199,11 +194,11 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs  r0, control                                \n"/* Read the CONTROL register. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   bics r0, r1                                     \n"/* Clear the bit 0. */
-        "   msr  control, r0                                \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs  r0, control                                \n" /* Read the CONTROL register. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   bics r0, r1                                     \n" /* Clear the bit 0. */
+        "   msr  control, r0                                \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -215,11 +210,11 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   movs r1, #1                                     \n"/* r1 = 1. */
-        "   orrs r0, r1                                     \n"/* r0 = r0 | r1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   movs r1, #1                                     \n" /* r1 = 1. */
+        "   orrs r0, r1                                     \n" /* r0 = r0 | r1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "r1", "memory"
     );
 }
@@ -231,18 +226,15 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -277,254 +269,248 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
-        " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
-        " mrs r2, psp                                     \n" /* r2 = PSP. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    stmia r1!, {r4-r7}                           \n" /* Store r4-r7. */
-        "    mov r4, r8                                   \n" /* r4 = r8. */
-        "    mov r5, r9                                   \n" /* r5 = r9. */
-        "    mov r6, r10                                  \n" /* r6 = r10. */
-        "    mov r7, r11                                  \n" /* r7 = r11. */
-        "    stmia r1!, {r4-r7}                           \n" /* Store r8-r11. */
-        "    ldmia r2!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
-        "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "    ldmia r2!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
-        "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r2, psp                                  \n" /* r2 = PSP. */
-        "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
-        "    mrs r4, control                              \n" /* r4 = CONTROL. */
-        "    mov r5, lr                                   \n" /* r5 = LR. */
-        "    stmia r1!, {r2-r5}                           \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    cpsid i                                      \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    cpsie i                                      \n"
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
-        "    movs r3, #5                                  \n" /* r3 = 5. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 5. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
-        "    movs r3, #6                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 6. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
-        "    movs r3, #7                                  \n" /* r3 = 6. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 7. */
-        "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    movs r3, #1                                  \n" /* r3 = 1. */
-        "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    subs r1, #16                                 \n"
-        "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
-        "    subs r1, #16                                 \n"
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "    mov lr, r5                                   \n"
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
-        "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
-        "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
-        "    subs r1, #48                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
-        "    mov r8, r4                                   \n" /* r8 = r4. */
-        "    mov r9, r5                                   \n" /* r9 = r5. */
-        "    mov r10, r6                                  \n" /* r10 = r6. */
-        "    mov r11, r7                                  \n" /* r11 = r7. */
-        "    subs r1, #32                                 \n"
-        "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
-        "    subs r1, #16                                 \n"
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
+            " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
+            " mrs r2, psp                                     \n" /* r2 = PSP. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    stmia r1!, {r4-r7}                           \n" /* Store r4-r7. */
+            "    mov r4, r8                                   \n" /* r4 = r8. */
+            "    mov r5, r9                                   \n" /* r5 = r9. */
+            "    mov r6, r10                                  \n" /* r6 = r10. */
+            "    mov r7, r11                                  \n" /* r7 = r11. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store r8-r11. */
+            "    ldmia r2!, {r4-r7}                           \n" /* Copy half of the  hardware saved context into r4-r7. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "    ldmia r2!, {r4-r7}                           \n" /* Copy rest half of the  hardware saved context into r4-r7. */
+            "    stmia r1!, {r4-r7}                           \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r2, psp                                  \n" /* r2 = PSP. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "    mrs r3, psplim                           \n" /* r3 = PSPLIM. */
+            #else
+                "    movs r3, #0                              \n" /* r3 = 0. 0 is stored in the PSPLIM slot. */
+            #endif
+            "    mrs r4, control                              \n" /* r4 = CONTROL. */
+            "    mov r5, lr                                   \n" /* r5 = LR. */
+            "    stmia r1!, {r2-r5}                           \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+            "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    cpsid i                                      \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    cpsie i                                      \n"
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    bics r2, r3                                  \n" /* r2 = r2 & ~r3 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read first set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write first set of RBAR/RLAR registers. */
+            "    movs r3, #5                                  \n" /* r3 = 5. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 5. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read second set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write second set of RBAR/RLAR registers. */
+            "    movs r3, #6                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 6. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read third set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write third set of RBAR/RLAR registers. */
+            "    movs r3, #7                                  \n" /* r3 = 6. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 7. */
+            "    ldmia r0!, {r4-r5}                           \n" /* Read fourth set of RBAR/RLAR registers from TCB. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "    stmia r2!, {r4-r5}                           \n" /* Write fourth set of RBAR/RLAR registers. */
+            "                                                 \n"
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    movs r3, #1                                  \n" /* r3 = 1. */
+            "    orrs r2, r3                                  \n" /* r2 = r2 | r3 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+            "    subs r1, #16                                 \n"
+            "    ldmia r1!, {r2-r5}                           \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
+            "    subs r1, #16                                 \n"
+            "    msr psp, r2                                  \n"
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "    msr psplim, r3                           \n"
+            #endif
+            "    msr control, r4                              \n"
+            "    mov lr, r5                                   \n"
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy half of the the hardware saved context on the task stack. */
+            "    ldmia r1!, {r4-r7}                           \n" /* r4-r7 contain rest half of the hardware saved context. */
+            "    stmia r2!, {r4-r7}                           \n" /* Copy rest half of the the hardware saved context on the task stack. */
+            "    subs r1, #48                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r8-r11. */
+            "    mov r8, r4                                   \n" /* r8 = r4. */
+            "    mov r9, r5                                   \n" /* r9 = r5. */
+            "    mov r10, r6                                  \n" /* r10 = r6. */
+            "    mov r11, r7                                  \n" /* r11 = r7. */
+            "    subs r1, #32                                 \n"
+            "    ldmia r1!, {r4-r7}                           \n" /* Restore r4-r7. */
+            "    subs r1, #16                                 \n"
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   mrs r0, psp                                     \n"/* Read PSP in r0. */
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   subs r0, r0, #40                                \n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */
-        "   str r0, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r2, psplim                                  \n"/* r2 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r0!, {r2-r7}                              \n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
-        "   mov r4, r8                                      \n"/* r4 = r8. */
-        "   mov r5, r9                                      \n"/* r5 = r9. */
-        "   mov r6, r10                                     \n"/* r6 = r10. */
-        "   mov r7, r11                                     \n"/* r7 = r11. */
-        "   stmia r0!, {r4-r7}                              \n"/* Store the high registers that are not saved automatically. */
-        "                                                   \n"
-        "   cpsid i                                         \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   cpsie i                                         \n"
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r0, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-        "                                                   \n"
-        "   adds r0, r0, #24                                \n"/* Move to the high registers. */
-        "   ldmia r0!, {r4-r7}                              \n"/* Restore the high registers that are not automatically restored. */
-        "   mov r8, r4                                      \n"/* r8 = r4. */
-        "   mov r9, r5                                      \n"/* r9 = r5. */
-        "   mov r10, r6                                     \n"/* r10 = r6. */
-        "   mov r11, r7                                     \n"/* r11 = r7. */
-        "   msr psp, r0                                     \n"/* Remember the new top of stack for the task. */
-        "   subs r0, r0, #40                                \n"/* Move to the starting of the saved context. */
-        "   ldmia r0!, {r2-r7}                              \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
-        "   msr psplim, r2                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   bx r3                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   mrs r0, psp                                     \n" /* Read PSP in r0. */
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   subs r0, r0, #40                                \n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
+            "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "   mrs r2, psplim                              \n" /* r2 = PSPLIM. */
+            #else
+                "   movs r2, #0                                 \n" /* r2 = 0. 0 is stored in the PSPLIM slot. */
+            #endif
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmia r0!, {r2-r7}                              \n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+            "   mov r4, r8                                      \n" /* r4 = r8. */
+            "   mov r5, r9                                      \n" /* r5 = r9. */
+            "   mov r6, r10                                     \n" /* r6 = r10. */
+            "   mov r7, r11                                     \n" /* r7 = r11. */
+            "   stmia r0!, {r4-r7}                              \n" /* Store the high registers that are not saved automatically. */
+            "                                                   \n"
+            "   cpsid i                                         \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   cpsie i                                         \n"
+            "                                                   \n"
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+            "                                                   \n"
+            "   adds r0, r0, #24                                \n" /* Move to the high registers. */
+            "   ldmia r0!, {r4-r7}                              \n" /* Restore the high registers that are not automatically restored. */
+            "   mov r8, r4                                      \n" /* r8 = r4. */
+            "   mov r9, r5                                      \n" /* r9 = r5. */
+            "   mov r10, r6                                     \n" /* r10 = r6. */
+            "   mov r11, r7                                     \n" /* r11 = r7. */
+            "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
+            "   subs r0, r0, #40                                \n" /* Move to the starting of the saved context. */
+            "   ldmia r0!, {r2-r7}                              \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+            #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+                "   msr psplim, r2                              \n" /* Restore the PSPLIM register value for the task. */
+            #endif
+            "   bx r3                                           \n"
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "movs r0, #4                    \n"
-        "mov r1, lr                     \n"
-        "tst r0, r1                     \n"
-        "beq stack_on_msp               \n"
-        "stack_on_psp:                  \n"
-        "    mrs r0, psp                \n"
-        "    b route_svc                \n"
-        "stack_on_msp:                  \n"
-        "    mrs r0, msp                \n"
-        "    b route_svc                \n"
-        "                               \n"
-        "route_svc:                     \n"
-        "    ldr r2, [r0, #24]          \n"
-        "    subs r2, #2                \n"
-        "    ldrb r3, [r2, #0]          \n"
-        "    cmp r3, %0                 \n"
-        "    beq system_call_enter      \n"
-        "    cmp r3, %1                 \n"
-        "    beq system_call_enter_1    \n"
-        "    cmp r3, %2                 \n"
-        "    beq system_call_exit       \n"
-        "    b vPortSVCHandler_C        \n"
-        "                               \n"
-        "system_call_enter:             \n"
-        "    b vSystemCallEnter         \n"
-        "system_call_enter_1:           \n"
-        "    b vSystemCallEnter_1       \n"
-        "system_call_exit:              \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "r3", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "movs r0, #4                    \n"
+            "mov r1, lr                     \n"
+            "tst r0, r1                     \n"
+            "beq stack_on_msp               \n"
+            "stack_on_psp:                  \n"
+            "    mrs r0, psp                \n"
+            "    b route_svc                \n"
+            "stack_on_msp:                  \n"
+            "    mrs r0, msp                \n"
+            "    b route_svc                \n"
+            "                               \n"
+            "route_svc:                     \n"
+            "    ldr r3, [r0, #24]          \n"
+            "    subs r3, #2                \n"
+            "    ldrb r2, [r3, #0]          \n"
+            "    cmp r2, %0                 \n"
+            "    blt system_call_enter      \n"
+            "    cmp r2, %1                 \n"
+            "    beq system_call_exit       \n"
+            "    b vPortSVCHandler_C        \n"
+            "                               \n"
+            "system_call_enter:             \n"
+            "    b vSystemCallEnter         \n"
+            "system_call_exit:              \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "r3", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   movs r0, #4                                     \n"
-        "   mov r1, lr                                      \n"
-        "   tst r0, r1                                      \n"
-        "   beq stacking_used_msp                           \n"
-        "   mrs r0, psp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        " stacking_used_msp:                                \n"
-        "   mrs r0, msp                                     \n"
-        "   ldr r2, svchandler_address_const                \n"
-        "   bx r2                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   movs r0, #4                                     \n"
+            "   mov r1, lr                                      \n"
+            "   tst r0, r1                                      \n"
+            "   beq stacking_used_msp                           \n"
+            "   mrs r0, psp                                     \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
+            "   bx r2                                           \n"
+            " stacking_used_msp:                                \n"
+            "   mrs r0, msp                                     \n"
+            "   ldr r2, =vPortSVCHandler_C                      \n"
+            "   bx r2                                           \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/

portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -48,9 +48,10 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -60,6 +61,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif ( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**

portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c

@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -36,122 +38,132 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
         #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
         #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Enable MPU. */
-        "    dsb                                          \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r3, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst2                 \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xSecureContextConst2: .word xSecureContext      \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+            "                                                 \n"
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    orr r2, #1                                   \n" /* r2 = r1 | 1 i.e. Set the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Enable MPU. */
+            "    dsb                                          \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
-        "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-        "   ldr  r4, xSecureContextConst2                   \n"
-        "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
-        "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n" /* r1 = 2. */
-        "   msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n" /* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-        "xSecureContextConst2: .word xSecureContext         \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r3, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r3]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r3}                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "   ldr  r4, =xSecureContext                        \n"
+            "   str  r1, [r4]                                   \n" /* Set xSecureContext to this task's value for the same. */
+            "   msr  psplim, r2                                 \n" /* Set this task's PSPLIM value. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r3                                         \n" /* Finally, branch to EXC_RETURN. */
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -162,14 +174,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         ::: "r0", "memory"
     );
 }
@@ -181,10 +191,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr control, r0                                 \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr control, r0                                 \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -196,10 +206,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -211,19 +221,16 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -235,12 +242,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -252,10 +259,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -263,320 +270,322 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        " .extern SecureContext_SaveContext               \n"
-        " .extern SecureContext_LoadContext               \n"
-        "                                                 \n"
-        " ldr r3, xSecureContextConst                     \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        " ldr r3, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
-        "                                                 \n"
-        " cbz r0, save_ns_context                         \n" /* No secure context to save. */
-        " save_s_context:                                 \n"
-        "    push {r0-r2, lr}                             \n"
-        "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r0-r2, lr}                              \n"
-        "                                                 \n"
-        " save_ns_context:                                \n"
-        "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
-        "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-        "    mrs r3, psp                                  \n"
-        "                                                 \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psp                                  \n" /* r3 = PSP. */
-        "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
-        "    mrs r5, control                              \n" /* r5 = CONTROL. */
-        "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r2, [r1]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " ldr r2, [r1]                                    \n" /* r2 = Location in TCB where the context should be saved. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+            "    mrs r3, psp                                  \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r3, r3, #0x20                            \n" /* Move r3 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r2!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r3, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r3, r3, #0x20                            \n" /* Set r3 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "    stmia r2!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r3, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r2!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psp                                  \n" /* r3 = PSP. */
+            "    mrs r4, psplim                               \n" /* r4 = PSPLIM. */
+            "    mrs r5, control                              \n" /* r5 = CONTROL. */
+            "    stmia r2!, {r0, r3-r5, lr}                   \n" /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r3, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r4, PAC_KEY_P_1                          \n"
+            "   mrs  r5, PAC_KEY_P_2                          \n"
+            "   mrs  r6, PAC_KEY_P_3                          \n"
+            "   stmia r2!, {r3-r6}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    str r2, [r1]                                 \n"      /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r3]                                 \n" /* r0 = pxCurrentTCB.*/
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
         #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
         #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r3, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
-        "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
-        "    msr psp, r3                                  \n"
-        "    msr psplim, r4                               \n"
-        "    msr control, r5                              \n"
-        "    ldr r4, xSecureContextConst                  \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
-        "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
-        "                                                 \n"
-        " restore_s_context:                              \n"
-        "    push {r1-r3, lr}                             \n"
-        "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "    pop {r1-r3, lr}                              \n"
-        "                                                 \n"
-        " restore_ns_context:                             \n"
-        "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
-        "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xSecureContextConst: .word xSecureContext       \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+            "                                                 \n"
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* r1 = pxCurrentTCB.*/
+            "    ldr r2, [r1]                                 \n" /* r2 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r2!, {r3-r6}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r3                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r4                          \n"
+            "   msr  PAC_KEY_P_2, r5                          \n"
+            "   msr  PAC_KEY_P_3, r6                          \n"
+            "   clrm {r3-r6}                                  \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    ldmdb r2!, {r0, r3-r5, lr}                   \n" /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
+            "    msr psp, r3                                  \n"
+            "    msr psplim, r4                               \n"
+            "    msr control, r5                              \n"
+            "    ldr r4, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r4]                                 \n" /* Restore xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* No secure context to restore. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r3!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r2!, {r4-r11}                          \n" /* r4-r11 restored. */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r2!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r3!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r2!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r2, [r1]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "   .extern SecureContext_SaveContext               \n"
-        "   .extern SecureContext_LoadContext               \n"
-        "                                                   \n"
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   ldr r0, [r3]                                    \n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
-        "   mrs r2, psp                                     \n"/* Read PSP in r2. */
-        "                                                   \n"
-        "   cbz r0, save_ns_context                         \n"/* No secure context to save. */
-        "   push {r0-r2, r14}                               \n"
-        "   bl SecureContext_SaveContext                    \n"/* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r0-r3}                                     \n"/* LR is now in r3. */
-        "   mov lr, r3                                      \n"/* LR = r3. */
-        "   lsls r1, r3, #25                                \n"/* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl save_ns_context                             \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB.*/
-        "   subs r2, r2, #12                                \n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "   b select_next_task                              \n"
-        "                                                   \n"
-        " save_ns_context:                                  \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            " .extern SecureContext_SaveContext               \n"
+            " .extern SecureContext_LoadContext               \n"
+            "                                                 \n"
+            " ldr r3, =xSecureContext                         \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            " ldr r0, [r3]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+            " ldr r3, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r1, [r3]                                    \n" /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
+            " mrs r2, psp                                     \n" /* Read PSP in r2. */
+            "                                                 \n"
+            " cbz r0, save_ns_context                         \n" /* No secure context to save. */
+            " save_s_context:                                 \n"
+            "    push {r0-r2, lr}                             \n"
+            "    bl SecureContext_SaveContext                 \n" /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r0-r2, lr}                              \n"
+            "                                                 \n"
+            " save_ns_context:                                \n"
+            "    mov r3, lr                                   \n" /* r3 = LR (EXC_RETURN). */
+            "    lsls r3, r3, #25                             \n" /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi save_special_regs                        \n" /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
         #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vstmdbeq r2!, {s16-s31}                     \n"/* Store the additional FP context registers which are not saved automatically. */
+            "    tst lr, #0x10                                \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "    it eq                                        \n"
+            "    vstmdbeq r2!, {s16-s31}                      \n" /* Store the additional FP context registers which are not saved automatically. */
         #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   subs r2, r2, #44                                \n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        "   str r2, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "   adds r2, r2, #12                                \n"/* r2 = r2 + 12. */
-        "   stm r2, {r4-r11}                                \n"/* Store the registers that are not saved automatically. */
-        "   mrs r1, psplim                                  \n"/* r1 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   subs r2, r2, #12                                \n"/* r2 = r2 - 12. */
-        "   stmia r2!, {r0, r1, r3}                         \n"/* Store xSecureContext, PSPLIM and LR on the stack. */
-        "                                                   \n"
-        " select_next_task:                                 \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r2, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r2!, {r0, r1, r4}                         \n"/* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        "   msr psplim, r1                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   ldr r3, xSecureContextConst                     \n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-        "   str r0, [r3]                                    \n"/* Restore the task's xSecureContext. */
-        "   cbz r0, restore_ns_context                      \n"/* If there is no secure context for the task, restore the non-secure context. */
-        "   ldr r3, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r3]                                    \n"/* Read pxCurrentTCB. */
-        "   push {r2, r4}                                   \n"
-        "   bl SecureContext_LoadContext                    \n"/* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        "   pop {r2, r4}                                    \n"
-        "   mov lr, r4                                      \n"/* LR = r4. */
-        "   lsls r1, r4, #25                                \n"/* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        "   bpl restore_ns_context                          \n"/* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        " restore_ns_context:                               \n"
-        "   ldmia r2!, {r4-r11}                             \n"/* Restore the registers that are not automatically restored. */
+            "   stmdb r2!, {r4-r11}                           \n" /* Store the registers that are not saved automatically. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    stmdb r2!, {r0, r3, lr}                      \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+        #if ( configENABLE_PAC == 1 )
+            "    mrs  r3, PAC_KEY_P_3                         \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "    mrs  r4, PAC_KEY_P_2                         \n"
+            "    mrs  r5, PAC_KEY_P_1                         \n"
+            "    mrs  r6, PAC_KEY_P_0                         \n"
+            "    stmdb r2!, {r3-r6}                           \n" /* Store the task's dedicated PAC key on the stack. */
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "                                                 \n"
+            " str r2, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r3, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r1, [r3]                                 \n" /* Read pxCurrentTCB. */
+            "    ldr r2, [r1]                                 \n" /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "    ldmia r2!, {r3-r6}                           \n" /* Read task's dedicated PAC key from stack. */
+            "    msr  PAC_KEY_P_3, r3                         \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "    msr  PAC_KEY_P_2, r4                         \n"
+            "    msr  PAC_KEY_P_1, r5                         \n"
+            "    msr  PAC_KEY_P_0, r6                         \n"
+            "    clrm {r3-r6}                                 \n" /* Clear r3-r6. */
+        #endif /* configENABLE_PAC */
+            "    ldmia r2!, {r0, r3, lr}                      \n" /* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+            "    msr psplim, r3                               \n" /* Restore the PSPLIM register value for the task. */
+            "    ldr r3, =xSecureContext                      \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "    str r0, [r3]                                 \n" /* Restore the task's xSecureContext. */
+            "    cbz r0, restore_ns_context                   \n" /* If there is no secure context for the task, restore the non-secure context. */
+            "                                                 \n"
+            " restore_s_context:                              \n"
+            "    push {r1-r3, lr}                             \n"
+            "    bl SecureContext_LoadContext                 \n" /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+            "    pop {r1-r3, lr}                              \n"
+            "                                                 \n"
+            " restore_ns_context:                             \n"
+            "    mov r0, lr                                   \n" /* r0 = LR (EXC_RETURN). */
+            "    lsls r0, r0, #25                             \n" /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "    bmi restore_context_done                     \n" /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmia r2!, {r4-r11}                          \n" /* Restore the registers that are not automatically restored. */
         #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                               \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
-            "   it eq                                       \n"
-            "   vldmiaeq r2!, {s16-s31}                     \n"/* Restore the additional FP context registers which are not restored automatically. */
+            "   tst lr, #0x10                                 \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   it eq                                         \n"
+            "   vldmiaeq r2!, {s16-s31}                       \n" /* Restore the additional FP context registers which are not restored automatically. */
         #endif /* configENABLE_FPU || configENABLE_MVE */
-        "   msr psp, r2                                     \n"/* Remember the new top of stack for the task. */
-        "   bx lr                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        "xSecureContextConst: .word xSecureContext          \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    msr psp, r2                                  \n" /* Remember the new top of stack for the task. */
+            "    bx lr                                        \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "blt syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
+            "   bx r1                                           \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/
@@ -587,8 +596,8 @@ void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   svc %0                                          \n"/* Secure context is allocated in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svc %0                                          \n" /* Secure context is allocated in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
     );
 }
@@ -600,12 +609,12 @@ void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PR
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r2, [r0]                                    \n"/* The first item in the TCB is the top of the stack. */
-        "   ldr r1, [r2]                                    \n"/* The first item on the stack is the task's xSecureContext. */
-        "   cmp r1, #0                                      \n"/* Raise svc if task's xSecureContext is not NULL. */
+        "   ldr r2, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
+        "   ldr r1, [r2]                                    \n" /* The first item on the stack is the task's xSecureContext. */
+        "   cmp r1, #0                                      \n" /* Raise svc if task's xSecureContext is not NULL. */
         "   it ne                                           \n"
-        "   svcne %0                                        \n"/* Secure context is freed in the supervisor call. */
-        "   bx lr                                           \n"/* Return. */
+        "   svcne %0                                        \n" /* Secure context is freed in the supervisor call. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
     );
 }

portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -48,20 +48,28 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif ( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */

portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c

@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -36,117 +38,128 @@
 /* Portasm includes. */
 #include "portasm.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
  * header files. */
 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
 
 #if ( configENABLE_MPU == 1 )
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " program_mpu_first_task:                         \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst2                       \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const2                         \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst2                           \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst2                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst2                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context_first_task:                     \n"
-        "    ldr r2, pxCurrentTCBConst2                   \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs_first_task:                \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs_first_task:                \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-        "                                                 \n"
-        " restore_context_done_first_task:                \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    mov r0, #0                                   \n"
-        "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst2: .word pxCurrentTCB          \n"
-        " xMPUCTRLConst2: .word 0xe000ed94                \n"
-        " xMAIR0Const2: .word 0xe000edc0                  \n"
-        " xRNRConst2: .word 0xe000ed98                    \n"
-        " xRBARConst2: .word 0xe000ed9c                   \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " program_mpu_first_task:                         \n"
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context_first_task:                     \n"
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs_first_task:                \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs_first_task:                \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+            "                                                 \n"
+            " restore_context_done_first_task:                \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    mov r0, #0                                   \n"
+            "    msr basepri, r0                              \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "    bx lr                                        \n"
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   ldr  r2, pxCurrentTCBConst2                     \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr  r1, [r2]                                   \n"/* Read pxCurrentTCB. */
-        "   ldr  r0, [r1]                                   \n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-        "                                                   \n"
-        "   ldm  r0!, {r1-r2}                               \n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-        "   msr  psplim, r1                                 \n"/* Set this task's PSPLIM value. */
-        "   movs r1, #2                                     \n"/* r1 = 2. */
-        "   msr  CONTROL, r1                                \n"/* Switch to use PSP in the thread mode. */
-        "   adds r0, #32                                    \n"/* Discard everything up to r0. */
-        "   msr  psp, r0                                    \n"/* This is now the new top of stack to use in the task. */
-        "   isb                                             \n"
-        "   mov  r0, #0                                     \n"
-        "   msr  basepri, r0                                \n"/* Ensure that interrupts are enabled when the first task starts. */
-        "   bx   r2                                         \n"/* Finally, branch to EXC_RETURN. */
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst2: .word pxCurrentTCB             \n"
-    );
-}
+    void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   ldr  r2, =pxCurrentTCB                          \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr  r1, [r2]                                   \n" /* Read pxCurrentTCB. */
+            "   ldr  r0, [r1]                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+            "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r1-r4}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r1                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r2                            \n"
+            "   msr  PAC_KEY_P_1, r3                            \n"
+            "   msr  PAC_KEY_P_0, r4                            \n"
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
+            "   ldm  r0!, {r1-r2}                               \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "   msr  psplim, r1                                 \n" /* Set this task's PSPLIM value. */
+            "   mrs  r1, control                                \n" /* Obtain current control register value. */
+            "   orrs r1, r1, #2                                 \n" /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointer (PSP). */
+            "   msr control, r1                                 \n" /* Write back the new control register value. */
+            "   adds r0, #32                                    \n" /* Discard everything up to r0. */
+            "   msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+            "   isb                                             \n"
+            "   mov  r0, #0                                     \n"
+            "   msr  basepri, r0                                \n" /* Ensure that interrupts are enabled when the first task starts. */
+            "   bx   r2                                         \n" /* Finally, branch to EXC_RETURN. */
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
@@ -157,14 +170,12 @@ BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   tst r0, #1                                      \n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   tst r0, #1                                      \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
         "   ite ne                                          \n"
-        "   movne r0, #0                                    \n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-        "   moveq r0, #1                                    \n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-        "   bx lr                                           \n"/* Return. */
-        "                                                   \n"
-        "   .align 4                                        \n"
+        "   movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "   moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "   bx lr                                           \n" /* Return. */
         ::: "r0", "memory"
     );
 }
@@ -176,10 +187,10 @@ void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs  r0, control                                \n"/* Read the CONTROL register. */
-        "   bic r0, #1                                      \n"/* Clear the bit 0. */
-        "   msr  control, r0                                \n"/* Write back the new CONTROL value. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs  r0, control                                \n" /* Read the CONTROL register. */
+        "   bic r0, #1                                      \n" /* Clear the bit 0. */
+        "   msr  control, r0                                \n" /* Write back the new CONTROL value. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -191,10 +202,10 @@ void vResetPrivilege( void ) /* __attribute__ (( naked )) */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, control                                 \n"/* r0 = CONTROL. */
-        "   orr r0, #1                                      \n"/* r0 = r0 | 1. */
-        "   msr control, r0                                 \n"/* CONTROL = r0. */
-        "   bx lr                                           \n"/* Return to the caller. */
+        "   mrs r0, control                                 \n" /* r0 = CONTROL. */
+        "   orr r0, #1                                      \n" /* r0 = r0 | 1. */
+        "   msr control, r0                                 \n" /* CONTROL = r0. */
+        "   bx lr                                           \n" /* Return to the caller. */
         ::: "r0", "memory"
     );
 }
@@ -206,19 +217,16 @@ void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   ldr r0, xVTORConst                              \n"/* Use the NVIC offset register to locate the stack. */
-        "   ldr r0, [r0]                                    \n"/* Read the VTOR register which gives the address of vector table. */
-        "   ldr r0, [r0]                                    \n"/* The first entry in vector table is stack pointer. */
-        "   msr msp, r0                                     \n"/* Set the MSP back to the start of the stack. */
-        "   cpsie i                                         \n"/* Globally enable interrupts. */
+        "   ldr r0, =0xe000ed08                             \n" /* Use the NVIC offset register to locate the stack. */
+        "   ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+        "   ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+        "   msr msp, r0                                     \n" /* Set the MSP back to the start of the stack. */
+        "   cpsie i                                         \n" /* Globally enable interrupts. */
         "   cpsie f                                         \n"
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   svc %0                                          \n"/* System call to start the first task. */
+        "   svc %0                                          \n" /* System call to start the first task. */
         "   nop                                             \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "xVTORConst: .word 0xe000ed08                       \n"
         ::"i" ( portSVC_START_SCHEDULER ) : "memory"
     );
 }
@@ -230,12 +238,12 @@ uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCT
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   mrs r0, basepri                                 \n"/* r0 = basepri. Return original basepri value. */
-        "   mov r1, %0                                      \n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   msr basepri, r1                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   mrs r0, basepri                                 \n" /* r0 = basepri. Return original basepri value. */
+        "   mov r1, %0                                      \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "   msr basepri, r1                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
     );
 }
@@ -247,10 +255,10 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
     (
         "   .syntax unified                                 \n"
         "                                                   \n"
-        "   msr basepri, r0                                 \n"/* basepri = ulMask. */
+        "   msr basepri, r0                                 \n" /* basepri = ulMask. */
         "   dsb                                             \n"
         "   isb                                             \n"
-        "   bx lr                                           \n"/* Return. */
+        "   bx lr                                           \n" /* Return. */
         ::: "memory"
     );
 }
@@ -258,246 +266,259 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
 
 #if ( configENABLE_MPU == 1 )
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        " .syntax unified                                 \n"
-        "                                                 \n"
-        " ldr r2, pxCurrentTCBConst                       \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
-        " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
-        " mrs r2, psp                                     \n" /* r2 = PSP. */
-        "                                                 \n"
-        " save_general_regs:                              \n"
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
-        "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
-        "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
-        "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
-        "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
-        "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
-        "                                                 \n"
-        " save_special_regs:                              \n"
-        "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
-        "    mrs r4, control                              \n" /* r4 = CONTROL. */
-        "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
-        "                                                 \n"
-        " select_next_task:                               \n"
-        "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "    msr basepri, r0                              \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "    dsb                                          \n"
-        "    isb                                          \n"
-        "    bl vTaskSwitchContext                        \n"
-        "    mov r0, #0                                   \n" /* r0 = 0. */
-        "    msr basepri, r0                              \n" /* Enable interrupts. */
-        "                                                 \n"
-        " program_mpu:                                    \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
-        "                                                 \n"
-        "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
-        "    ldr r1, xMPUCTRLConst                        \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
-        "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
-        "    str r2, [r1]                                 \n" /* Disable MPU. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
-        "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
-        "    ldr r2, xMAIR0Const                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-        "    str r1, [r2]                                 \n" /* Program MAIR0. */
-        "                                                 \n"
-        "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
-        "    ldr r1, xRNRConst                            \n" /* r1 = 0xe000ed98 [Location of RNR]. */
-        "    ldr r2, xRBARConst                           \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-        "                                                 \n"
-        "    movs r3, #4                                  \n" /* r3 = 4. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 4. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "                                                 \n"
-    #if ( configTOTAL_MPU_REGIONS == 16 )
-        "    movs r3, #8                                  \n" /* r3 = 8. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 8. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-        "    movs r3, #12                                 \n" /* r3 = 12. */
-        "    str r3, [r1]                                 \n" /* Program RNR = 12. */
-        "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-        "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-    #endif /* configTOTAL_MPU_REGIONS == 16 */
-        "                                                 \n"
-        "   ldr r1, xMPUCTRLConst                         \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
-        "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
-        "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
-        "   str r2, [r1]                                  \n" /* Enable MPU. */
-        "   dsb                                           \n" /* Force memory writes before continuing. */
-        "                                                 \n"
-        " restore_context:                                \n"
-        "    ldr r2, pxCurrentTCBConst                    \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
-        "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
-        "                                                 \n"
-        " restore_special_regs:                           \n"
-        "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
-        "    msr psp, r2                                  \n"
-        "    msr psplim, r3                               \n"
-        "    msr control, r4                              \n"
-        "                                                 \n"
-        " restore_general_regs:                           \n"
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
-        "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
-        "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
-    #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-        "    tst lr, #0x10                                \n"
-        "    ittt eq                                      \n"
-        "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
-        "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
-        "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
-    #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                 \n"
-        " restore_context_done:                           \n"
-        "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
-        "    bx lr                                        \n"
-        "                                                 \n"
-        " .align 4                                        \n"
-        " pxCurrentTCBConst: .word pxCurrentTCB           \n"
-        " xMPUCTRLConst: .word 0xe000ed94                 \n"
-        " xMAIR0Const: .word 0xe000edc0                   \n"
-        " xRNRConst: .word 0xe000ed98                     \n"
-        " xRBARConst: .word 0xe000ed9c                    \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            " .syntax unified                                 \n"
+            "                                                 \n"
+            " ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            " ldr r0, [r2]                                    \n" /* r0 = pxCurrentTCB. */
+            " ldr r1, [r0]                                    \n" /* r1 = Location in TCB where the context should be saved. */
+            " mrs r2, psp                                     \n" /* r2 = PSP. */
+            "                                                 \n"
+            " save_general_regs:                              \n"
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    add r2, r2, #0x20                            \n" /* Move r2 to location where s0 is saved. */
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vstmiaeq r1!, {s16-s31}                      \n" /* Store s16-s31. */
+            "    vldmiaeq r2, {s0-s16}                        \n" /* Copy hardware saved FP context into s0-s16. */
+            "    vstmiaeq r1!, {s0-s16}                       \n" /* Store hardware saved FP context. */
+            "    sub r2, r2, #0x20                            \n" /* Set r2 back to the location of hardware saved context. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "    stmia r1!, {r4-r11}                          \n" /* Store r4-r11. */
+            "    ldmia r2, {r4-r11}                           \n" /* Copy the hardware saved context into r4-r11. */
+            "    stmia r1!, {r4-r11}                          \n" /* Store the hardware saved context. */
+            "                                                 \n"
+            " save_special_regs:                              \n"
+            "    mrs r3, psplim                               \n" /* r3 = PSPLIM. */
+            "    mrs r4, control                              \n" /* r4 = CONTROL. */
+            "    stmia r1!, {r2-r4, lr}                       \n" /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r2, PAC_KEY_P_0                          \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r3, PAC_KEY_P_1                          \n"
+            "   mrs  r4, PAC_KEY_P_2                          \n"
+            "   mrs  r5, PAC_KEY_P_3                          \n"
+            "   stmia r1!, {r2-r5}                            \n" /* Store the task's dedicated PAC key on the task's context. */
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
+            "    str r1, [r0]                                 \n" /* Save the location from where the context should be restored as the first member of TCB. */
+            "                                                 \n"
+            " select_next_task:                               \n"
+            "    mov r0, %0                                   \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "    msr basepri, r0                              \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "    dsb                                          \n"
+            "    isb                                          \n"
+            "    bl vTaskSwitchContext                        \n"
+            "    mov r0, #0                                   \n" /* r0 = 0. */
+            "    msr basepri, r0                              \n" /* Enable interrupts. */
+            "                                                 \n"
+            " program_mpu:                                    \n"
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB. */
+            "                                                 \n"
+            "    dmb                                          \n" /* Complete outstanding transfers before disabling MPU. */
+            "    ldr r1, =0xe000ed94                          \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "    ldr r2, [r1]                                 \n" /* Read the value of MPU_CTRL. */
+            "    bic r2, #1                                   \n" /* r2 = r2 & ~1 i.e. Clear the bit 0 in r2. */
+            "    str r2, [r1]                                 \n" /* Disable MPU. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to MAIR0 in TCB. */
+            "    ldr r1, [r0]                                 \n" /* r1 = *r0 i.e. r1 = MAIR0. */
+            "    ldr r2, =0xe000edc0                          \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "    str r1, [r2]                                 \n" /* Program MAIR0. */
+            "                                                 \n"
+            "    adds r0, #4                                  \n" /* r0 = r0 + 4. r0 now points to first RBAR in TCB. */
+            "    ldr r1, =0xe000ed98                          \n" /* r1 = 0xe000ed98 [Location of RNR]. */
+            "    ldr r2, =0xe000ed9c                          \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+            "                                                 \n"
+            "    movs r3, #4                                  \n" /* r3 = 4. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 4. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "                                                 \n"
+        #if ( configTOTAL_MPU_REGIONS == 16 )
+            "    movs r3, #8                                  \n" /* r3 = 8. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 8. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "    movs r3, #12                                 \n" /* r3 = 12. */
+            "    str r3, [r1]                                 \n" /* Program RNR = 12. */
+            "    ldmia r0!, {r4-r11}                          \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "    stmia r2, {r4-r11}                           \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+        #endif /* configTOTAL_MPU_REGIONS == 16 */
+            "                                                 \n"
+            "   ldr r1, =0xe000ed94                           \n" /* r1 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "   ldr r2, [r1]                                  \n" /* Read the value of MPU_CTRL. */
+            "   orr r2, #1                                    \n" /* r2 = r2 | 1 i.e. Set the bit 0 in r2. */
+            "   str r2, [r1]                                  \n" /* Enable MPU. */
+            "   dsb                                           \n" /* Force memory writes before continuing. */
+            "                                                 \n"
+            " restore_context:                                \n"
+            "    ldr r2, =pxCurrentTCB                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "    ldr r0, [r2]                                 \n" /* r0 = pxCurrentTCB.*/
+            "    ldr r1, [r0]                                 \n" /* r1 = Location of saved context in TCB. */
+            "                                                 \n"
+            " restore_special_regs:                           \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmdb r1!, {r2-r5}                            \n" /* Read task's dedicated PAC key from the task's context. */
+            "   msr  PAC_KEY_P_0, r2                          \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_1, r3                          \n"
+            "   msr  PAC_KEY_P_2, r4                          \n"
+            "   msr  PAC_KEY_P_3, r5                          \n"
+            "   clrm {r2-r5}                                  \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
+            "    ldmdb r1!, {r2-r4, lr}                       \n" /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
+            "    msr psp, r2                                  \n"
+            "    msr psplim, r3                               \n"
+            "    msr control, r4                              \n"
+            "                                                 \n"
+            " restore_general_regs:                           \n"
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 contain hardware saved context. */
+            "    stmia r2!, {r4-r11}                          \n" /* Copy the hardware saved context on the task stack. */
+            "    ldmdb r1!, {r4-r11}                          \n" /* r4-r11 restored. */
+        #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
+            "    tst lr, #0x10                                \n"
+            "    ittt eq                                      \n"
+            "    vldmdbeq r1!, {s0-s16}                       \n" /* s0-s16 contain hardware saved FP context. */
+            "    vstmiaeq r2!, {s0-s16}                       \n" /* Copy hardware saved FP context on the task stack. */
+            "    vldmdbeq r1!, {s16-s31}                      \n" /* Restore s16-s31. */
+        #endif /* configENABLE_FPU || configENABLE_MVE */
+            "                                                 \n"
+            " restore_context_done:                           \n"
+            "    str r1, [r0]                                 \n" /* Save the location where the context should be saved next as the first member of TCB. */
+            "    bx lr                                        \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #else /* configENABLE_MPU */
 
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   mrs r0, psp                                     \n"/* Read PSP in r0. */
-        "                                                   \n"
+    void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   mrs r0, psp                                     \n" /* Read PSP in r0. */
+            "                                                   \n"
         #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst lr, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   tst lr, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
             "   it eq                                           \n"
-            "   vstmdbeq r0!, {s16-s31}                         \n"/* Store the additional FP context registers which are not saved automatically. */
+            "   vstmdbeq r0!, {s16-s31}                         \n" /* Store the additional FP context registers which are not saved automatically. */
         #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   mrs r2, psplim                                  \n"/* r2 = PSPLIM. */
-        "   mov r3, lr                                      \n"/* r3 = LR/EXC_RETURN. */
-        "   stmdb r0!, {r2-r11}                             \n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   str r0, [r1]                                    \n"/* Save the new top of stack in TCB. */
-        "                                                   \n"
-        "   mov r0, %0                                      \n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
-        "   msr basepri, r0                                 \n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-        "   dsb                                             \n"
-        "   isb                                             \n"
-        "   bl vTaskSwitchContext                           \n"
-        "   mov r0, #0                                      \n"/* r0 = 0. */
-        "   msr basepri, r0                                 \n"/* Enable interrupts. */
-        "                                                   \n"
-        "   ldr r2, pxCurrentTCBConst                       \n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        "   ldr r1, [r2]                                    \n"/* Read pxCurrentTCB. */
-        "   ldr r0, [r1]                                    \n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-        "                                                   \n"
-        "   ldmia r0!, {r2-r11}                             \n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-        "                                                   \n"
+            "                                                   \n"
+            "   mrs r2, psplim                                  \n" /* r2 = PSPLIM. */
+            "   mov r3, lr                                      \n" /* r3 = LR/EXC_RETURN. */
+            "   stmdb r0!, {r2-r11}                             \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+            "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   mrs  r1, PAC_KEY_P_3                            \n" /* Read task's dedicated PAC key from the PAC key registers. */
+            "   mrs  r2, PAC_KEY_P_2                            \n"
+            "   mrs  r3, PAC_KEY_P_1                            \n"
+            "   mrs  r4, PAC_KEY_P_0                            \n"
+            "   stmdb r0!, {r1-r4}                              \n" /* Store the task's dedicated PAC key on the stack. */
+            "   clrm {r1-r4}                                    \n" /* Clear r1-r4. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+            "                                                   \n"
+            "   mov r0, %0                                      \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+            "   msr basepri, r0                                 \n" /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+            "   dsb                                             \n"
+            "   isb                                             \n"
+            "   bl vTaskSwitchContext                           \n"
+            "   mov r0, #0                                      \n" /* r0 = 0. */
+            "   msr basepri, r0                                 \n" /* Enable interrupts. */
+            "                                                   \n"
+            "   ldr r2, =pxCurrentTCB                           \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+            "   ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+            "   ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+            "                                                   \n"
+        #if ( configENABLE_PAC == 1 )
+            "   ldmia r0!, {r2-r5}                              \n" /* Read task's dedicated PAC key from stack. */
+            "   msr  PAC_KEY_P_3, r2                            \n" /* Write the task's dedicated PAC key to the PAC key registers. */
+            "   msr  PAC_KEY_P_2, r3                            \n"
+            "   msr  PAC_KEY_P_1, r4                            \n"
+            "   msr  PAC_KEY_P_0, r5                            \n"
+            "   clrm {r2-r5}                                    \n" /* Clear r2-r5. */
+        #endif /* configENABLE_PAC */
+            "                                                   \n"
+            "   ldmia r0!, {r2-r11}                             \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+            "                                                   \n"
         #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
-            "   tst r3, #0x10                                   \n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
+            "   tst r3, #0x10                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
             "   it eq                                           \n"
-            "   vldmiaeq r0!, {s16-s31}                         \n"/* Restore the additional FP context registers which are not restored automatically. */
+            "   vldmiaeq r0!, {s16-s31}                         \n" /* Restore the additional FP context registers which are not restored automatically. */
         #endif /* configENABLE_FPU || configENABLE_MVE */
-        "                                                   \n"
-        "   msr psplim, r2                                  \n"/* Restore the PSPLIM register value for the task. */
-        "   msr psp, r0                                     \n"/* Remember the new top of stack for the task. */
-        "   bx r3                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "pxCurrentTCBConst: .word pxCurrentTCB              \n"
-        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-    );
-}
+            "                                                   \n"
+            "   msr psplim, r2                                  \n" /* Restore the PSPLIM register value for the task. */
+            "   msr psp, r0                                     \n" /* Remember the new top of stack for the task. */
+            "   bx r3                                           \n"
+            ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+        );
+    }
 
 #endif /* configENABLE_MPU */
 /*-----------------------------------------------------------*/
 
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-   __asm volatile
-    (
-        ".syntax unified                \n"
-        ".extern vPortSVCHandler_C      \n"
-        ".extern vSystemCallEnter       \n"
-        ".extern vSystemCallEnter_1     \n"
-        ".extern vSystemCallExit        \n"
-        "                               \n"
-        "tst lr, #4                     \n"
-        "ite eq                         \n"
-        "mrseq r0, msp                  \n"
-        "mrsne r0, psp                  \n"
-        "                               \n"
-        "ldr r1, [r0, #24]              \n"
-        "ldrb r2, [r1, #-2]             \n"
-        "cmp r2, %0                     \n"
-        "beq syscall_enter              \n"
-        "cmp r2, %1                     \n"
-        "beq syscall_enter_1            \n"
-        "cmp r2, %2                     \n"
-        "beq syscall_exit               \n"
-        "b vPortSVCHandler_C            \n"
-        "                               \n"
-        "syscall_enter:                 \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter         \n"
-        "                               \n"
-        "syscall_enter_1:               \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallEnter_1       \n"
-        "                               \n"
-        "syscall_exit:                  \n"
-        "    mov r1, lr                 \n"
-        "    b vSystemCallExit          \n"
-        "                               \n"
-        : /* No outputs. */
-        :"i" ( portSVC_SYSTEM_CALL_ENTER ), "i" ( portSVC_SYSTEM_CALL_ENTER_1 ), "i" ( portSVC_SYSTEM_CALL_EXIT )
-        : "r0", "r1", "r2", "memory"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            ".syntax unified                \n"
+            ".extern vPortSVCHandler_C      \n"
+            ".extern vSystemCallEnter       \n"
+            ".extern vSystemCallExit        \n"
+            "                               \n"
+            "tst lr, #4                     \n"
+            "ite eq                         \n"
+            "mrseq r0, msp                  \n"
+            "mrsne r0, psp                  \n"
+            "                               \n"
+            "ldr r1, [r0, #24]              \n"
+            "ldrb r2, [r1, #-2]             \n"
+            "cmp r2, %0                     \n"
+            "blt syscall_enter              \n"
+            "cmp r2, %1                     \n"
+            "beq syscall_exit               \n"
+            "b vPortSVCHandler_C            \n"
+            "                               \n"
+            "syscall_enter:                 \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallEnter         \n"
+            "                               \n"
+            "syscall_exit:                  \n"
+            "    mov r1, lr                 \n"
+            "    b vSystemCallExit          \n"
+            "                               \n"
+            : /* No outputs. */
+            : "i" ( NUM_SYSTEM_CALLS ), "i" ( portSVC_SYSTEM_CALL_EXIT )
+            : "r0", "r1", "r2", "memory"
+        );
+    }
 
 #else /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-    __asm volatile
-    (
-        "   .syntax unified                                 \n"
-        "                                                   \n"
-        "   tst lr, #4                                      \n"
-        "   ite eq                                          \n"
-        "   mrseq r0, msp                                   \n"
-        "   mrsne r0, psp                                   \n"
-        "   ldr r1, svchandler_address_const                \n"
-        "   bx r1                                           \n"
-        "                                                   \n"
-        "   .align 4                                        \n"
-        "svchandler_address_const: .word vPortSVCHandler_C  \n"
-    );
-}
+    void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+    {
+        __asm volatile
+        (
+            "   .syntax unified                                 \n"
+            "                                                   \n"
+            "   tst lr, #4                                      \n"
+            "   ite eq                                          \n"
+            "   mrseq r0, msp                                   \n"
+            "   mrsne r0, psp                                   \n"
+            "   ldr r1, =vPortSVCHandler_C                      \n"
+            "   bx r1                                           \n"
+        );
+    }
 
 #endif /* ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) */
 /*-----------------------------------------------------------*/

portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -48,20 +48,28 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif ( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */

portable/ARMv8M/non_secure/portable/GCC/ARM_CM35P/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -48,20 +48,28 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_BASEPRI                     1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M35P"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif ( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */

portable/ARMv8M/non_secure/portable/GCC/ARM_CM55/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,9 +53,10 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M55"
-#define portHAS_BASEPRI                     1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -65,8 +66,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */

portable/ARMv8M/non_secure/portable/GCC/ARM_CM85/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,9 +53,10 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M85"
-#define portHAS_BASEPRI                     1
-#define portDONT_DISCARD                    __attribute__( ( used ) )
+#define portARCH_NAME                    "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
+#define portDONT_DISCARD                 __attribute__( ( used ) )
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -65,8 +66,8 @@
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* *INDENT-OFF* */

portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -33,10 +33,14 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
+
     EXTERN pxCurrentTCB
     EXTERN xSecureContext
     EXTERN vTaskSwitchContext
@@ -45,7 +49,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN SecureContext_LoadContext
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -95,7 +98,7 @@ vResetPrivilege:
 /*-----------------------------------------------------------*/
 
 vPortAllocateSecureContext:
-    svc 0                                   /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+    svc 100                                 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
@@ -167,7 +170,6 @@ vRestoreContextOfFirstTask:
         ldmia r2!, {r0, r3-r6}              /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
         subs r2, #20
         msr psp, r3
-        msr psplim, r4
         msr control, r5
         mov lr, r6
         ldr r4, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -203,7 +205,6 @@ vRestoreContextOfFirstTask:
     ldm  r0!, {r1-r3}                       /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
-    msr  psplim, r2                         /* Set this task's PSPLIM value. */
     movs r1, #2                             /* r1 = 2. */
     msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
     adds r0, #32                            /* Discard everything up to r0. */
@@ -230,7 +231,7 @@ vStartFirstTask:
     cpsie i                                 /* Globally enable interrupts. */
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
@@ -279,7 +280,7 @@ PendSV_Handler:
 
     save_special_regs:
         mrs r3, psp                         /* r3 = PSP. */
-        mrs r4, psplim                      /* r4 = PSPLIM. */
+        movs r4, #0                         /* r4 = 0. 0 is stored in the PSPLIM slot. */
         mrs r5, control                     /* r5 = CONTROL. */
         mov r6, lr                          /* r6 = LR. */
         stmia r2!, {r0, r3-r6}              /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -347,7 +348,6 @@ PendSV_Handler:
         ldmia r2!, {r0, r3-r6}              /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, r6 = LR. */
         subs r2, #20
         msr psp, r3
-        msr psplim, r4
         msr control, r5
         mov lr, r6
         ldr r4, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
@@ -406,7 +406,7 @@ PendSV_Handler:
 
     subs r2, r2, #12                        /* Make space for xSecureContext, PSPLIM and LR on the stack. */
     str r2, [r1]                            /* Save the new top of stack in TCB. */
-    mrs r1, psplim                          /* r1 = PSPLIM. */
+    movs r1, #0                             /* r1 = 0. 0 is stored in the PSPLIM slot. */
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmia r2!, {r0, r1, r3}                 /* Store xSecureContext, PSPLIM and LR on the stack. */
 
@@ -417,7 +417,7 @@ PendSV_Handler:
         ldr r1, [r3]                        /* Read pxCurrentTCB. */
         subs r2, r2, #44                    /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
         str r2, [r1]                        /* Save the new top of stack in TCB. */
-        mrs r1, psplim                      /* r1 = PSPLIM. */
+        movs r1, #0                         /* r1 = 0. 0 is stored in the PSPLIM slot. */
         mov r3, lr                          /* r3 = LR/EXC_RETURN. */
         stmia r2!, {r0, r1, r3-r7}          /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
         mov r4, r8                          /* r4 = r8. */
@@ -436,7 +436,6 @@ PendSV_Handler:
         ldr r2, [r1]                        /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 
         ldmia r2!, {r0, r1, r4}             /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        msr psplim, r1                      /* Restore the PSPLIM register value for the task. */
         mov lr, r4                          /* LR = r4. */
         ldr r3, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
         str r0, [r3]                        /* Restore the task's xSecureContext. */
@@ -482,21 +481,17 @@ SVC_Handler:
         b route_svc
 
     route_svc:
-        ldr r2, [r0, #24]
-        subs r2, #2
-        ldrb r3, [r2, #0]
-        cmp r3, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-        beq system_call_enter
-        cmp r3, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-        beq system_call_enter_1
-        cmp r3, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+        ldr r3, [r0, #24]
+        subs r3, #2
+        ldrb r2, [r3, #0]
+        cmp r2, #NUM_SYSTEM_CALLS
+        blt system_call_enter
+        cmp r2, #104        /* portSVC_SYSTEM_CALL_EXIT. */
         beq system_call_exit
         b vPortSVCHandler_C
 
     system_call_enter:
         b vSystemCallEnter
-    system_call_enter_1:
-        b vSystemCallEnter_1
     system_call_exit:
         b vSystemCallExit
 
@@ -523,7 +518,7 @@ vPortFreeSecureContext:
     bne free_secure_context                 /* Branch if r1 != 0. */
     bx lr                                   /* There is no secure context (xSecureContext is NULL). */
     free_secure_context:
-        svc 1                               /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+        svc 101                             /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
         bx lr                               /* Return. */
 /*-----------------------------------------------------------*/
 

portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -48,9 +48,10 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __root
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -60,6 +61,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif ( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**

portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -32,16 +32,22 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
 
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+    #define configRUN_FREERTOS_SECURE_ONLY 0
+#endif
+
     EXTERN pxCurrentTCB
     EXTERN vTaskSwitchContext
     EXTERN vPortSVCHandler_C
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -157,7 +163,9 @@ vRestoreContextOfFirstTask:
         ldmia r1!, {r2-r5}                  /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
         subs r1, #16
         msr psp, r2
+    #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
         msr psplim, r3
+    #endif
         msr control, r4
         mov lr, r5
 
@@ -189,7 +197,9 @@ vRestoreContextOfFirstTask:
     ldr  r0, [r1]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
+#endif
     movs r1, #2                             /* r1 = 2. */
     msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
     adds r0, #32                            /* Discard everything up to r0. */
@@ -216,7 +226,7 @@ vStartFirstTask:
     cpsie i                                 /* Globally enable interrupts. */
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
     nop
 /*-----------------------------------------------------------*/
 
@@ -253,7 +263,11 @@ PendSV_Handler:
 
     save_special_regs:
         mrs r2, psp                         /* r2 = PSP. */
+    #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
         mrs r3, psplim                      /* r3 = PSPLIM. */
+    #else
+        movs r3, #0                         /* r3 = 0. 0 is stored in the PSPLIM slot. */
+    #endif
         mrs r4, control                     /* r4 = CONTROL. */
         mov r5, lr                          /* r5 = LR. */
         stmia r1!, {r2-r5}                  /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
@@ -321,7 +335,9 @@ PendSV_Handler:
         ldmia r1!, {r2-r5}                  /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, r5 = LR. */
         subs r1, #16
         msr psp, r2
+    #if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
         msr psplim, r3
+    #endif
         msr control, r4
         mov lr, r5
 
@@ -354,7 +370,11 @@ PendSV_Handler:
 
     subs r0, r0, #40                        /* Make space for PSPLIM, LR and the remaining registers on the stack. */
     str r0, [r1]                            /* Save the new top of stack in TCB. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
     mrs r2, psplim                          /* r2 = PSPLIM. */
+#else
+    movs r2, #0                             /* r0 = 0. 0 is stored in the PSPLIM slot. */
+#endif
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmia r0!, {r2-r7}                      /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
     mov r4, r8                              /* r4 = r8. */
@@ -380,7 +400,9 @@ PendSV_Handler:
     msr psp, r0                             /* Remember the new top of stack for the task. */
     subs r0, r0, #40                        /* Move to the starting of the saved context. */
     ldmia r0!, {r2-r7}                      /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
     msr psplim, r2                          /* Restore the PSPLIM register value for the task. */
+#endif
     bx r3
 
 #endif /* configENABLE_MPU */
@@ -401,21 +423,17 @@ SVC_Handler:
         b route_svc
 
     route_svc:
-        ldr r2, [r0, #24]
-        subs r2, #2
-        ldrb r3, [r2, #0]
-        cmp r3, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-        beq system_call_enter
-        cmp r3, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-        beq system_call_enter_1
-        cmp r3, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+        ldr r3, [r0, #24]
+        subs r3, #2
+        ldrb r2, [r3, #0]
+        cmp r2, #NUM_SYSTEM_CALLS
+        blt system_call_enter
+        cmp r2, #104        /* portSVC_SYSTEM_CALL_EXIT. */
         beq system_call_exit
         b vPortSVCHandler_C
 
     system_call_enter:
         b vSystemCallEnter
-    system_call_enter_1:
-        b vSystemCallEnter_1
     system_call_exit:
         b vSystemCallExit
 

portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -48,9 +48,10 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME         "Cortex-M23"
-#define portHAS_BASEPRI       0
-#define portDONT_DISCARD      __root
+#define portARCH_NAME                    "Cortex-M23"
+#define portHAS_ARMV8M_MAIN_EXTENSION    0
+#define portARMV8M_MINOR_VERSION         0
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
@@ -60,6 +61,12 @@
 #if ( configTOTAL_MPU_REGIONS == 16 )
     #error 16 MPU regions are not yet supported for this port.
 #endif
+
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif ( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M23.
+#endif
 /*-----------------------------------------------------------*/
 
 /**

portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s

@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -32,6 +34,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -44,7 +49,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN SecureContext_LoadContext
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -86,7 +90,7 @@ vResetPrivilege:
 /*-----------------------------------------------------------*/
 
 vPortAllocateSecureContext:
-    svc 0                                   /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+    svc 100                                 /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 100. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 
@@ -148,6 +152,14 @@ vRestoreContextOfFirstTask:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -173,12 +185,22 @@ vRestoreContextOfFirstTask:
     ldr  r3, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r3]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4.  */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r3}                       /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
     ldr  r4, =xSecureContext
     str  r1, [r4]                           /* Set xSecureContext to this task's value for the same. */
     msr  psplim, r2                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
@@ -205,13 +227,13 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -266,11 +288,20 @@ PendSV_Handler:
         mrs r4, psplim                      /* r4 = PSPLIM. */
         mrs r5, control                     /* r5 = CONTROL. */
         stmia r2!, {r0, r3-r5, lr}          /* Store xSecureContext, original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
-        str r2, [r1]                        /* Save the location from where the context should be restored as the first member of TCB. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_1
+        mrs  r5, PAC_KEY_P_2
+        mrs  r6, PAC_KEY_P_3
+        stmia r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -324,6 +355,14 @@ PendSV_Handler:
         ldr r2, [r1]                        /* r2 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r2!, {r3-r6}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r4
+        msr  PAC_KEY_P_2, r5
+        msr  PAC_KEY_P_3, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
         ldmdb r2!, {r0, r3-r5, lr}          /* r0 = xSecureContext, r3 = original PSP, r4 = PSPLIM, r5 = CONTROL, LR restored. */
         msr psp, r3
         msr psplim, r4
@@ -369,76 +408,86 @@ PendSV_Handler:
     mrs r2, psp                             /* Read PSP in r2. */
 
     cbz r0, save_ns_context                 /* No secure context to save. */
-    push {r0-r2, r14}
-    bl SecureContext_SaveContext            /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-    pop {r0-r3}                             /* LR is now in r3. */
-    mov lr, r3                              /* LR = r3. */
-    lsls r1, r3, #25                        /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-    bpl save_ns_context                     /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-
-    ldr r3, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-    ldr r1, [r3]                            /* Read pxCurrentTCB. */
-    subs r2, r2, #12                        /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-    str r2, [r1]                            /* Save the new top of stack in TCB. */
-    mrs r1, psplim                          /* r1 = PSPLIM. */
-    mov r3, lr                              /* r3 = LR/EXC_RETURN. */
-    stmia r2!, {r0, r1, r3}                 /* Store xSecureContext, PSPLIM and LR on the stack. */
-    b select_next_task
+    save_s_context:
+        push {r0-r2, lr}
+        bl SecureContext_SaveContext       /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
+        pop {r0-r2, lr}
 
     save_ns_context:
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
+        mov r3, lr                          /* r3 = LR. */
+        lsls r3, r3, #25                    /* r3 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi save_special_regs               /* If r3 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used. */
+
+    save_general_regs:
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vstmdbeq r2!, {s16-s31}             /* Store the additional FP context registers which are not saved automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-        subs r2, r2, #44                    /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-        str r2, [r1]                        /* Save the new top of stack in TCB. */
-        adds r2, r2, #12                    /* r2 = r2 + 12. */
-        stm r2, {r4-r11}                    /* Store the registers that are not saved automatically. */
-        mrs r1, psplim                      /* r1 = PSPLIM. */
-        mov r3, lr                          /* r3 = LR/EXC_RETURN. */
-        subs r2, r2, #12                    /* r2 = r2 - 12. */
-        stmia r2!, {r0, r1, r3}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+        stmdb r2!, {r4-r11}                 /* Store the registers that are not saved automatically. */
+
+    save_special_regs:
+        mrs r3, psplim                      /* r3 = PSPLIM. */
+        stmdb r2!, {r0, r3, lr}             /* Store xSecureContext, PSPLIM and LR on the stack. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r3, PAC_KEY_P_3                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_1
+        mrs  r6, PAC_KEY_P_0
+        stmdb r2!, {r3-r6}                  /* Store the task's dedicated PAC key on the stack. */
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+
+    str r2, [r1]                            /* Save the new top of stack in TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
         mov r0, #0                          /* r0 = 0. */
         msr basepri, r0                     /* Enable interrupts. */
 
+    restore_context:
         ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
         ldr r1, [r3]                        /* Read pxCurrentTCB. */
         ldr r2, [r1]                        /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
 
-        ldmia r2!, {r0, r1, r4}             /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
-        msr psplim, r1                      /* Restore the PSPLIM register value for the task. */
-        mov lr, r4                          /* LR = r4. */
+    restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmia r2!, {r3-r6}                  /* Read task's dedicated PAC key from stack. */
+        msr  PAC_KEY_P_3, r3                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_1, r5
+        msr  PAC_KEY_P_0, r6
+        clrm {r3-r6}                        /* Clear r3-r6. */
+    #endif /* configENABLE_PAC */
+        ldmia r2!, {r0, r3, lr}             http://files.iar.com/ftp/pub/box/bxarm-9.60.3.deb/* Read from stack - r0 = xSecureContext, r3 = PSPLIM and LR restored. */
+        msr psplim, r3                      /* Restore the PSPLIM register value for the task. */
         ldr r3, =xSecureContext             /* Read the location of xSecureContext i.e. &( xSecureContext ). */
         str r0, [r3]                        /* Restore the task's xSecureContext. */
         cbz r0, restore_ns_context          /* If there is no secure context for the task, restore the non-secure context. */
-        ldr r3, =pxCurrentTCB               /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-        ldr r1, [r3]                        /* Read pxCurrentTCB. */
-        push {r2, r4}
+
+    restore_s_context:
+        push {r1-r3, lr}
         bl SecureContext_LoadContext        /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
-        pop {r2, r4}
-        mov lr, r4                          /* LR = r4. */
-        lsls r1, r4, #25                    /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-        bpl restore_ns_context              /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-        msr psp, r2                         /* Remember the new top of stack for the task. */
-        bx lr
+        pop {r1-r3, lr}
 
     restore_ns_context:
+        mov r0, lr                          /* r0 = LR (EXC_RETURN). */
+        lsls r0, r0, #25                    /* r0 = r0 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bmi restore_context_done            /* r0 < 0 ==> Bit[6] in EXC_RETURN is 1 ==> secure stack was used to store the stack frame. */
+
+    restore_general_regs:
         ldmia r2!, {r4-r11}                 /* Restore the registers that are not automatically restored. */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
         tst lr, #0x10                       /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the Extended Stack Frame is in use. */
         it eq
         vldmiaeq r2!, {s16-s31}             /* Restore the additional FP context registers which are not restored automatically. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
+
+    restore_context_done:
         msr psp, r2                         /* Remember the new top of stack for the task. */
         bx lr
 
@@ -455,11 +504,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -467,10 +514,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit
@@ -493,7 +536,7 @@ vPortFreeSecureContext:
     ldr r1, [r2]                            /* The first item on the stack is the task's xSecureContext. */
     cmp r1, #0                              /* Raise svc if task's xSecureContext is not NULL. */
     it ne
-    svcne 1                                 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+    svcne 101                               /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 101. */
     bx lr                                   /* Return. */
 /*-----------------------------------------------------------*/
 

portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -48,25 +48,28 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
-#define portDONT_DISCARD                    __root
-/*-----------------------------------------------------------*/
-
-#if( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif ( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
+#endif
+/*-----------------------------------------------------------*/
+
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in

portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s

@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -32,6 +34,9 @@ the code is included in C files but excluded by the preprocessor in assembly
 files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
 #include "FreeRTOSConfig.h"
 
+/* System call numbers includes. */
+#include "mpu_syscall_numbers.h"
+
 #ifndef configUSE_MPU_WRAPPERS_V1
     #define configUSE_MPU_WRAPPERS_V1 0
 #endif
@@ -41,7 +46,6 @@ files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler.
     EXTERN vPortSVCHandler_C
 #if ( ( configENABLE_MPU == 1 ) && ( configUSE_MPU_WRAPPERS_V1 == 0 ) )
     EXTERN vSystemCallEnter
-    EXTERN vSystemCallEnter_1
     EXTERN vSystemCallExit
 #endif
 
@@ -138,6 +142,14 @@ vRestoreContextOfFirstTask:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs_first_task:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -161,10 +173,20 @@ vRestoreContextOfFirstTask:
     ldr  r1, [r2]                           /* Read pxCurrentTCB. */
     ldr  r0, [r1]                           /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r1-r4}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r1                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r2
+    msr  PAC_KEY_P_1, r3
+    msr  PAC_KEY_P_0, r4
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldm  r0!, {r1-r2}                       /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
     msr  psplim, r1                         /* Set this task's PSPLIM value. */
-    movs r1, #2                             /* r1 = 2. */
-    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    mrs  r1, control                        /* Obtain current control register value. */
+    orrs r1, r1, #2                         /* r1 = r1 | 0x2 - Set the second bit to use the program stack pointe (PSP). */
+    msr control, r1                         /* Write back the new control register value. */
     adds r0, #32                            /* Discard everything up to r0. */
     msr  psp, r0                            /* This is now the new top of stack to use in the task. */
     isb
@@ -191,13 +213,13 @@ vStartFirstTask:
     cpsie f
     dsb
     isb
-    svc 2                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+    svc 102                                 /* System call to start the first task. portSVC_START_SCHEDULER = 102. */
 /*-----------------------------------------------------------*/
 
 ulSetInterruptMask:
     mrs r0, basepri                         /* r0 = basepri. Return original basepri value. */
     mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r1                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r1                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bx lr                                   /* Return. */
@@ -228,7 +250,6 @@ PendSV_Handler:
         vstmiaeq r1!, {s0-s16}              /* Store hardware saved FP context. */
         sub r2, r2, #0x20                   /* Set r2 back to the location of hardware saved context. */
     #endif /* configENABLE_FPU || configENABLE_MVE */
-
         stmia r1!, {r4-r11}                 /* Store r4-r11. */
         ldmia r2, {r4-r11}                  /* Copy the hardware saved context into r4-r11. */
         stmia r1!, {r4-r11}                 /* Store the hardware saved context. */
@@ -237,11 +258,20 @@ PendSV_Handler:
         mrs r3, psplim                      /* r3 = PSPLIM. */
         mrs r4, control                     /* r4 = CONTROL. */
         stmia r1!, {r2-r4, lr}              /* Store original PSP (after hardware has saved context), PSPLIM, CONTROL and LR. */
+    #if ( configENABLE_PAC == 1 )
+        mrs  r2, PAC_KEY_P_0                /* Read task's dedicated PAC key from the PAC key registers. */
+        mrs  r3, PAC_KEY_P_1
+        mrs  r4, PAC_KEY_P_2
+        mrs  r5, PAC_KEY_P_3
+        stmia r1!, {r2-r5}                  /* Store the task's dedicated PAC key on the task's context. */
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
+
         str r1, [r0]                        /* Save the location from where the context should be restored as the first member of TCB. */
 
     select_next_task:
         mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-        msr basepri, r0                     /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        msr basepri, r0                     /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
         dsb
         isb
         bl vTaskSwitchContext
@@ -295,6 +325,14 @@ PendSV_Handler:
         ldr r1, [r0]                        /* r1 = Location of saved context in TCB. */
 
     restore_special_regs:
+    #if ( configENABLE_PAC == 1 )
+        ldmdb r1!, {r2-r5}                  /* Read task's dedicated PAC key from the task's context. */
+        msr  PAC_KEY_P_0, r2                /* Write the task's dedicated PAC key to the PAC key registers. */
+        msr  PAC_KEY_P_1, r3
+        msr  PAC_KEY_P_2, r4
+        msr  PAC_KEY_P_3, r5
+        clrm {r2-r5}                        /* Clear r2-r5. */
+    #endif /* configENABLE_PAC */
         ldmdb r1!, {r2-r4, lr}              /* r2 = original PSP, r3 = PSPLIM, r4 = CONTROL, LR restored. */
         msr psp, r2
         msr psplim, r3
@@ -330,12 +368,21 @@ PendSV_Handler:
     mov r3, lr                              /* r3 = LR/EXC_RETURN. */
     stmdb r0!, {r2-r11}                     /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
 
+#if ( configENABLE_PAC == 1 )
+    mrs  r1, PAC_KEY_P_3                    /* Read task's dedicated PAC key from the PAC key registers. */
+    mrs  r2, PAC_KEY_P_2
+    mrs  r3, PAC_KEY_P_1
+    mrs  r4, PAC_KEY_P_0
+    stmdb r0!, {r1-r4}                      /* Store the task's dedicated PAC key on the stack. */
+    clrm {r1-r4}                            /* Clear r1-r4. */
+#endif /* configENABLE_PAC */
+
     ldr r2, =pxCurrentTCB                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     str r0, [r1]                            /* Save the new top of stack in TCB. */
 
     mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-    msr basepri, r0                         /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+    msr basepri, r0                         /* Disable interrupts up to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
     dsb
     isb
     bl vTaskSwitchContext
@@ -346,6 +393,15 @@ PendSV_Handler:
     ldr r1, [r2]                            /* Read pxCurrentTCB. */
     ldr r0, [r1]                            /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
 
+#if ( configENABLE_PAC == 1 )
+    ldmia r0!, {r2-r5}                      /* Read task's dedicated PAC key from stack. */
+    msr  PAC_KEY_P_3, r2                    /* Write the task's dedicated PAC key to the PAC key registers. */
+    msr  PAC_KEY_P_2, r3
+    msr  PAC_KEY_P_1, r4
+    msr  PAC_KEY_P_0, r5
+    clrm {r2-r5}                            /* Clear r2-r5. */
+#endif /* configENABLE_PAC */
+
     ldmia r0!, {r2-r11}                     /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
 
 #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
@@ -371,11 +427,9 @@ SVC_Handler:
 
     ldr r1, [r0, #24]
     ldrb r2, [r1, #-2]
-    cmp r2, #4          /* portSVC_SYSTEM_CALL_ENTER. */
-    beq syscall_enter
-    cmp r2, #5          /* portSVC_SYSTEM_CALL_ENTER_1. */
-    beq syscall_enter_1
-    cmp r2, #6          /* portSVC_SYSTEM_CALL_EXIT. */
+    cmp r2, #NUM_SYSTEM_CALLS
+    blt syscall_enter
+    cmp r2, #104            /* portSVC_SYSTEM_CALL_EXIT. */
     beq syscall_exit
     b vPortSVCHandler_C
 
@@ -383,10 +437,6 @@ SVC_Handler:
         mov r1, lr
         b vSystemCallEnter
 
-    syscall_enter_1:
-        mov r1, lr
-        b vSystemCallEnter_1
-
     syscall_exit:
         mov r1, lr
         b vSystemCallExit

portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -48,25 +48,28 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M33"
-#define portHAS_BASEPRI                     1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M33"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif ( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M33.
 #endif
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in

portable/ARMv8M/non_secure/portable/IAR/ARM_CM35P/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -48,25 +48,28 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M35P"
-#define portHAS_BASEPRI                     1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M35P"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         0
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
+#ifndef configENABLE_MVE
+    #define configENABLE_MVE    0
+#elif ( configENABLE_MVE != 0 )
+    #error configENABLE_MVE must be left undefined, or defined to 0 for the Cortex-M35.
 #endif
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in

portable/ARMv8M/non_secure/portable/IAR/ARM_CM55/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,25 +53,21 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M55"
-#define portHAS_BASEPRI                     1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M55"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in

portable/ARMv8M/non_secure/portable/IAR/ARM_CM85/portmacro.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -53,25 +53,21 @@
 /**
  * Architecture specifics.
  */
-#define portARCH_NAME                       "Cortex-M85"
-#define portHAS_BASEPRI                     1
-#define portDONT_DISCARD                    __root
+#define portARCH_NAME                    "Cortex-M85"
+#define portHAS_ARMV8M_MAIN_EXTENSION    1
+#define portARMV8M_MINOR_VERSION         1
+#define portDONT_DISCARD                 __root
 /*-----------------------------------------------------------*/
 
 /* ARMv8-M common port configurations. */
 #include "portmacrocommon.h"
 /*-----------------------------------------------------------*/
 
-#if( configTOTAL_MPU_REGIONS == 16 )
-    #error 16 MPU regions are not yet supported for this port.
-#endif
-/*-----------------------------------------------------------*/
-
 /**
  * @brief Critical section management.
  */
-#define portDISABLE_INTERRUPTS()            ulSetInterruptMask()
-#define portENABLE_INTERRUPTS()             vClearInterruptMask( 0 )
+#define portDISABLE_INTERRUPTS()    ulSetInterruptMask()
+#define portENABLE_INTERRUPTS()     vClearInterruptMask( 0 )
 /*-----------------------------------------------------------*/
 
 /* Suppress warnings that are generated by the IAR tools, but cannot be fixed in

portable/ARMv8M/non_secure/portasm.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -52,7 +52,7 @@ BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
  * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
  * register.
  *
- * @note This is a privileged function and should only be called from the kenrel
+ * @note This is a privileged function and should only be called from the kernel
  * code.
  *
  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.

portable/ARMv8M/non_secure/portmacrocommon.h

@@ -1,6 +1,8 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ * Copyright 2024 Arm Limited and/or its affiliates
+ * <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: MIT
  *
@@ -117,7 +119,7 @@ extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGE
 extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
 
 #if ( configENABLE_TRUSTZONE == 1 )
-    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );     /* __attribute__ (( naked )) */
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
     extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
 #endif /* configENABLE_TRUSTZONE */
 
@@ -125,6 +127,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
     extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
 #endif /* configENABLE_MPU */
+
+#if ( configENABLE_PAC == 1 )
+
+    /**
+     * @brief Generates 128-bit task's random PAC key.
+     *
+     * @param[out] pulTaskPacKey Pointer to a 4-word (128-bits) array to be
+     *             filled with a 128-bit random number.
+     */
+    void vApplicationGenerateTaskRandomPacKey( uint32_t * pulTaskPacKey );
+
+#endif /* configENABLE_PAC */
 /*-----------------------------------------------------------*/
 
 /**
@@ -137,7 +151,7 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
     #define portPRIVILEGE_BIT         ( 0x0UL )
 #endif /* configENABLE_MPU */
 
-/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+/* MPU settings that can be overridden in FreeRTOSConfig.h. */
 #ifndef configTOTAL_MPU_REGIONS
     /* Define to 8 for backward compatibility. */
     #define configTOTAL_MPU_REGIONS    ( 8UL )
@@ -193,8 +207,8 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
      */
     typedef struct MPURegionSettings
     {
-        uint32_t ulRBAR;     /**< RBAR for the region. */
-        uint32_t ulRLAR;     /**< RLAR for the region. */
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
     } MPURegionSettings_t;
 
     #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
@@ -223,7 +237,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
      */
     #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) )
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +-----------+---------------+----------+-----------------+------------------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><-----------------------------><-----------><---->
+             *      16             17            8               8                     5                     16         1
+             */
+            #define MAX_CONTEXT_SIZE    71
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
             /*
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
@@ -232,11 +259,24 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+------------------------------+-----+
              *
              * <-----------><--------------><---------><----------------><-----------------------------><---->
-             *      16             16            8               8                     5                   1
+             *      16             17            8               8                     5                   1
              */
-            #define MAX_CONTEXT_SIZE 54
+            #define MAX_CONTEXT_SIZE    55
 
-        #else /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             * |  s16-s31  | s0-s15, FPSCR |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |           |               |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +-----------+---------------+----------+-----------------+----------------------+------------+-----+
+             *
+             * <-----------><--------------><---------><----------------><---------------------><-----------><---->
+             *      16             17            8               8                  4                16         1
+             */
+            #define MAX_CONTEXT_SIZE    70
+
+        #else /* if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
             /*
              * +-----------+---------------+----------+-----------------+----------------------+-----+
@@ -245,15 +285,28 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * +-----------+---------------+----------+-----------------+----------------------+-----+
              *
              * <-----------><--------------><---------><----------------><---------------------><---->
-             *      16             16            8               8                  4              1
+             *      16             17            8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE 53
+            #define MAX_CONTEXT_SIZE    54
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #else /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
-        #if( configENABLE_TRUSTZONE == 1 )
+        #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+------------------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | xSecureContext, PSP, PSPLIM, | TaskPacKey |     |
+             * |          | PC, xPSR        | CONTROL, EXC_RETURN          |            |     |
+             * +----------+-----------------+------------------------------+------------+-----+
+             *
+             * <---------><----------------><------------------------------><-----------><---->
+             *     8               8                      5                      16         1
+             */
+            #define MAX_CONTEXT_SIZE    38
+
+        #elif ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 0 ) )
 
             /*
              * +----------+-----------------+------------------------------+-----+
@@ -264,7 +317,20 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * <---------><----------------><------------------------------><---->
              *     8               8                      5                   1
              */
-            #define MAX_CONTEXT_SIZE 22
+            #define MAX_CONTEXT_SIZE    22
+
+        #elif ( ( configENABLE_TRUSTZONE == 0 ) && ( configENABLE_PAC == 1 ) )
+
+            /*
+             * +----------+-----------------+----------------------+------------+-----+
+             * |  r4-r11  | r0-r3, r12, LR, | PSP, PSPLIM, CONTROL | TaskPacKey |     |
+             * |          | PC, xPSR        | EXC_RETURN           |            |     |
+             * +----------+-----------------+----------------------+------------+-----+
+             *
+             * <---------><----------------><----------------------><-----------><---->
+             *     8               8                  4                  16         1
+             */
+            #define MAX_CONTEXT_SIZE    37
 
         #else /* #if( configENABLE_TRUSTZONE == 1 ) */
 
@@ -277,15 +343,18 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
              * <---------><----------------><----------------------><---->
              *     8               8                  4              1
              */
-            #define MAX_CONTEXT_SIZE 21
+            #define MAX_CONTEXT_SIZE    21
 
-        #endif /* #if( configENABLE_TRUSTZONE == 1 ) */
+        #endif /* #if ( ( configENABLE_TRUSTZONE == 1 ) && ( configENABLE_PAC == 1 ) ) */
 
     #endif /* #if ( ( configENABLE_FPU == 1 ) || ( configENABLE_MVE == 1 ) ) */
 
     /* Flags used for xMPU_SETTINGS.ulTaskFlags member. */
-    #define portSTACK_FRAME_HAS_PADDING_FLAG     ( 1UL << 0UL )
-    #define portTASK_IS_PRIVILEGED_FLAG          ( 1UL << 1UL )
+    #define portSTACK_FRAME_HAS_PADDING_FLAG    ( 1UL << 0UL )
+    #define portTASK_IS_PRIVILEGED_FLAG         ( 1UL << 1UL )
+
+    /* Size of an Access Control List (ACL) entry in bits. */
+    #define portACL_ENTRY_SIZE_BITS             ( 32U )
 
     typedef struct MPU_SETTINGS
     {
@@ -296,6 +365,9 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
         #if ( configUSE_MPU_WRAPPERS_V1 == 0 )
             xSYSTEM_CALL_STACK_INFO xSystemCallStackInfo;
+            #if ( configENABLE_ACCESS_CONTROL_LIST == 1 )
+                uint32_t ulAccessControlList[ ( configPROTECTED_KERNEL_OBJECT_POOL_SIZE / portACL_ENTRY_SIZE_BITS ) + 1 ];
+            #endif
         #endif
     } xMPU_SETTINGS;
 
@@ -306,8 +378,8 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
  * @brief Validate priority of ISRs that are allowed to call FreeRTOS
  * system calls.
  */
-#ifdef configASSERT
-    #if ( portHAS_BASEPRI == 1 )
+#if ( configASSERT_DEFINED == 1 )
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
         void vPortValidateInterruptPriority( void );
         #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
     #endif
@@ -316,24 +388,40 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 /**
  * @brief SVC numbers.
  */
-#define portSVC_ALLOCATE_SECURE_CONTEXT    0
-#define portSVC_FREE_SECURE_CONTEXT        1
-#define portSVC_START_SCHEDULER            2
-#define portSVC_RAISE_PRIVILEGE            3
-#define portSVC_SYSTEM_CALL_ENTER          4   /* System calls with upto 4 parameters. */
-#define portSVC_SYSTEM_CALL_ENTER_1        5   /* System calls with 5 parameters. */
-#define portSVC_SYSTEM_CALL_EXIT           6
+#define portSVC_ALLOCATE_SECURE_CONTEXT    100
+#define portSVC_FREE_SECURE_CONTEXT        101
+#define portSVC_START_SCHEDULER            102
+#define portSVC_RAISE_PRIVILEGE            103
+#define portSVC_SYSTEM_CALL_EXIT           104
+#define portSVC_YIELD                      105
 /*-----------------------------------------------------------*/
 
 /**
  * @brief Scheduler utilities.
  */
-#define portYIELD()    vPortYield()
+#if ( configENABLE_MPU == 1 )
+    #define portYIELD()               __asm volatile ( "svc %0" ::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()    vPortYield()
+#else
+    #define portYIELD()               vPortYield()
+    #define portYIELD_WITHIN_API()    vPortYield()
+#endif
+
 #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
 #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )                                 \
-    do { if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; } \
-    while( 0 )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            \
+    do                                                      \
+    {                                                       \
+        if( xSwitchRequired )                               \
+        {                                                   \
+            traceISR_EXIT_TO_SCHEDULER();                   \
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        }                                                   \
+        else                                                \
+        {                                                   \
+            traceISR_EXIT();                                \
+        }                                                   \
+    } while( 0 )
 #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
 /*-----------------------------------------------------------*/
 
@@ -419,12 +507,12 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 
     extern BaseType_t xPortIsTaskPrivileged( void );
 
-    /**
-     * @brief Checks whether or not the calling task is privileged.
-     *
-     * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
-     */
-    #define portIS_TASK_PRIVILEGED()      xPortIsTaskPrivileged()
+/**
+ * @brief Checks whether or not the calling task is privileged.
+ *
+ * @return pdTRUE if the calling task is privileged, pdFALSE otherwise.
+ */
+    #define portIS_TASK_PRIVILEGED()    xPortIsTaskPrivileged()
 
 #endif /* configENABLE_MPU == 1 */
 /*-----------------------------------------------------------*/
@@ -435,6 +523,56 @@ extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) P
 #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
 /*-----------------------------------------------------------*/
 
+/* Select correct value of configUSE_PORT_OPTIMISED_TASK_SELECTION
+ * based on whether or not Mainline extension is implemented. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 1 )
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #else
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
+    #endif
+#endif /* #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/**
+ * @brief Port-optimised task selection.
+ */
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/**
+ * @brief Count the number of leading zeros in a 32-bit value.
+ */
+    static portFORCE_INLINE uint32_t ulPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint32_t ulReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ulReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ulReturn;
+    }
+
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+
+    #if ( portHAS_ARMV8M_MAIN_EXTENSION == 0 )
+        #error ARMv8-M baseline implementations (such as Cortex-M23) do not support port-optimised task selection.  Please set configUSE_PORT_OPTIMISED_TASK_SELECTION to 0 or leave it undefined.
+    #endif
+
+/**
+ * @brief Store/clear the ready priorities in a bit map.
+ */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )      ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )       ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/**
+ * @brief Get the priority of the highest-priority task that is ready to execute.
+ */
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ulPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
 /* *INDENT-OFF* */
 #ifdef __cplusplus
     }

portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *

portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *

portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *

portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *

portable/ARMv8M/secure/context/secure_context.c

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -65,7 +65,7 @@
  * @brief Maximum number of secure contexts.
  */
 #ifndef secureconfigMAX_SECURE_CONTEXTS
-    #define secureconfigMAX_SECURE_CONTEXTS        8UL
+    #define secureconfigMAX_SECURE_CONTEXTS    8UL
 #endif
 /*-----------------------------------------------------------*/
 
@@ -164,15 +164,15 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
         }
 
         #if ( configENABLE_MPU == 1 )
-            {
-                /* Configure thread mode to use PSP and to be unprivileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
         #else /* configENABLE_MPU */
-            {
-                /* Configure thread mode to use PSP and to be privileged. */
-                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-            }
+        {
+            /* Configure thread mode to use PSP and to be privileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
         #endif /* configENABLE_MPU */
     }
 }
@@ -207,7 +207,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
      * securecontextNO_STACK when no secure context is loaded. */
     if( ( ulIPSR != 0 ) && ( pucStackLimit == securecontextNO_STACK ) )
     {
-        /* Ontain a free secure context. */
+        /* Obtain a free secure context. */
         ulSecureContextIndex = ulGetSecureContext( pvTaskHandle );
 
         /* Were we able to get a free context? */
@@ -219,16 +219,16 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
             if( pucStackMemory != NULL )
             {
                 /* Since stack grows down, the starting point will be the last
-                 * location. Note that this location is next to the last
-                 * allocated byte for stack (excluding the space for seal values)
-                 * because the hardware decrements the stack pointer before
-                 * writing i.e. if stack pointer is 0x2, a push operation will
-                 * decrement the stack pointer to 0x1 and then write at 0x1. */
+                * location. Note that this location is next to the last
+                * allocated byte for stack (excluding the space for seal values)
+                * because the hardware decrements the stack pointer before
+                * writing i.e. if stack pointer is 0x2, a push operation will
+                * decrement the stack pointer to 0x1 and then write at 0x1. */
                 xSecureContexts[ ulSecureContextIndex ].pucStackStart = pucStackMemory + ulSecureStackSize;
 
                 /* Seal the created secure process stack. */
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
-                *( uint32_t * )( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize ) = securecontextSTACK_SEAL_VALUE;
+                *( uint32_t * ) ( pucStackMemory + ulSecureStackSize + 4 ) = securecontextSTACK_SEAL_VALUE;
 
                 /* The stack cannot go beyond this location. This value is
                  * programmed in the PSPLIM register on context switch.*/
@@ -237,32 +237,32 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
                 xSecureContexts[ ulSecureContextIndex ].pvTaskHandle = pvTaskHandle;
 
                 #if ( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                    pulCurrentStackPointer--;
+
+                    if( ulIsTaskPrivileged )
                     {
-                        /* Store the correct CONTROL value for the task on the stack.
-                         * This value is programmed in the CONTROL register on
-                         * context switch. */
-                        pulCurrentStackPointer = ( uint32_t * ) xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                        pulCurrentStackPointer--;
-
-                        if( ulIsTaskPrivileged )
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-                        }
-                        else
-                        {
-                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-                        }
-
-                        /* Store the current stack pointer. This value is programmed in
-                         * the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
                     }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
                 #else /* configENABLE_MPU */
-                    {
-                        /* Current SP is set to the starting of the stack. This
-                         * value programmed in the PSP register on context switch. */
-                        xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
-                    }
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContexts[ ulSecureContextIndex ].pucCurrentStackPointer = xSecureContexts[ ulSecureContextIndex ].pucStackStart;
+                }
                 #endif /* configENABLE_MPU */
 
                 /* Ensure to never return 0 as a valid context handle. */
@@ -275,7 +275,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint32_t ulIPSR, ulSecureContextIndex;
 
@@ -306,7 +307,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;
@@ -328,7 +330,8 @@ secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandl
 }
 /*-----------------------------------------------------------*/
 
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle )
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                                              void * pvTaskHandle )
 {
     uint8_t * pucStackLimit;
     uint32_t ulSecureContextIndex;

portable/ARMv8M/secure/context/secure_context.h

@@ -1,6 +1,6 @@
 /*
  * FreeRTOS Kernel <DEVELOPMENT BRANCH>
- * Copyright (C) 2021 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -38,12 +38,12 @@
 /**
  * @brief PSP value when no secure context is loaded.
  */
-#define securecontextNO_STACK               0x0
+#define securecontextNO_STACK              0x0
 
 /**
  * @brief Invalid context ID.
  */
-#define securecontextINVALID_CONTEXT_ID     0UL
+#define securecontextINVALID_CONTEXT_ID    0UL
 /*-----------------------------------------------------------*/
 
 /**
@@ -108,7 +108,8 @@ void SecureContext_Init( void );
  * @param[in] xSecureContextHandle Context handle corresponding to the
  * context to be freed.
  */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Loads the given context.
@@ -119,7 +120,8 @@ void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be loaded.
  */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 /**
  * @brief Saves the given context.
@@ -130,6 +132,7 @@ void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle, void
  * @param[in] xSecureContextHandle Context handle corresponding to the context
  * to be saved.
  */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle, void * pvTaskHandle );
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle,
+                                void * pvTaskHandle );
 
 #endif /* __SECURE_CONTEXT_H__ */