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opus: name the ARM inline-asm gates after the cores they cover
Upstream's OPUS_ARM_INLINE_ASM means any ARM with inline assembly, with OPUS_ARM_INLINE_EDSP layered on top for ARMv5E. config.h instead defines exactly one of them per core, so the names read as broader than they are, and code added ARM_ARCH tests beside them to pin the scope down. Renamed to OPUS_ARM_ASM_ARMV4_ONLY and OPUS_ARM_ASM_ARMV5E_AND_LATER throughout celt and silk, upstream files included; README.rockbox records it for the next libopus sync. No code change: opus.elf disassembly and section sizes are identical before and after on ARMv4 (e200v1), ARMv5E (Clip+) and ARMv6 (iPod Nano 4G). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Change-Id: I89932d348dedd76748a1bc7b3f2e7de1c5be49c8
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14 changed files with 28 additions and 23 deletions
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@ -13,6 +13,9 @@ Opus:
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Celt:
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* changed #if FIXED_POINT to #ifdef FIXED_POINT in bands.c
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* changed #elif OPUS_ARM_INLINE_EDSP to #elif defined (OPUS_ARM_INLINE_EDSP)
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* renamed OPUS_ARM_INLINE_ASM to OPUS_ARM_ASM_ARMV4_ONLY and
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OPUS_ARM_INLINE_EDSP to OPUS_ARM_ASM_ARMV5E_AND_LATER throughout celt and
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silk, since config.h defines exactly one of them per core
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* add #define ABS(a)(((a) < 0) ? - (a) :(a)) to mathops.h
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Opus-tools:
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@ -90,11 +90,11 @@
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do {(res).r = ADD32_ovflw((res).r,(a).r); (res).i = SUB32_ovflw((res).i,(a).i); \
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}while(0)
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#if defined(OPUS_ARM_INLINE_ASM)
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#if defined(OPUS_ARM_ASM_ARMV4_ONLY)
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#include "arm/kiss_fft_armv4.h"
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#endif
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#if defined(OPUS_ARM_INLINE_EDSP)
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#if defined(OPUS_ARM_ASM_ARMV5E_AND_LATER)
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#include "arm/kiss_fft_armv5e.h"
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#endif
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#if defined(OPUS_CF_INLINE_ASM)
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@ -173,9 +173,9 @@ static OPUS_INLINE opus_int16 SAT16(opus_int32 x) {
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#ifdef OPUS_ARM_PRESUME_AARCH64_NEON_INTR
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#include "arm/fixed_arm64.h"
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#elif defined (OPUS_ARM_INLINE_EDSP)
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#elif defined (OPUS_ARM_ASM_ARMV5E_AND_LATER)
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#include "arm/fixed_armv5e.h"
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#elif defined (OPUS_ARM_INLINE_ASM)
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#elif defined (OPUS_ARM_ASM_ARMV4_ONLY)
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#include "arm/fixed_armv4.h"
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#elif defined (BFIN_ASM)
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#include "fixed_bfin.h"
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@ -35,14 +35,14 @@
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#if defined(FIXED_POINT) && !defined(OPUS_ARM_NO_BANDS_ASM)
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# if defined(OPUS_ARM_INLINE_ASM) && (ARM_ARCH == 4)
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# if defined(OPUS_ARM_ASM_ARMV4_ONLY) && (ARM_ARCH == 4)
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# define OVERRIDE_DENORM_BAND
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void denorm_band_armv4(celt_sig *f, const celt_norm *x, int n, int g,
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int shift);
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# define DENORM_BAND denorm_band_armv4
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# elif defined(OPUS_ARM_INLINE_EDSP) && (ARM_ARCH >= 5)
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# elif defined(OPUS_ARM_ASM_ARMV5E_AND_LATER) && (ARM_ARCH >= 5)
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# define OVERRIDE_DENORM_BAND
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void denorm_band_armv5e(celt_sig *f, const celt_norm *x, int n, int g,
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@ -38,7 +38,7 @@
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#if defined(FIXED_POINT) && !defined(CUSTOM_MODES) \
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&& !defined(OPUS_ARM_NO_COMB_ASM)
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# if defined(OPUS_ARM_INLINE_ASM) && (ARM_ARCH == 4)
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# if defined(OPUS_ARM_ASM_ARMV4_ONLY) && (ARM_ARCH == 4)
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# define OVERRIDE_COMB_FILTER_CONST
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void comb_filter_const_armv4(opus_val32 *y, opus_val32 *x, int T, int N,
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@ -61,7 +61,7 @@ void deemph_stereo_armv4(celt_sig *x0, celt_sig *x1, opus_val16 *pcm, int N,
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# define deemphasis_stereo_simple(in, pcm, N, coef0, mem) \
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deemph_stereo_armv4((in)[0], (in)[1], (pcm), (N), (coef0), (mem))
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# elif defined(OPUS_ARM_INLINE_EDSP) && (ARM_ARCH >= 5)
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# elif defined(OPUS_ARM_ASM_ARMV5E_AND_LATER) && (ARM_ARCH >= 5)
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# define OVERRIDE_COMB_FILTER_CONST
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void comb_filter_const_armv5e(opus_val32 *y, opus_val32 *x, int T, int N,
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@ -34,7 +34,7 @@
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Building with OPUS_ARM_NO_MDCT_ASM selects the C loops instead, which is
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how the two are compared. */
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#if defined(OPUS_ARM_INLINE_ASM) && defined(FIXED_POINT) \
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#if defined(OPUS_ARM_ASM_ARMV4_ONLY) && defined(FIXED_POINT) \
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&& !defined(OPUS_ARM_NO_MDCT_ASM)
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#define OVERRIDE_MDCT_PREROT
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@ -38,7 +38,7 @@
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Building with OPUS_ARM_NO_MDCT_ASM selects the C loops instead, which is
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how the two are compared. */
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#if defined(OPUS_ARM_INLINE_EDSP) && defined(FIXED_POINT) \
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#if defined(OPUS_ARM_ASM_ARMV5E_AND_LATER) && defined(FIXED_POINT) \
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&& (ARM_ARCH >= 5) && !defined(OPUS_ARM_NO_MDCT_ASM)
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#define OVERRIDE_MDCT_PREROT
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@ -11,13 +11,13 @@
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#if defined(FIXED_POINT) && defined(OPUS_PFA)
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#if defined(OPUS_ARM_INLINE_EDSP)
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#if defined(OPUS_ARM_ASM_ARMV5E_AND_LATER)
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#define OVERRIDE_PFA_FFT15
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void pfa_fft15_armv5e(const kiss_fft_cpx *in, kiss_fft_cpx *out, int ostride);
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#define PFA_FFT15(in, out, ostride) pfa_fft15_armv5e(in, out, ostride)
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#elif defined(OPUS_ARM_INLINE_ASM)
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#elif defined(OPUS_ARM_ASM_ARMV4_ONLY)
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#define OVERRIDE_PFA_FFT15
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void pfa_fft15_armv4(const kiss_fft_cpx *in, kiss_fft_cpx *out, int ostride);
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@ -74,7 +74,7 @@ extern void (*const DUAL_INNER_PROD_IMPL[OPUS_ARCHMASK+1])(const opus_val16 *x,
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5.5 after. ARMv4 is deliberately left alone: without the packed
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multiplies the extraction would cost exactly what the saved loads buy.
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Escape hatch OPUS_ARM_NO_PITCH_ASM. */
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# if defined(OPUS_ARM_INLINE_EDSP) && defined(FIXED_POINT) \
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# if defined(OPUS_ARM_ASM_ARMV5E_AND_LATER) && defined(FIXED_POINT) \
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&& !defined(OVERRIDE_DUAL_INNER_PROD) && !defined(OPUS_ARM_NO_PITCH_ASM)
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void dual_inner_prod_armv5e(const opus_val16 *x, const opus_val16 *y01,
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const opus_val16 *y02, int N, opus_val32 *xy1, opus_val32 *xy2);
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@ -36,7 +36,7 @@
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Shares OPUS_ARM_NO_BANDS_ASM with arm/bands_arm.h as the escape hatch. */
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#if defined(FIXED_POINT) && !defined(OPUS_ARM_NO_BANDS_ASM) \
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&& defined(OPUS_ARM_INLINE_EDSP) && (ARM_ARCH >= 5)
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&& defined(OPUS_ARM_ASM_ARMV5E_AND_LATER) && (ARM_ARCH >= 5)
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#define OVERRIDE_vq_exp_rotation1
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void exp_rotation1_armv5e(celt_norm *X, int len, int stride, opus_val16 c,
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@ -52,7 +52,7 @@ void normres_scale_armv5e(celt_norm *X, const int *iy, int N, int g,
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#define NORMRES_SCALE normres_scale_armv5e
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#elif defined(FIXED_POINT) && !defined(OPUS_ARM_NO_BANDS_ASM) \
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&& defined(OPUS_ARM_INLINE_ASM) && (ARM_ARCH == 4)
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&& defined(OPUS_ARM_ASM_ARMV4_ONLY) && (ARM_ARCH == 4)
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#define OVERRIDE_vq_exp_rotation1
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void exp_rotation1_armv4(celt_norm *X, int len, int stride, opus_val16 c,
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@ -64,7 +64,7 @@ static __inline int ec_bsr(unsigned long _x){
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# include "dsplib.h"
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# define EC_CLZ0 (31)
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# define EC_CLZ(_x) (_lnorm(_x))
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#elif defined(OPUS_ARM_INLINE_ASM) && !defined(OPUS_ARM_NO_ILOG_INLINE)
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#elif defined(OPUS_ARM_ASM_ARMV4_ONLY) && !defined(OPUS_ARM_NO_ILOG_INLINE)
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/*ARMv4 has no CLZ instruction, so __builtin_clz compiles to a call to
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libgcc's __clzsi2. Leave EC_CLZ undefined and inline EC_ILOG below.*/
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#elif __GNUC_PREREQ(3,4)
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@ -83,7 +83,7 @@ static __inline int ec_bsr(unsigned long _x){
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The majority of the time we can never pass it zero.
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When we need to, it can be special cased.*/
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# define EC_ILOG(_x) (EC_CLZ0-EC_CLZ(_x))
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#elif defined(OPUS_ARM_INLINE_ASM) && !defined(OPUS_ARM_NO_ILOG_INLINE)
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#elif defined(OPUS_ARM_ASM_ARMV4_ONLY) && !defined(OPUS_ARM_NO_ILOG_INLINE)
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/*Fifteen branchless instructions, no memory access. The libgcc call it
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replaces costs about half again once the call, its table load and the
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caller's register saves are counted. Compares against 0x10000, 0x100 and
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@ -78,10 +78,12 @@
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#if defined(CPU_ARM)
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#define OPUS_ARM_ASM
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/* Upstream's OPUS_ARM_INLINE_ASM and OPUS_ARM_INLINE_EDSP, renamed: upstream
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layers EDSP on top of ASM, but here exactly one is defined per core. */
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#if ARM_ARCH == 4
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#define OPUS_ARM_INLINE_ASM
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#define OPUS_ARM_ASM_ARMV4_ONLY
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#elif ARM_ARCH > 4
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#define OPUS_ARM_INLINE_EDSP
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#define OPUS_ARM_ASM_ARMV5E_AND_LATER
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#if (ARCH_PROFILE == ARM_PROFILE_MICRO)
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#define OPUS_ARM_NO_FFT_ASM
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#define OPUS_ARM_NO_MDCT_ASM
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@ -621,11 +621,11 @@ static OPUS_INLINE opus_int64 silk_max_64(opus_int64 a, opus_int64 b)
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#include "MacroCount.h"
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#include "MacroDebug.h"
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#ifdef OPUS_ARM_INLINE_ASM
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#ifdef OPUS_ARM_ASM_ARMV4_ONLY
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#include "arm/SigProc_FIX_armv4.h"
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#endif
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#ifdef OPUS_ARM_INLINE_EDSP
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#ifdef OPUS_ARM_ASM_ARMV5E_AND_LATER
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#include "arm/SigProc_FIX_armv5e.h"
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#endif
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@ -135,11 +135,11 @@ static OPUS_INLINE opus_int32 silk_CLZ32(opus_int32 in32)
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(*((Matrix_base_adr) + ((row)+(M)*(column))))
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#endif
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#ifdef OPUS_ARM_INLINE_ASM
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#ifdef OPUS_ARM_ASM_ARMV4_ONLY
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#include "arm/macros_armv4.h"
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#endif
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#ifdef OPUS_ARM_INLINE_EDSP
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#ifdef OPUS_ARM_ASM_ARMV5E_AND_LATER
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#include "arm/macros_armv5e.h"
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#endif
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