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c47b2e1be2
Upstream's OPUS_ARM_INLINE_ASM means any ARM with inline assembly, with OPUS_ARM_INLINE_EDSP layered on top for ARMv5E. config.h instead defines exactly one of them per core, so the names read as broader than they are, and code added ARM_ARCH tests beside them to pin the scope down. Renamed to OPUS_ARM_ASM_ARMV4_ONLY and OPUS_ARM_ASM_ARMV5E_AND_LATER throughout celt and silk, upstream files included; README.rockbox records it for the next libopus sync. No code change: opus.elf disassembly and section sizes are identical before and after on ARMv4 (e200v1), ARMv5E (Clip+) and ARMv6 (iPod Nano 4G). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Change-Id: I89932d348dedd76748a1bc7b3f2e7de1c5be49c8
65 lines
3 KiB
C
65 lines
3 KiB
C
/* Copyright (c) 2025 Xiph.Org Foundation and contributors
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Copyright (c) 2026 Michael Giacomelli
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef VQ_ARM_H
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#define VQ_ARM_H
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/* Hand-written loops for celt/vq.c, through the OVERRIDE_vq_exp_rotation1
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hook vq.c already provides. Both architectures have one: the rotation
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chain writes X[i+stride] and reads it straight back as the next x1, so at
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stride 1 one of the two loads is redundant and one of the two stores is
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dead, and both kernels carry that value in a register instead. Bit-exact;
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see celt/arm/exp_rotation1_armv5e_asm.S and _armv4_asm.S.
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Shares OPUS_ARM_NO_BANDS_ASM with arm/bands_arm.h as the escape hatch. */
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#if defined(FIXED_POINT) && !defined(OPUS_ARM_NO_BANDS_ASM) \
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&& defined(OPUS_ARM_ASM_ARMV5E_AND_LATER) && (ARM_ARCH >= 5)
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#define OVERRIDE_vq_exp_rotation1
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void exp_rotation1_armv5e(celt_norm *X, int len, int stride, opus_val16 c,
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opus_val16 s);
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#define exp_rotation1(X, len, stride, c, s) \
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exp_rotation1_armv5e((X), (len), (stride), (c), (s))
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/* The scaling loop at the end of normalise_residual. ARMv5E only: it wants
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smulwb. See celt/arm/normres_armv5e_asm.S. */
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#define OVERRIDE_NORMRES_SCALE
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void normres_scale_armv5e(celt_norm *X, const int *iy, int N, int g,
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int shift);
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#define NORMRES_SCALE normres_scale_armv5e
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#elif defined(FIXED_POINT) && !defined(OPUS_ARM_NO_BANDS_ASM) \
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&& defined(OPUS_ARM_ASM_ARMV4_ONLY) && (ARM_ARCH == 4)
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#define OVERRIDE_vq_exp_rotation1
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void exp_rotation1_armv4(celt_norm *X, int len, int stride, opus_val16 c,
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opus_val16 s);
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#define exp_rotation1(X, len, stride, c, s) \
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exp_rotation1_armv4((X), (len), (stride), (c), (s))
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#endif
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#endif /* VQ_ARM_H */
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