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c47b2e1be2
Upstream's OPUS_ARM_INLINE_ASM means any ARM with inline assembly, with OPUS_ARM_INLINE_EDSP layered on top for ARMv5E. config.h instead defines exactly one of them per core, so the names read as broader than they are, and code added ARM_ARCH tests beside them to pin the scope down. Renamed to OPUS_ARM_ASM_ARMV4_ONLY and OPUS_ARM_ASM_ARMV5E_AND_LATER throughout celt and silk, upstream files included; README.rockbox records it for the next libopus sync. No code change: opus.elf disassembly and section sizes are identical before and after on ARMv4 (e200v1), ARMv5E (Clip+) and ARMv6 (iPod Nano 4G). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Change-Id: I89932d348dedd76748a1bc7b3f2e7de1c5be49c8
76 lines
3.3 KiB
C
76 lines
3.3 KiB
C
/* Copyright (c) 2025 Xiph.Org Foundation and contributors
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Copyright (c) 2026 Michael Giacomelli
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef MDCT_ARMv5E_H
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#define MDCT_ARMv5E_H
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/* Hand-written inner loops for the backward MDCT, the ARMv5E counterpart of
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arm/mdct_armv4.h. The compiled loops on this architecture already use the
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32x16 multiply; what they miss is the packed halfword operand, the
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multiply-accumulate and the multi-register transfer. See
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celt/arm/mdct_armv5e_asm.S.
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These are bit-exact with the C on this architecture, unlike the ARMv4
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kernels, which are more accurate than theirs.
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Building with OPUS_ARM_NO_MDCT_ASM selects the C loops instead, which is
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how the two are compared. */
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#if defined(OPUS_ARM_ASM_ARMV5E_AND_LATER) && defined(FIXED_POINT) \
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&& (ARM_ARCH >= 5) && !defined(OPUS_ARM_NO_MDCT_ASM)
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#define OVERRIDE_MDCT_PREROT
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#define OVERRIDE_MDCT_POSTROT
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#define OVERRIDE_MDCT_MIRROR
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#define mdct_prerot_opt mdct_prerot_armv5e
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#define mdct_postrot_opt mdct_postrot_armv5e
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#ifdef OPUS_PFA
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#define OVERRIDE_MDCT_POSTROT_PFA
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#define mdct_postrot_pfa_opt mdct_postrot_pfa_armv5e
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void mdct_postrot_pfa_armv5e(const kiss_fft_scalar *S, kiss_fft_scalar *yp0,
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kiss_fft_scalar *yp1, const kiss_twiddle_scalar *t,
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const opus_int16 *pmap, int N4);
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#endif
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#define mdct_mirror_opt mdct_mirror_armv5e
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/* step is a byte stride, so the caller scales by sizeof(kiss_fft_scalar). */
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void mdct_prerot_armv5e(const kiss_fft_scalar *xp1,
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const kiss_fft_scalar *xp2,
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const kiss_twiddle_scalar *t,
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const opus_int16 *bitrev,
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kiss_fft_scalar *yp, int N4, int step);
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void mdct_postrot_armv5e(kiss_fft_scalar *yp0, kiss_fft_scalar *yp1,
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const kiss_twiddle_scalar *t, int N4, int count);
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void mdct_mirror_armv5e(kiss_fft_scalar *xp1, kiss_fft_scalar *yp1,
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const opus_val16 *wp1, const opus_val16 *wp2,
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int count);
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#endif
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#endif /* MDCT_ARMv5E_H */
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