arm: split ARM cache maintenance functions to separate header

Cortex-M processors don't have an MMU, but can still have caches
that need software management, so on those platforms we don't want
to include the MMU related functions.

While here, remove an outdated section of a comment referring to
deprecated cache maintenance functions which no longer exist.

Change-Id: I6f0fe694560bdee25ed7c69a846bf46e3e544cb1

bootloader/gigabeat.c

@@ -44,7 +44,6 @@
 #include "loader_strerror.h"
 #include "rbunicode.h"
 #include "usb.h"
-#include "mmu-arm.h"
 #include "rtc.h"
 #include "version.h"
 

firmware/target/arm/as3525/pcm-as3525.c

@@ -29,6 +29,7 @@
 #include "as3514.h"
 #include "audiohw.h"
 #include "mmu-arm.h"
+#include "cpucache-arm.h"
 #include "pcm-internal.h"
 
 #define MAX_TRANSFER (4*((1<<11)-1)) /* maximum data we can transfer via DMA

firmware/target/arm/as3525/system-target.h

@@ -26,6 +26,7 @@
 
 #include "system-arm.h"
 #include "mmu-arm.h"
+#include "cpucache-arm.h"
 #include "panic.h"
 
 #include "clock-target.h" /* CPUFREQ_* are defined here */

firmware/target/arm/cpucache-arm.h

@@ -0,0 +1,64 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006,2007 by Greg White
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+/*  This file MUST be included in your system-target.h file if you want arm
+ *  cache coherence functions to be called (I.E. during codec load, etc).
+ */
+
+#ifndef CPUCACHE_ARM_H
+#define CPUCACHE_ARM_H
+
+/* Note for the function names
+ *
+ * ARM refers to the cache coherency functions as (in the CPU manuals):
+ *  clean (write-back)
+ *  clean and invalidate (write-back and removing the line from cache)
+ *  invalidate (removing from cache without write-back)
+ *
+ * This names have been proven to cause confusion, therefore we use:
+ *  commit
+ *  commit and discard
+ *  discard
+ */
+
+/* Commits entire DCache */
+void commit_dcache(void);
+
+/* Commit and discard entire DCache, will do writeback */
+void commit_discard_dcache(void);
+
+/* Write DCache back to RAM for the given range and remove cache lines
+ * from DCache afterwards */
+void commit_discard_dcache_range(const void *base, unsigned int size);
+
+/* Write DCache back to RAM for the given range */
+void commit_dcache_range(const void *base, unsigned int size);
+
+/*
+ * Remove cache lines for the given range from DCache
+ * will *NOT* do write back except for buffer edges not on a line boundary
+ */
+void discard_dcache_range(const void *base, unsigned int size);
+
+/* Discards the entire ICache, and commit+discards the entire DCache */
+void commit_discard_idcache(void);
+
+#endif /* CPUCACHE_ARM_H */

firmware/target/arm/imx233/system-target.h

@@ -23,6 +23,7 @@
 
 #include "system-arm.h"
 #include "mmu-arm.h"
+#include "cpucache-arm.h"
 #include "panic.h"
 #include "clkctrl-imx233.h"
 #include "icoll-imx233.h"

firmware/target/arm/imx31/gigabeat-s/system-target.h

@@ -23,6 +23,7 @@
 
 #include "system-arm.h"
 #include "mmu-arm.h"
+#include "cpucache-arm.h"
 
 /* High enough for most tasks but low enough for reduced voltage */
 #define CPUFREQ_DEFAULT     264000000

firmware/target/arm/mmu-arm.h

@@ -19,10 +19,6 @@
  *
  ****************************************************************************/
 
-/*  This file MUST be included in your system-target.h file if you want arm
- *  cache coherence functions to be called (I.E. during codec load, etc).   
- */
-
 #ifndef MMU_ARM_H
 #define MMU_ARM_H
 
@@ -35,42 +31,4 @@ void ttb_init(void);
 void enable_mmu(void);
 void map_section(unsigned int pa, unsigned int va, int mb, int flags);
 
-/* Note for the function names
- *
- * ARM refers to the cache coherency functions as (in the CPU manuals):
- *  clean (write-back)
- *  clean and invalidate (write-back and removing the line from cache)
- *  invalidate (removing from cache without write-back)
- *
- * The deprecated functions below don't follow the above (which is why
- * they're deprecated).
- *
- * This names have been proven to cause confusion, therefore we use:
- *  commit
- *  commit and discard
- *  discard
- */
-
-/* Commits entire DCache */
-void commit_dcache(void);
-
-/* Commit and discard entire DCache, will do writeback */
-void commit_discard_dcache(void);
-
-/* Write DCache back to RAM for the given range and remove cache lines
- * from DCache afterwards */
-void commit_discard_dcache_range(const void *base, unsigned int size);
-
-/* Write DCache back to RAM for the given range */
-void commit_dcache_range(const void *base, unsigned int size);
-
-/*
- * Remove cache lines for the given range from DCache
- * will *NOT* do write back except for buffer edges not on a line boundary
- */
-void discard_dcache_range(const void *base, unsigned int size);
-
-/* Discards the entire ICache, and commit+discards the entire DCache */
-void commit_discard_idcache(void);
-
 #endif /* MMU_ARM_H */

firmware/target/arm/s3c2440/dma-s3c2440.c

@@ -23,7 +23,6 @@
 #include "config.h"
 #include "panic.h"
 #include "system.h"
-#include "mmu-arm.h"
 #include "s3c2440.h"
 #include "dma-target.h"
 #include "system-target.h"

firmware/target/arm/s3c2440/system-s3c2440.c

@@ -21,7 +21,6 @@
 #include "kernel.h"
 #include "system.h"
 #include "panic.h"
-#include "mmu-arm.h"
 #include "cpu.h"
 #include "gcc_extensions.h"
 

firmware/target/arm/s3c2440/system-target.h

@@ -23,6 +23,7 @@
 
 #include "system-arm.h"
 #include "mmu-arm.h"
+#include "cpucache-arm.h"
 
 /* NB: These values must match the register settings in s3c2440/crt0.S */
 

firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c

@@ -29,6 +29,7 @@
 #include "nand-target.h"
 #include <pmu-target.h>
 #include <mmu-arm.h>
+#include <cpucache-arm.h>
 #include <string.h>
 #include "led.h"
 #include "storage.h"

firmware/target/arm/s5l8700/pcm-s5l8700.c

@@ -31,6 +31,7 @@
 #include "pcm_sampr.h"
 #include "dma-target.h"
 #include "mmu-arm.h"
+#include "cpucache-arm.h"
 
 /*  Driver for the IIS/PCM part of the s5l8700 using DMA
 

firmware/target/arm/s5l8700/system-target.h

@@ -23,6 +23,7 @@
 
 #include "system-arm.h"
 #include "mmu-arm.h"
+#include "cpucache-arm.h"
 
 #define CPUFREQ_SLEEP      32768
 #define CPUFREQ_MAX     (1843200 * 4 * 26 / 1) /* 191692800 Hz */

firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c

@@ -27,7 +27,6 @@
 #include "string.h"
 #include "power.h"
 #include "panic.h"
-#include "mmu-arm.h"
 #include "mmcdefs-target.h"
 #include "s5l87xx.h"
 #include "led.h"

firmware/target/arm/s5l8702/pcm-s5l8702.c

@@ -29,7 +29,6 @@
 #include "pcm.h"
 #include "pcm-internal.h"
 #include "pcm_sampr.h"
-#include "mmu-arm.h"
 #include "pcm-target.h"
 #include "dma-s5l8702.h"
 

firmware/target/arm/s5l8702/system-target.h

@@ -23,6 +23,7 @@
 
 #include "system-arm.h"
 #include "mmu-arm.h"
+#include "cpucache-arm.h"
 
 #define CPUFREQ_SLEEP   32768
 

firmware/target/arm/tcc780x/system-target.h

@@ -23,6 +23,7 @@
 
 #include "system-arm.h"
 #include "mmu-arm.h"
+#include "cpucache-arm.h"
 
 #define CPUFREQ_DEFAULT 32000000
 #define CPUFREQ_NORMAL  48000000

firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c

@@ -29,7 +29,6 @@
 #include "kernel.h"
 #include "system.h"
 #include "string-extra.h" /* memset16() */
-#include "mmu-arm.h"
 #include "system-target.h"
 #include "lcd.h"
 #include "lcd-target.h"

firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c

@@ -27,7 +27,6 @@
 #include "file.h"
 #include "dsp-target.h"
 #include "dsp/ipc.h"
-#include "mmu-arm.h"
 #include "pcm-internal.h"
 
 /* This is global to save some latency when pcm_play_dma_get_peak_buffer is 

firmware/target/arm/tms320dm320/sansa-connect/pcm-sansaconnect.c

@@ -27,7 +27,6 @@
 #include "file.h"
 #include "dsp-target.h"
 #include "dsp/ipc.h"
-#include "mmu-arm.h"
 #include "pcm-internal.h"
 #include "dma-target.h"
 

firmware/target/arm/tms320dm320/system-dm320.c

@@ -20,7 +20,6 @@
  *
  ****************************************************************************/
 #include "cpu.h"
-#include "mmu-arm.h"
 #include "kernel.h"
 #include "system.h"
 #include "panic.h"

firmware/target/arm/tms320dm320/system-target.h

@@ -23,6 +23,7 @@
 
 #include "system-arm.h"
 #include "mmu-arm.h"
+#include "cpucache-arm.h"
 
 #ifdef SANSA_CONNECT
 #define CPUFREQ_DEFAULT  74250000