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arm: add ARM Cortex-M register definitions
Change-Id: Ifb90606d2b6c94c4f91798a41415c895e2888520
This commit is contained in:
Aidan MacDonald
Solomon Peachy
parent
96f5cb728c
commit
bfa76dca9a
6 changed files with 724 additions and 0 deletions
74
firmware/target/arm/cortex-m/cache.h
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74
firmware/target/arm/cortex-m/cache.h
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@ -0,0 +1,74 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* cortex_m7 version: 1.0
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* cortex_m7 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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||||
* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __ARM_CORTEX_M_CACHE_H__
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#define __ARM_CORTEX_M_CACHE_H__
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#include "macro.h"
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#define REG_CACHE_ICIALLU cm_reg(CACHE_ICIALLU)
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#define CMA_CACHE_ICIALLU (0xe000e000 + 0xf50)
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#define CMT_CACHE_ICIALLU CMIO_32_RW
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#define CMN_CACHE_ICIALLU CACHE_ICIALLU
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#define REG_CACHE_ICIMVAU cm_reg(CACHE_ICIMVAU)
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#define CMA_CACHE_ICIMVAU (0xe000e000 + 0xf58)
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#define CMT_CACHE_ICIMVAU CMIO_32_RW
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#define CMN_CACHE_ICIMVAU CACHE_ICIMVAU
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#define REG_CACHE_DCIMVAC cm_reg(CACHE_DCIMVAC)
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#define CMA_CACHE_DCIMVAC (0xe000e000 + 0xf5c)
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#define CMT_CACHE_DCIMVAC CMIO_32_RW
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#define CMN_CACHE_DCIMVAC CACHE_DCIMVAC
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#define REG_CACHE_DCISW cm_reg(CACHE_DCISW)
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#define CMA_CACHE_DCISW (0xe000e000 + 0xf60)
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#define CMT_CACHE_DCISW CMIO_32_RW
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#define CMN_CACHE_DCISW CACHE_DCISW
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#define REG_CACHE_DCCMVAU cm_reg(CACHE_DCCMVAU)
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#define CMA_CACHE_DCCMVAU (0xe000e000 + 0xf64)
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#define CMT_CACHE_DCCMVAU CMIO_32_RW
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#define CMN_CACHE_DCCMVAU CACHE_DCCMVAU
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#define REG_CACHE_DCCMVAC cm_reg(CACHE_DCCMVAC)
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#define CMA_CACHE_DCCMVAC (0xe000e000 + 0xf68)
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#define CMT_CACHE_DCCMVAC CMIO_32_RW
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#define CMN_CACHE_DCCMVAC CACHE_DCCMVAC
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#define REG_CACHE_DCCSW cm_reg(CACHE_DCCSW)
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#define CMA_CACHE_DCCSW (0xe000e000 + 0xf6c)
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#define CMT_CACHE_DCCSW CMIO_32_RW
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#define CMN_CACHE_DCCSW CACHE_DCCSW
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#define REG_CACHE_DCCIMVAC cm_reg(CACHE_DCCIMVAC)
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#define CMA_CACHE_DCCIMVAC (0xe000e000 + 0xf70)
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#define CMT_CACHE_DCCIMVAC CMIO_32_RW
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#define CMN_CACHE_DCCIMVAC CACHE_DCCIMVAC
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#define REG_CACHE_DCCISW cm_reg(CACHE_DCCISW)
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#define CMA_CACHE_DCCISW (0xe000e000 + 0xf74)
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#define CMT_CACHE_DCCISW CMIO_32_RW
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#define CMN_CACHE_DCCISW CACHE_DCCISW
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#endif /* __ARM_CORTEX_M_CACHE_H__*/
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301
firmware/target/arm/cortex-m/macro.h
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301
firmware/target/arm/cortex-m/macro.h
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@ -0,0 +1,301 @@
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* This file was automatically generated by headergen, DO NOT EDIT it.
|
||||
* headergen version: 3.0.0
|
||||
*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __ARM_CORTEX_M_MACRO_H__
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#define __ARM_CORTEX_M_MACRO_H__
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#include <stdint.h>
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#define __VAR_OR1(prefix, suffix) \
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(prefix##suffix)
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#define __VAR_OR2(pre, s1, s2) \
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(__VAR_OR1(pre, s1) | __VAR_OR1(pre, s2))
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#define __VAR_OR3(pre, s1, s2, s3) \
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(__VAR_OR1(pre, s1) | __VAR_OR2(pre, s2, s3))
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#define __VAR_OR4(pre, s1, s2, s3, s4) \
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(__VAR_OR2(pre, s1, s2) | __VAR_OR2(pre, s3, s4))
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#define __VAR_OR5(pre, s1, s2, s3, s4, s5) \
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(__VAR_OR2(pre, s1, s2) | __VAR_OR3(pre, s3, s4, s5))
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#define __VAR_OR6(pre, s1, s2, s3, s4, s5, s6) \
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(__VAR_OR3(pre, s1, s2, s3) | __VAR_OR3(pre, s4, s5, s6))
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#define __VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) \
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(__VAR_OR3(pre, s1, s2, s3) | __VAR_OR4(pre, s4, s5, s6, s7))
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#define __VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) \
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(__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR4(pre, s5, s6, s7, s8))
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#define __VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) \
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(__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR5(pre, s5, s6, s7, s8, s9))
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#define __VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) \
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(__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR5(pre, s6, s7, s8, s9, s10))
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#define __VAR_OR11(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11) \
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(__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR6(pre, s6, s7, s8, s9, s10, s11))
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#define __VAR_OR12(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12) \
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(__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR6(pre, s7, s8, s9, s10, s11, s12))
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#define __VAR_OR13(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13) \
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(__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR7(pre, s7, s8, s9, s10, s11, s12, s13))
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#define __VAR_OR14(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14) \
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(__VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) | __VAR_OR7(pre, s8, s9, s10, s11, s12, s13, s14))
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#define __VAR_OR15(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15) \
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(__VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) | __VAR_OR8(pre, s8, s9, s10, s11, s12, s13, s14, s15))
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#define __VAR_OR16(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16) \
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(__VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) | __VAR_OR8(pre, s9, s10, s11, s12, s13, s14, s15, s16))
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#define __VAR_OR17(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17) \
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(__VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) | __VAR_OR9(pre, s9, s10, s11, s12, s13, s14, s15, s16, s17))
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#define __VAR_OR18(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18) \
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(__VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) | __VAR_OR9(pre, s10, s11, s12, s13, s14, s15, s16, s17, s18))
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#define __VAR_OR19(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19) \
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(__VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) | __VAR_OR10(pre, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19))
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#define __VAR_OR20(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20) \
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(__VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) | __VAR_OR10(pre, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20))
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#define __VAR_NARGS(...) __VAR_NARGS_(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)
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#define __VAR_NARGS_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, N, ...) N
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#define __VAR_EXPAND(macro, prefix, ...) __VAR_EXPAND_(macro, __VAR_NARGS(__VA_ARGS__), prefix, __VA_ARGS__)
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#define __VAR_EXPAND_(macro, cnt, prefix, ...) __VAR_EXPAND__(macro, cnt, prefix, __VA_ARGS__)
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#define __VAR_EXPAND__(macro, cnt, prefix, ...) __VAR_EXPAND___(macro##cnt, prefix, __VA_ARGS__)
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#define __VAR_EXPAND___(macro, prefix, ...) macro(prefix, __VA_ARGS__)
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#define CMIO_8_RO(op, name, ...) CMIO_8_RO_##op(name, __VA_ARGS__)
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#define CMIO_8_RO_RD(name, ...) (*(const volatile uint8_t *)(CMA_##name))
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#define CMIO_8_RO_WR(name, val) _Static_assert(0, #name " is read-only")
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#define CMIO_8_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
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#define CMIO_8_RO_VAR(name, ...) (*(const volatile uint8_t *)(CMA_##name))
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#define CMIO_16_RO(op, name, ...) CMIO_16_RO_##op(name, __VA_ARGS__)
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#define CMIO_16_RO_RD(name, ...) (*(const volatile uint16_t *)(CMA_##name))
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#define CMIO_16_RO_WR(name, val) _Static_assert(0, #name " is read-only")
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#define CMIO_16_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
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#define CMIO_16_RO_VAR(name, ...) (*(const volatile uint16_t *)(CMA_##name))
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#define CMIO_32_RO(op, name, ...) CMIO_32_RO_##op(name, __VA_ARGS__)
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#define CMIO_32_RO_RD(name, ...) (*(const volatile uint32_t *)(CMA_##name))
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#define CMIO_32_RO_WR(name, val) _Static_assert(0, #name " is read-only")
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#define CMIO_32_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
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#define CMIO_32_RO_VAR(name, ...) (*(const volatile uint32_t *)(CMA_##name))
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#define CMIO_8_RW(op, name, ...) CMIO_8_RW_##op(name, __VA_ARGS__)
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#define CMIO_8_RW_RD(name, ...) (*(volatile uint8_t *)(CMA_##name))
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#define CMIO_8_RW_WR(name, val) (*(volatile uint8_t *)(CMA_##name)) = (val)
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#define CMIO_8_RW_RMW(name, vand, vor) CMIO_8_RW_WR(name, (CMIO_8_RW_RD(name) & (vand)) | (vor))
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#define CMIO_8_RW_VAR(name, ...) (*(volatile uint8_t *)(CMA_##name))
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#define CMIO_16_RW(op, name, ...) CMIO_16_RW_##op(name, __VA_ARGS__)
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#define CMIO_16_RW_RD(name, ...) (*(volatile uint16_t *)(CMA_##name))
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#define CMIO_16_RW_WR(name, val) (*(volatile uint16_t *)(CMA_##name)) = (val)
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#define CMIO_16_RW_RMW(name, vand, vor) CMIO_16_RW_WR(name, (CMIO_16_RW_RD(name) & (vand)) | (vor))
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#define CMIO_16_RW_VAR(name, ...) (*(volatile uint16_t *)(CMA_##name))
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#define CMIO_32_RW(op, name, ...) CMIO_32_RW_##op(name, __VA_ARGS__)
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#define CMIO_32_RW_RD(name, ...) (*(volatile uint32_t *)(CMA_##name))
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#define CMIO_32_RW_WR(name, val) (*(volatile uint32_t *)(CMA_##name)) = (val)
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#define CMIO_32_RW_RMW(name, vand, vor) CMIO_32_RW_WR(name, (CMIO_32_RW_RD(name) & (vand)) | (vor))
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#define CMIO_32_RW_VAR(name, ...) (*(volatile uint32_t *)(CMA_##name))
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#define CMIO_8_WO(op, name, ...) CMIO_8_WO_##op(name, __VA_ARGS__)
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#define CMIO_8_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
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#define CMIO_8_WO_WR(name, val) (*(volatile uint8_t *)(CMA_##name)) = (val)
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#define CMIO_8_WO_RMW(name, vand, vor) CMIO_8_WO_WR(name, vor)
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#define CMIO_8_WO_VAR(name, ...) (*(volatile uint8_t *)(CMA_##name))
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#define CMIO_16_WO(op, name, ...) CMIO_16_WO_##op(name, __VA_ARGS__)
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#define CMIO_16_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
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#define CMIO_16_WO_WR(name, val) (*(volatile uint16_t *)(CMA_##name)) = (val)
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#define CMIO_16_WO_RMW(name, vand, vor) CMIO_16_WO_WR(name, vor)
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#define CMIO_16_WO_VAR(name, ...) (*(volatile uint16_t *)(CMA_##name))
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#define CMIO_32_WO(op, name, ...) CMIO_32_WO_##op(name, __VA_ARGS__)
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#define CMIO_32_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
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#define CMIO_32_WO_WR(name, val) (*(volatile uint32_t *)(CMA_##name)) = (val)
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#define CMIO_32_WO_RMW(name, vand, vor) CMIO_32_WO_WR(name, vor)
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#define CMIO_32_WO_VAR(name, ...) (*(volatile uint32_t *)(CMA_##name))
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/** cm_orf
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*
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* usage: cm_orf(register, f1(v1), f2(v2), ...)
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*
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* effect: expands to the register value where each field fi has value vi.
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* Informally: reg_f1(v1) | reg_f2(v2) | ...
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* note: enumerated values for fields can be obtained by using the syntax:
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* f1_V(name)
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*
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* example: cm_orf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
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*/
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#define cm_orf(reg, ...) __VAR_EXPAND(__VAR_OR, BF_##reg##_, __VA_ARGS__)
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/** __cm_orfm
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*
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* usage: __cm_orfm(register, f1(v1), f2(v2), ...)
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*
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* effect: expands to the register value where each field fi has maximum value (vi is ignored).
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* note: internal usage
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*
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* example: __cm_orfm(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
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*/
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#define __cm_orfm(reg, ...) __VAR_EXPAND(__VAR_OR, BFM_##reg##_, __VA_ARGS__)
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/** cm_orm
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*
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* usage: cm_orm(register, f1, f2, ...)
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*
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* effect: expands to the register value where each field fi is set to its maximum value.
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* Informally: reg_f1_mask | reg_f2_mask | ...
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*
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* example: cm_orm(ICOLL_CTRL, SFTRST, CLKGATE)
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*/
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#define cm_orm(reg, ...) __VAR_EXPAND(__VAR_OR, BM_##reg##_, __VA_ARGS__)
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/** cm_vreadf
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*
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* usage: cm_vreadf(value, register, field)
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*
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* effect: given a register value, return the value of a particular field
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* note: this macro does NOT read any register
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*
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* example: cm_vreadf(0xc0000000, ICOLL_CTRL, SFTRST)
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* cm_vreadf(0x46ff, ICOLL_ENABLE, CPU0_PRIO)
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*/
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#define cm_vreadf(val, name, field) (((val) & BM_##name##_##field) >> BP_##name##_##field)
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/** cm_vwritef
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*
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* usage: cm_vwritef(var, register, f1(v1), f2(v2), ...)
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*
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* effect: change the variable value so that field fi has value vi
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* note: this macro will perform a read-modify-write
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*
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* example: cm_vwritef(var, ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
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* cm_vwritef(var, ICOLL_ENABLE, CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
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*/
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#define cm_vwritef(var, name, ...) (var) = cm_orf(name, __VA_ARGS__) | (~__cm_orfm(name, __VA_ARGS__) & (var))
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/** cm_read
|
||||
*
|
||||
* usage: cm_read(register)
|
||||
*
|
||||
* effect: read the register and return its value
|
||||
* note: register must be fully qualified if indexed
|
||||
*
|
||||
* example: cm_read(ICOLL_STATUS)
|
||||
* cm_read(ICOLL_ENABLE(42))
|
||||
*/
|
||||
#define cm_read(name) CMT_##name(RD, name)
|
||||
|
||||
/** cm_readf
|
||||
*
|
||||
* usage: cm_readf(register, field)
|
||||
*
|
||||
* effect: read a register and return the value of a particular field
|
||||
* note: register must be fully qualified if indexed
|
||||
*
|
||||
* example: cm_readf(ICOLL_CTRL, SFTRST)
|
||||
* cm_readf(ICOLL_ENABLE(3), CPU0_PRIO)
|
||||
*/
|
||||
#define cm_readf(name, field) cm_readf_(cm_read(name), CMN_##name, field)
|
||||
#define cm_readf_(...) cm_vreadf(__VA_ARGS__)
|
||||
|
||||
/** cm_write
|
||||
*
|
||||
* usage: cm_write(register, value)
|
||||
*
|
||||
* effect: write a register
|
||||
* note: register must be fully qualified if indexed
|
||||
*
|
||||
* example: cm_write(ICOLL_CTRL, 0x42)
|
||||
* cm_write(ICOLL_ENABLE_SET(3), 0x37)
|
||||
*/
|
||||
#define cm_write(name, val) CMT_##name(WR, name, val)
|
||||
|
||||
/** cm_writef
|
||||
*
|
||||
* usage: cm_writef(register, f1(v1), f2(v2), ...)
|
||||
*
|
||||
* effect: change the register value so that field fi has value vi
|
||||
* note: register must be fully qualified if indexed
|
||||
* note: this macro may perform a read-modify-write
|
||||
*
|
||||
* example: cm_writef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
|
||||
* cm_writef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
|
||||
*/
|
||||
#define cm_writef(name, ...) cm_writef_(name, CMN_##name, __VA_ARGS__)
|
||||
#define cm_writef_(name, name2, ...) CMT_##name(RMW, name, ~__cm_orfm(name2, __VA_ARGS__), cm_orf(name2, __VA_ARGS__))
|
||||
|
||||
/** cm_overwritef
|
||||
*
|
||||
* usage: cm_overwritef(register, f1(v1), f2(v2), ...)
|
||||
*
|
||||
* effect: change the register value so that field fi has value vi and other fields have value zero
|
||||
* thus this macro is equivalent to:
|
||||
* cm_write(register, cm_orf(register, f1(v1), ...))
|
||||
* note: register must be fully qualified if indexed
|
||||
* note: this macro will overwrite the register (it is NOT a read-modify-write)
|
||||
*
|
||||
* example: cm_overwritef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
|
||||
* cm_overwritef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
|
||||
*/
|
||||
#define cm_overwritef(name, ...) cm_overwritef_(name, CMN_##name, __VA_ARGS__)
|
||||
#define cm_overwritef_(name, name2, ...) CMT_##name(WR, name, cm_orf(name2, __VA_ARGS__))
|
||||
|
||||
/** cm_setf
|
||||
*
|
||||
* usage: cm_setf(register, f1, f2, ...)
|
||||
*
|
||||
* effect: change the register value so that field fi has maximum value
|
||||
* note: this macro will perform a read-modify-write
|
||||
* note: register must be fully qualified if indexed
|
||||
*
|
||||
* example: cm_setf(ICOLL_CTRL, SFTRST, CLKGATE)
|
||||
* cm_setf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
|
||||
*/
|
||||
#define cm_setf(name, ...) cm_setf_(name, CMN_##name, __VA_ARGS__)
|
||||
#define cm_setf_(name, name2, ...) CMT_##name(RMW, name, ~0,cm_orm(name2, __VA_ARGS__))
|
||||
|
||||
/** cm_clrf
|
||||
*
|
||||
* usage: cm_clrf(register, f1, f2, ...)
|
||||
*
|
||||
* effect: change the register value so that field fi has value zero
|
||||
* note: this macro will perform a read-modify-write
|
||||
* note: register must be fully qualified if indexed
|
||||
*
|
||||
* example: cm_clrf(ICOLL_CTRL, SFTRST, CLKGATE)
|
||||
* cm_clrf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
|
||||
*/
|
||||
#define cm_clrf(name, ...) cm_clrf_(name, CMN_##name, __VA_ARGS__)
|
||||
#define cm_clrf_(name, name2, ...) CMT_##name(RMW, name, ~cm_orm(name2, __VA_ARGS__), 0)
|
||||
|
||||
/** cm_reg
|
||||
*
|
||||
* usage: cm_reg(register)
|
||||
*
|
||||
* effect: return a variable-like expression that can be read/written
|
||||
* note: register must be fully qualified if indexed
|
||||
* note: read-only registers will yield a constant expression
|
||||
*
|
||||
* example: unsigned x = cm_reg(ICOLL_STATUS)
|
||||
* unsigned x = cm_reg(ICOLL_ENABLE(42))
|
||||
* cm_reg(ICOLL_ENABLE(42)) = 64
|
||||
*/
|
||||
#define cm_reg(name) CMT_##name(VAR, name)
|
||||
|
||||
|
||||
#endif /* __ARM_CORTEX_M_MACRO_H__*/
|
||||
70
firmware/target/arm/cortex-m/nvic.h
Normal file
70
firmware/target/arm/cortex-m/nvic.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* This file was automatically generated by headergen, DO NOT EDIT it.
|
||||
* headergen version: 3.0.0
|
||||
* cortex_m7 version: 1.0
|
||||
* cortex_m7 authors: Aidan MacDonald
|
||||
*
|
||||
* Copyright (C) 2015 by the authors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef __ARM_CORTEX_M_NVIC_H__
|
||||
#define __ARM_CORTEX_M_NVIC_H__
|
||||
|
||||
#include "macro.h"
|
||||
|
||||
#define REG_NVIC_ISER(_n1) cm_reg(NVIC_ISER(_n1))
|
||||
#define CMA_NVIC_ISER(_n1) (0xe000e000 + 0x100 + (_n1) * 0x4)
|
||||
#define CMT_NVIC_ISER(_n1) CMIO_32_RW
|
||||
#define CMN_NVIC_ISER(_n1) NVIC_ISER
|
||||
|
||||
#define REG_NVIC_ICER(_n1) cm_reg(NVIC_ICER(_n1))
|
||||
#define CMA_NVIC_ICER(_n1) (0xe000e000 + 0x180 + (_n1) * 0x4)
|
||||
#define CMT_NVIC_ICER(_n1) CMIO_32_RW
|
||||
#define CMN_NVIC_ICER(_n1) NVIC_ICER
|
||||
|
||||
#define REG_NVIC_ISPR(_n1) cm_reg(NVIC_ISPR(_n1))
|
||||
#define CMA_NVIC_ISPR(_n1) (0xe000e000 + 0x200 + (_n1) * 0x4)
|
||||
#define CMT_NVIC_ISPR(_n1) CMIO_32_RW
|
||||
#define CMN_NVIC_ISPR(_n1) NVIC_ISPR
|
||||
|
||||
#define REG_NVIC_ICPR(_n1) cm_reg(NVIC_ICPR(_n1))
|
||||
#define CMA_NVIC_ICPR(_n1) (0xe000e000 + 0x280 + (_n1) * 0x4)
|
||||
#define CMT_NVIC_ICPR(_n1) CMIO_32_RW
|
||||
#define CMN_NVIC_ICPR(_n1) NVIC_ICPR
|
||||
|
||||
#define REG_NVIC_IABR(_n1) cm_reg(NVIC_IABR(_n1))
|
||||
#define CMA_NVIC_IABR(_n1) (0xe000e000 + 0x300 + (_n1) * 0x4)
|
||||
#define CMT_NVIC_IABR(_n1) CMIO_32_RW
|
||||
#define CMN_NVIC_IABR(_n1) NVIC_IABR
|
||||
|
||||
#define REG_NVIC_IPR(_n1) cm_reg(NVIC_IPR(_n1))
|
||||
#define CMA_NVIC_IPR(_n1) (0xe000e000 + 0x400 + (_n1) * 0x4)
|
||||
#define CMT_NVIC_IPR(_n1) CMIO_32_RW
|
||||
#define CMN_NVIC_IPR(_n1) NVIC_IPR
|
||||
|
||||
#define REG_NVIC_STIR cm_reg(NVIC_STIR)
|
||||
#define CMA_NVIC_STIR (0xe000e000 + 0xf00)
|
||||
#define CMT_NVIC_STIR CMIO_32_RW
|
||||
#define CMN_NVIC_STIR NVIC_STIR
|
||||
#define BP_NVIC_STIR_INTID 0
|
||||
#define BM_NVIC_STIR_INTID 0x1ff
|
||||
#define BF_NVIC_STIR_INTID(v) (((v) & 0x1ff) << 0)
|
||||
#define BFM_NVIC_STIR_INTID(v) BM_NVIC_STIR_INTID
|
||||
#define BF_NVIC_STIR_INTID_V(e) BF_NVIC_STIR_INTID(BV_NVIC_STIR_INTID__##e)
|
||||
#define BFM_NVIC_STIR_INTID_V(v) BM_NVIC_STIR_INTID
|
||||
|
||||
#endif /* __ARM_CORTEX_M_NVIC_H__*/
|
||||
93
firmware/target/arm/cortex-m/scb.h
Normal file
93
firmware/target/arm/cortex-m/scb.h
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* This file was automatically generated by headergen, DO NOT EDIT it.
|
||||
* headergen version: 3.0.0
|
||||
* cortex_m7 version: 1.0
|
||||
* cortex_m7 authors: Aidan MacDonald
|
||||
*
|
||||
* Copyright (C) 2015 by the authors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef __ARM_CORTEX_M_SCB_H__
|
||||
#define __ARM_CORTEX_M_SCB_H__
|
||||
|
||||
#include "macro.h"
|
||||
|
||||
#define REG_SCB_VTOR cm_reg(SCB_VTOR)
|
||||
#define CMA_SCB_VTOR (0xe000e000 + 0xd08)
|
||||
#define CMT_SCB_VTOR CMIO_32_RW
|
||||
#define CMN_SCB_VTOR SCB_VTOR
|
||||
|
||||
#define REG_SCB_CCR cm_reg(SCB_CCR)
|
||||
#define CMA_SCB_CCR (0xe000e000 + 0xd14)
|
||||
#define CMT_SCB_CCR CMIO_32_RW
|
||||
#define CMN_SCB_CCR SCB_CCR
|
||||
#define BP_SCB_CCR_BP 18
|
||||
#define BM_SCB_CCR_BP 0x40000
|
||||
#define BF_SCB_CCR_BP(v) (((v) & 0x1) << 18)
|
||||
#define BFM_SCB_CCR_BP(v) BM_SCB_CCR_BP
|
||||
#define BF_SCB_CCR_BP_V(e) BF_SCB_CCR_BP(BV_SCB_CCR_BP__##e)
|
||||
#define BFM_SCB_CCR_BP_V(v) BM_SCB_CCR_BP
|
||||
#define BP_SCB_CCR_IC 17
|
||||
#define BM_SCB_CCR_IC 0x20000
|
||||
#define BF_SCB_CCR_IC(v) (((v) & 0x1) << 17)
|
||||
#define BFM_SCB_CCR_IC(v) BM_SCB_CCR_IC
|
||||
#define BF_SCB_CCR_IC_V(e) BF_SCB_CCR_IC(BV_SCB_CCR_IC__##e)
|
||||
#define BFM_SCB_CCR_IC_V(v) BM_SCB_CCR_IC
|
||||
#define BP_SCB_CCR_DC 16
|
||||
#define BM_SCB_CCR_DC 0x10000
|
||||
#define BF_SCB_CCR_DC(v) (((v) & 0x1) << 16)
|
||||
#define BFM_SCB_CCR_DC(v) BM_SCB_CCR_DC
|
||||
#define BF_SCB_CCR_DC_V(e) BF_SCB_CCR_DC(BV_SCB_CCR_DC__##e)
|
||||
#define BFM_SCB_CCR_DC_V(v) BM_SCB_CCR_DC
|
||||
#define BP_SCB_CCR_STKALIGN 9
|
||||
#define BM_SCB_CCR_STKALIGN 0x200
|
||||
#define BF_SCB_CCR_STKALIGN(v) (((v) & 0x1) << 9)
|
||||
#define BFM_SCB_CCR_STKALIGN(v) BM_SCB_CCR_STKALIGN
|
||||
#define BF_SCB_CCR_STKALIGN_V(e) BF_SCB_CCR_STKALIGN(BV_SCB_CCR_STKALIGN__##e)
|
||||
#define BFM_SCB_CCR_STKALIGN_V(v) BM_SCB_CCR_STKALIGN
|
||||
#define BP_SCB_CCR_BFHFNMIGN 8
|
||||
#define BM_SCB_CCR_BFHFNMIGN 0x100
|
||||
#define BF_SCB_CCR_BFHFNMIGN(v) (((v) & 0x1) << 8)
|
||||
#define BFM_SCB_CCR_BFHFNMIGN(v) BM_SCB_CCR_BFHFNMIGN
|
||||
#define BF_SCB_CCR_BFHFNMIGN_V(e) BF_SCB_CCR_BFHFNMIGN(BV_SCB_CCR_BFHFNMIGN__##e)
|
||||
#define BFM_SCB_CCR_BFHFNMIGN_V(v) BM_SCB_CCR_BFHFNMIGN
|
||||
#define BP_SCB_CCR_DIV_0_TRP 4
|
||||
#define BM_SCB_CCR_DIV_0_TRP 0x10
|
||||
#define BF_SCB_CCR_DIV_0_TRP(v) (((v) & 0x1) << 4)
|
||||
#define BFM_SCB_CCR_DIV_0_TRP(v) BM_SCB_CCR_DIV_0_TRP
|
||||
#define BF_SCB_CCR_DIV_0_TRP_V(e) BF_SCB_CCR_DIV_0_TRP(BV_SCB_CCR_DIV_0_TRP__##e)
|
||||
#define BFM_SCB_CCR_DIV_0_TRP_V(v) BM_SCB_CCR_DIV_0_TRP
|
||||
#define BP_SCB_CCR_UNALIGN_TRP 3
|
||||
#define BM_SCB_CCR_UNALIGN_TRP 0x8
|
||||
#define BF_SCB_CCR_UNALIGN_TRP(v) (((v) & 0x1) << 3)
|
||||
#define BFM_SCB_CCR_UNALIGN_TRP(v) BM_SCB_CCR_UNALIGN_TRP
|
||||
#define BF_SCB_CCR_UNALIGN_TRP_V(e) BF_SCB_CCR_UNALIGN_TRP(BV_SCB_CCR_UNALIGN_TRP__##e)
|
||||
#define BFM_SCB_CCR_UNALIGN_TRP_V(v) BM_SCB_CCR_UNALIGN_TRP
|
||||
#define BP_SCB_CCR_USERETMPEND 1
|
||||
#define BM_SCB_CCR_USERETMPEND 0x2
|
||||
#define BF_SCB_CCR_USERETMPEND(v) (((v) & 0x1) << 1)
|
||||
#define BFM_SCB_CCR_USERETMPEND(v) BM_SCB_CCR_USERETMPEND
|
||||
#define BF_SCB_CCR_USERETMPEND_V(e) BF_SCB_CCR_USERETMPEND(BV_SCB_CCR_USERETMPEND__##e)
|
||||
#define BFM_SCB_CCR_USERETMPEND_V(v) BM_SCB_CCR_USERETMPEND
|
||||
#define BP_SCB_CCR_NONBASETHRDENA 0
|
||||
#define BM_SCB_CCR_NONBASETHRDENA 0x1
|
||||
#define BF_SCB_CCR_NONBASETHRDENA(v) (((v) & 0x1) << 0)
|
||||
#define BFM_SCB_CCR_NONBASETHRDENA(v) BM_SCB_CCR_NONBASETHRDENA
|
||||
#define BF_SCB_CCR_NONBASETHRDENA_V(e) BF_SCB_CCR_NONBASETHRDENA(BV_SCB_CCR_NONBASETHRDENA__##e)
|
||||
#define BFM_SCB_CCR_NONBASETHRDENA_V(v) BM_SCB_CCR_NONBASETHRDENA
|
||||
|
||||
#endif /* __ARM_CORTEX_M_SCB_H__*/
|
||||
105
firmware/target/arm/cortex-m/systick.h
Normal file
105
firmware/target/arm/cortex-m/systick.h
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
/***************************************************************************
|
||||
* __________ __ ___.
|
||||
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
||||
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
||||
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
||||
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
||||
* \/ \/ \/ \/ \/
|
||||
* This file was automatically generated by headergen, DO NOT EDIT it.
|
||||
* headergen version: 3.0.0
|
||||
* cortex_m7 version: 1.0
|
||||
* cortex_m7 authors: Aidan MacDonald
|
||||
*
|
||||
* Copyright (C) 2015 by the authors
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
||||
* KIND, either express or implied.
|
||||
*
|
||||
****************************************************************************/
|
||||
#ifndef __ARM_CORTEX_M_SYSTICK_H__
|
||||
#define __ARM_CORTEX_M_SYSTICK_H__
|
||||
|
||||
#include "macro.h"
|
||||
|
||||
#define REG_SYSTICK_CSR cm_reg(SYSTICK_CSR)
|
||||
#define CMA_SYSTICK_CSR (0xe000e000 + 0x10)
|
||||
#define CMT_SYSTICK_CSR CMIO_32_RW
|
||||
#define CMN_SYSTICK_CSR SYSTICK_CSR
|
||||
#define BP_SYSTICK_CSR_COUNTFLAG 16
|
||||
#define BM_SYSTICK_CSR_COUNTFLAG 0x10000
|
||||
#define BF_SYSTICK_CSR_COUNTFLAG(v) (((v) & 0x1) << 16)
|
||||
#define BFM_SYSTICK_CSR_COUNTFLAG(v) BM_SYSTICK_CSR_COUNTFLAG
|
||||
#define BF_SYSTICK_CSR_COUNTFLAG_V(e) BF_SYSTICK_CSR_COUNTFLAG(BV_SYSTICK_CSR_COUNTFLAG__##e)
|
||||
#define BFM_SYSTICK_CSR_COUNTFLAG_V(v) BM_SYSTICK_CSR_COUNTFLAG
|
||||
#define BP_SYSTICK_CSR_CLKSOURCE 2
|
||||
#define BM_SYSTICK_CSR_CLKSOURCE 0x4
|
||||
#define BV_SYSTICK_CSR_CLKSOURCE__EXT 0x0
|
||||
#define BV_SYSTICK_CSR_CLKSOURCE__CPU 0x1
|
||||
#define BF_SYSTICK_CSR_CLKSOURCE(v) (((v) & 0x1) << 2)
|
||||
#define BFM_SYSTICK_CSR_CLKSOURCE(v) BM_SYSTICK_CSR_CLKSOURCE
|
||||
#define BF_SYSTICK_CSR_CLKSOURCE_V(e) BF_SYSTICK_CSR_CLKSOURCE(BV_SYSTICK_CSR_CLKSOURCE__##e)
|
||||
#define BFM_SYSTICK_CSR_CLKSOURCE_V(v) BM_SYSTICK_CSR_CLKSOURCE
|
||||
#define BP_SYSTICK_CSR_TICKINT 1
|
||||
#define BM_SYSTICK_CSR_TICKINT 0x2
|
||||
#define BF_SYSTICK_CSR_TICKINT(v) (((v) & 0x1) << 1)
|
||||
#define BFM_SYSTICK_CSR_TICKINT(v) BM_SYSTICK_CSR_TICKINT
|
||||
#define BF_SYSTICK_CSR_TICKINT_V(e) BF_SYSTICK_CSR_TICKINT(BV_SYSTICK_CSR_TICKINT__##e)
|
||||
#define BFM_SYSTICK_CSR_TICKINT_V(v) BM_SYSTICK_CSR_TICKINT
|
||||
#define BP_SYSTICK_CSR_ENABLE 0
|
||||
#define BM_SYSTICK_CSR_ENABLE 0x1
|
||||
#define BF_SYSTICK_CSR_ENABLE(v) (((v) & 0x1) << 0)
|
||||
#define BFM_SYSTICK_CSR_ENABLE(v) BM_SYSTICK_CSR_ENABLE
|
||||
#define BF_SYSTICK_CSR_ENABLE_V(e) BF_SYSTICK_CSR_ENABLE(BV_SYSTICK_CSR_ENABLE__##e)
|
||||
#define BFM_SYSTICK_CSR_ENABLE_V(v) BM_SYSTICK_CSR_ENABLE
|
||||
|
||||
#define REG_SYSTICK_RVR cm_reg(SYSTICK_RVR)
|
||||
#define CMA_SYSTICK_RVR (0xe000e000 + 0x14)
|
||||
#define CMT_SYSTICK_RVR CMIO_32_RW
|
||||
#define CMN_SYSTICK_RVR SYSTICK_RVR
|
||||
#define BP_SYSTICK_RVR_VALUE 0
|
||||
#define BM_SYSTICK_RVR_VALUE 0xffffff
|
||||
#define BF_SYSTICK_RVR_VALUE(v) (((v) & 0xffffff) << 0)
|
||||
#define BFM_SYSTICK_RVR_VALUE(v) BM_SYSTICK_RVR_VALUE
|
||||
#define BF_SYSTICK_RVR_VALUE_V(e) BF_SYSTICK_RVR_VALUE(BV_SYSTICK_RVR_VALUE__##e)
|
||||
#define BFM_SYSTICK_RVR_VALUE_V(v) BM_SYSTICK_RVR_VALUE
|
||||
|
||||
#define REG_SYSTICK_CVR cm_reg(SYSTICK_CVR)
|
||||
#define CMA_SYSTICK_CVR (0xe000e000 + 0x18)
|
||||
#define CMT_SYSTICK_CVR CMIO_32_RW
|
||||
#define CMN_SYSTICK_CVR SYSTICK_CVR
|
||||
#define BP_SYSTICK_CVR_VALUE 0
|
||||
#define BM_SYSTICK_CVR_VALUE 0xffffff
|
||||
#define BF_SYSTICK_CVR_VALUE(v) (((v) & 0xffffff) << 0)
|
||||
#define BFM_SYSTICK_CVR_VALUE(v) BM_SYSTICK_CVR_VALUE
|
||||
#define BF_SYSTICK_CVR_VALUE_V(e) BF_SYSTICK_CVR_VALUE(BV_SYSTICK_CVR_VALUE__##e)
|
||||
#define BFM_SYSTICK_CVR_VALUE_V(v) BM_SYSTICK_CVR_VALUE
|
||||
|
||||
#define REG_SYSTICK_CALIB cm_reg(SYSTICK_CALIB)
|
||||
#define CMA_SYSTICK_CALIB (0xe000e000 + 0x1c)
|
||||
#define CMT_SYSTICK_CALIB CMIO_32_RW
|
||||
#define CMN_SYSTICK_CALIB SYSTICK_CALIB
|
||||
#define BP_SYSTICK_CALIB_TENMS 0
|
||||
#define BM_SYSTICK_CALIB_TENMS 0xffffff
|
||||
#define BF_SYSTICK_CALIB_TENMS(v) (((v) & 0xffffff) << 0)
|
||||
#define BFM_SYSTICK_CALIB_TENMS(v) BM_SYSTICK_CALIB_TENMS
|
||||
#define BF_SYSTICK_CALIB_TENMS_V(e) BF_SYSTICK_CALIB_TENMS(BV_SYSTICK_CALIB_TENMS__##e)
|
||||
#define BFM_SYSTICK_CALIB_TENMS_V(v) BM_SYSTICK_CALIB_TENMS
|
||||
#define BP_SYSTICK_CALIB_NOREF 31
|
||||
#define BM_SYSTICK_CALIB_NOREF 0x80000000
|
||||
#define BF_SYSTICK_CALIB_NOREF(v) (((v) & 0x1) << 31)
|
||||
#define BFM_SYSTICK_CALIB_NOREF(v) BM_SYSTICK_CALIB_NOREF
|
||||
#define BF_SYSTICK_CALIB_NOREF_V(e) BF_SYSTICK_CALIB_NOREF(BV_SYSTICK_CALIB_NOREF__##e)
|
||||
#define BFM_SYSTICK_CALIB_NOREF_V(v) BM_SYSTICK_CALIB_NOREF
|
||||
#define BP_SYSTICK_CALIB_SKEW 30
|
||||
#define BM_SYSTICK_CALIB_SKEW 0x40000000
|
||||
#define BF_SYSTICK_CALIB_SKEW(v) (((v) & 0x1) << 30)
|
||||
#define BFM_SYSTICK_CALIB_SKEW(v) BM_SYSTICK_CALIB_SKEW
|
||||
#define BF_SYSTICK_CALIB_SKEW_V(e) BF_SYSTICK_CALIB_SKEW(BV_SYSTICK_CALIB_SKEW__##e)
|
||||
#define BFM_SYSTICK_CALIB_SKEW_V(v) BM_SYSTICK_CALIB_SKEW
|
||||
|
||||
#endif /* __ARM_CORTEX_M_SYSTICK_H__*/
|
||||
81
utils/reggen-ng/arm-cortex-m7.reggen
Normal file
81
utils/reggen-ng/arm-cortex-m7.reggen
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
name "cortex_m7"
|
||||
title "Cortex-M7"
|
||||
isa "armv7-m"
|
||||
version "1.0"
|
||||
author "Aidan MacDonald"
|
||||
|
||||
node CACHE {
|
||||
title "Cache control"
|
||||
addr 0xe000e000
|
||||
|
||||
reg ICIALLU 0xf50
|
||||
reg ICIMVAU 0xf58
|
||||
reg DCIMVAC 0xf5c
|
||||
reg DCISW 0xf60
|
||||
reg DCCMVAU 0xf64
|
||||
reg DCCMVAC 0xf68
|
||||
reg DCCSW 0xf6c
|
||||
reg DCCIMVAC 0xf70
|
||||
reg DCCISW 0xf74
|
||||
}
|
||||
|
||||
node NVIC {
|
||||
title "Nested vectored interrupt controller"
|
||||
addr 0xe000e000
|
||||
|
||||
reg ISER { instance 0x100 0x4 8 }
|
||||
reg ICER { instance 0x180 0x4 8 }
|
||||
reg ISPR { instance 0x200 0x4 8 }
|
||||
reg ICPR { instance 0x280 0x4 8 }
|
||||
reg IABR { instance 0x300 0x4 8 }
|
||||
reg IPR { instance 0x400 0x4 60 }
|
||||
|
||||
reg STIR 0xf00 {
|
||||
fld 8 0 INTID
|
||||
}
|
||||
}
|
||||
|
||||
node SCB {
|
||||
title "System control block"
|
||||
addr 0xe000e000
|
||||
|
||||
reg VTOR 0xd08
|
||||
|
||||
reg CCR 0xd14 {
|
||||
bit 18 BP
|
||||
bit 17 IC
|
||||
bit 16 DC
|
||||
bit 9 STKALIGN
|
||||
bit 8 BFHFNMIGN
|
||||
bit 4 DIV_0_TRP
|
||||
bit 3 UNALIGN_TRP
|
||||
bit 1 USERETMPEND
|
||||
bit 0 NONBASETHRDENA
|
||||
}
|
||||
}
|
||||
|
||||
node SYSTICK {
|
||||
title "System timer"
|
||||
addr 0xe000e000
|
||||
|
||||
reg CSR 0x10 {
|
||||
bit 16 COUNTFLAG
|
||||
bit 2 CLKSOURCE { enum EXT 0; enum CPU 1 }
|
||||
bit 1 TICKINT
|
||||
bit 0 ENABLE
|
||||
}
|
||||
|
||||
reg RVR 0x14 {
|
||||
fld 23 0 VALUE
|
||||
}
|
||||
|
||||
reg CVR 0x18 {
|
||||
fld 23 0 VALUE
|
||||
}
|
||||
|
||||
reg CALIB 0x1c {
|
||||
bit 31 NOREF
|
||||
bit 30 SKEW
|
||||
fld 23 0 TENMS
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue