From 4d3190f416209ad9926090dac6efef2e4747c420 Mon Sep 17 00:00:00 2001 From: Aidan MacDonald Date: Tue, 7 Jan 2025 12:12:16 +0000 Subject: [PATCH] arm: split ARM cache maintenance functions to separate header Cortex-M processors don't have an MMU, but can still have caches that need software management, so on those platforms we don't want to include the MMU related functions. While here, remove an outdated section of a comment referring to deprecated cache maintenance functions which no longer exist. Change-Id: I6f0fe694560bdee25ed7c69a846bf46e3e544cb1 --- bootloader/gigabeat.c | 1 - firmware/target/arm/as3525/pcm-as3525.c | 1 + firmware/target/arm/as3525/system-target.h | 1 + firmware/target/arm/cpucache-arm.h | 64 +++++++++++++++++++ firmware/target/arm/imx233/system-target.h | 1 + .../arm/imx31/gigabeat-s/system-target.h | 1 + firmware/target/arm/mmu-arm.h | 42 ------------ firmware/target/arm/s3c2440/dma-s3c2440.c | 1 - firmware/target/arm/s3c2440/system-s3c2440.c | 1 - firmware/target/arm/s3c2440/system-target.h | 1 + .../arm/s5l8700/ipodnano2g/nand-nano2g.c | 1 + firmware/target/arm/s5l8700/pcm-s5l8700.c | 1 + firmware/target/arm/s5l8700/system-target.h | 1 + .../arm/s5l8702/ipod6g/storage_ata-6g.c | 1 - firmware/target/arm/s5l8702/pcm-s5l8702.c | 1 - firmware/target/arm/s5l8702/system-target.h | 1 + firmware/target/arm/tcc780x/system-target.h | 1 + .../arm/tms320dm320/mrobe-500/lcd-mr500.c | 1 - .../arm/tms320dm320/mrobe-500/pcm-mr500.c | 1 - .../sansa-connect/pcm-sansaconnect.c | 1 - .../target/arm/tms320dm320/system-dm320.c | 1 - .../target/arm/tms320dm320/system-target.h | 1 + 22 files changed, 75 insertions(+), 51 deletions(-) create mode 100644 firmware/target/arm/cpucache-arm.h diff --git a/bootloader/gigabeat.c b/bootloader/gigabeat.c index 005d33630f..b56cc13655 100644 --- a/bootloader/gigabeat.c +++ b/bootloader/gigabeat.c @@ -44,7 +44,6 @@ #include "loader_strerror.h" #include "rbunicode.h" #include "usb.h" -#include "mmu-arm.h" #include "rtc.h" #include "version.h" diff --git a/firmware/target/arm/as3525/pcm-as3525.c b/firmware/target/arm/as3525/pcm-as3525.c index e480140497..8800602b47 100644 --- a/firmware/target/arm/as3525/pcm-as3525.c +++ b/firmware/target/arm/as3525/pcm-as3525.c @@ -29,6 +29,7 @@ #include "as3514.h" #include "audiohw.h" #include "mmu-arm.h" +#include "cpucache-arm.h" #include "pcm-internal.h" #define MAX_TRANSFER (4*((1<<11)-1)) /* maximum data we can transfer via DMA diff --git a/firmware/target/arm/as3525/system-target.h b/firmware/target/arm/as3525/system-target.h index 5cdc573a1b..5b504b72d4 100644 --- a/firmware/target/arm/as3525/system-target.h +++ b/firmware/target/arm/as3525/system-target.h @@ -26,6 +26,7 @@ #include "system-arm.h" #include "mmu-arm.h" +#include "cpucache-arm.h" #include "panic.h" #include "clock-target.h" /* CPUFREQ_* are defined here */ diff --git a/firmware/target/arm/cpucache-arm.h b/firmware/target/arm/cpucache-arm.h new file mode 100644 index 0000000000..40bfe7e2f1 --- /dev/null +++ b/firmware/target/arm/cpucache-arm.h @@ -0,0 +1,64 @@ +/*************************************************************************** + * __________ __ ___. + * Open \______ \ ____ ____ | | _\_ |__ _______ ___ + * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / + * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < + * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ + * \/ \/ \/ \/ \/ + * $Id$ + * + * Copyright (C) 2006,2007 by Greg White + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY + * KIND, either express or implied. + * + ****************************************************************************/ + +/* This file MUST be included in your system-target.h file if you want arm + * cache coherence functions to be called (I.E. during codec load, etc). + */ + +#ifndef CPUCACHE_ARM_H +#define CPUCACHE_ARM_H + +/* Note for the function names + * + * ARM refers to the cache coherency functions as (in the CPU manuals): + * clean (write-back) + * clean and invalidate (write-back and removing the line from cache) + * invalidate (removing from cache without write-back) + * + * This names have been proven to cause confusion, therefore we use: + * commit + * commit and discard + * discard + */ + +/* Commits entire DCache */ +void commit_dcache(void); + +/* Commit and discard entire DCache, will do writeback */ +void commit_discard_dcache(void); + +/* Write DCache back to RAM for the given range and remove cache lines + * from DCache afterwards */ +void commit_discard_dcache_range(const void *base, unsigned int size); + +/* Write DCache back to RAM for the given range */ +void commit_dcache_range(const void *base, unsigned int size); + +/* + * Remove cache lines for the given range from DCache + * will *NOT* do write back except for buffer edges not on a line boundary + */ +void discard_dcache_range(const void *base, unsigned int size); + +/* Discards the entire ICache, and commit+discards the entire DCache */ +void commit_discard_idcache(void); + +#endif /* CPUCACHE_ARM_H */ diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h index bab76752df..3c7bbc6f37 100644 --- a/firmware/target/arm/imx233/system-target.h +++ b/firmware/target/arm/imx233/system-target.h @@ -23,6 +23,7 @@ #include "system-arm.h" #include "mmu-arm.h" +#include "cpucache-arm.h" #include "panic.h" #include "clkctrl-imx233.h" #include "icoll-imx233.h" diff --git a/firmware/target/arm/imx31/gigabeat-s/system-target.h b/firmware/target/arm/imx31/gigabeat-s/system-target.h index b12ca13bb5..14cfaf2eb7 100644 --- a/firmware/target/arm/imx31/gigabeat-s/system-target.h +++ b/firmware/target/arm/imx31/gigabeat-s/system-target.h @@ -23,6 +23,7 @@ #include "system-arm.h" #include "mmu-arm.h" +#include "cpucache-arm.h" /* High enough for most tasks but low enough for reduced voltage */ #define CPUFREQ_DEFAULT 264000000 diff --git a/firmware/target/arm/mmu-arm.h b/firmware/target/arm/mmu-arm.h index 155769489e..348d52acaa 100644 --- a/firmware/target/arm/mmu-arm.h +++ b/firmware/target/arm/mmu-arm.h @@ -19,10 +19,6 @@ * ****************************************************************************/ -/* This file MUST be included in your system-target.h file if you want arm - * cache coherence functions to be called (I.E. during codec load, etc). - */ - #ifndef MMU_ARM_H #define MMU_ARM_H @@ -35,42 +31,4 @@ void ttb_init(void); void enable_mmu(void); void map_section(unsigned int pa, unsigned int va, int mb, int flags); -/* Note for the function names - * - * ARM refers to the cache coherency functions as (in the CPU manuals): - * clean (write-back) - * clean and invalidate (write-back and removing the line from cache) - * invalidate (removing from cache without write-back) - * - * The deprecated functions below don't follow the above (which is why - * they're deprecated). - * - * This names have been proven to cause confusion, therefore we use: - * commit - * commit and discard - * discard - */ - -/* Commits entire DCache */ -void commit_dcache(void); - -/* Commit and discard entire DCache, will do writeback */ -void commit_discard_dcache(void); - -/* Write DCache back to RAM for the given range and remove cache lines - * from DCache afterwards */ -void commit_discard_dcache_range(const void *base, unsigned int size); - -/* Write DCache back to RAM for the given range */ -void commit_dcache_range(const void *base, unsigned int size); - -/* - * Remove cache lines for the given range from DCache - * will *NOT* do write back except for buffer edges not on a line boundary - */ -void discard_dcache_range(const void *base, unsigned int size); - -/* Discards the entire ICache, and commit+discards the entire DCache */ -void commit_discard_idcache(void); - #endif /* MMU_ARM_H */ diff --git a/firmware/target/arm/s3c2440/dma-s3c2440.c b/firmware/target/arm/s3c2440/dma-s3c2440.c index 3cf1d05f1b..32be66d0a8 100644 --- a/firmware/target/arm/s3c2440/dma-s3c2440.c +++ b/firmware/target/arm/s3c2440/dma-s3c2440.c @@ -23,7 +23,6 @@ #include "config.h" #include "panic.h" #include "system.h" -#include "mmu-arm.h" #include "s3c2440.h" #include "dma-target.h" #include "system-target.h" diff --git a/firmware/target/arm/s3c2440/system-s3c2440.c b/firmware/target/arm/s3c2440/system-s3c2440.c index 1e5613f7b6..569dcabdbe 100644 --- a/firmware/target/arm/s3c2440/system-s3c2440.c +++ b/firmware/target/arm/s3c2440/system-s3c2440.c @@ -21,7 +21,6 @@ #include "kernel.h" #include "system.h" #include "panic.h" -#include "mmu-arm.h" #include "cpu.h" #include "gcc_extensions.h" diff --git a/firmware/target/arm/s3c2440/system-target.h b/firmware/target/arm/s3c2440/system-target.h index c48a62cf47..33662cd9e5 100644 --- a/firmware/target/arm/s3c2440/system-target.h +++ b/firmware/target/arm/s3c2440/system-target.h @@ -23,6 +23,7 @@ #include "system-arm.h" #include "mmu-arm.h" +#include "cpucache-arm.h" /* NB: These values must match the register settings in s3c2440/crt0.S */ diff --git a/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c b/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c index 85b8354c1e..49e0c4d3b5 100644 --- a/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c +++ b/firmware/target/arm/s5l8700/ipodnano2g/nand-nano2g.c @@ -29,6 +29,7 @@ #include "nand-target.h" #include #include +#include #include #include "led.h" #include "storage.h" diff --git a/firmware/target/arm/s5l8700/pcm-s5l8700.c b/firmware/target/arm/s5l8700/pcm-s5l8700.c index 5ad6cab0fb..fa7ff75ada 100644 --- a/firmware/target/arm/s5l8700/pcm-s5l8700.c +++ b/firmware/target/arm/s5l8700/pcm-s5l8700.c @@ -31,6 +31,7 @@ #include "pcm_sampr.h" #include "dma-target.h" #include "mmu-arm.h" +#include "cpucache-arm.h" /* Driver for the IIS/PCM part of the s5l8700 using DMA diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h index 170794a999..67c8647042 100644 --- a/firmware/target/arm/s5l8700/system-target.h +++ b/firmware/target/arm/s5l8700/system-target.h @@ -23,6 +23,7 @@ #include "system-arm.h" #include "mmu-arm.h" +#include "cpucache-arm.h" #define CPUFREQ_SLEEP 32768 #define CPUFREQ_MAX (1843200 * 4 * 26 / 1) /* 191692800 Hz */ diff --git a/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c b/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c index 488340c434..4b5143e623 100644 --- a/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c +++ b/firmware/target/arm/s5l8702/ipod6g/storage_ata-6g.c @@ -27,7 +27,6 @@ #include "string.h" #include "power.h" #include "panic.h" -#include "mmu-arm.h" #include "mmcdefs-target.h" #include "s5l87xx.h" #include "led.h" diff --git a/firmware/target/arm/s5l8702/pcm-s5l8702.c b/firmware/target/arm/s5l8702/pcm-s5l8702.c index 207bc44613..0f532cc1bf 100644 --- a/firmware/target/arm/s5l8702/pcm-s5l8702.c +++ b/firmware/target/arm/s5l8702/pcm-s5l8702.c @@ -29,7 +29,6 @@ #include "pcm.h" #include "pcm-internal.h" #include "pcm_sampr.h" -#include "mmu-arm.h" #include "pcm-target.h" #include "dma-s5l8702.h" diff --git a/firmware/target/arm/s5l8702/system-target.h b/firmware/target/arm/s5l8702/system-target.h index 65aba53a91..c1835fc9bc 100644 --- a/firmware/target/arm/s5l8702/system-target.h +++ b/firmware/target/arm/s5l8702/system-target.h @@ -23,6 +23,7 @@ #include "system-arm.h" #include "mmu-arm.h" +#include "cpucache-arm.h" #define CPUFREQ_SLEEP 32768 diff --git a/firmware/target/arm/tcc780x/system-target.h b/firmware/target/arm/tcc780x/system-target.h index fe66a6eb68..995e745a64 100644 --- a/firmware/target/arm/tcc780x/system-target.h +++ b/firmware/target/arm/tcc780x/system-target.h @@ -23,6 +23,7 @@ #include "system-arm.h" #include "mmu-arm.h" +#include "cpucache-arm.h" #define CPUFREQ_DEFAULT 32000000 #define CPUFREQ_NORMAL 48000000 diff --git a/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c b/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c index 8620c672e1..dcd077eae9 100644 --- a/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c +++ b/firmware/target/arm/tms320dm320/mrobe-500/lcd-mr500.c @@ -29,7 +29,6 @@ #include "kernel.h" #include "system.h" #include "string-extra.h" /* memset16() */ -#include "mmu-arm.h" #include "system-target.h" #include "lcd.h" #include "lcd-target.h" diff --git a/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c b/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c index fda8615e5a..7befeb40c0 100644 --- a/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c +++ b/firmware/target/arm/tms320dm320/mrobe-500/pcm-mr500.c @@ -27,7 +27,6 @@ #include "file.h" #include "dsp-target.h" #include "dsp/ipc.h" -#include "mmu-arm.h" #include "pcm-internal.h" /* This is global to save some latency when pcm_play_dma_get_peak_buffer is diff --git a/firmware/target/arm/tms320dm320/sansa-connect/pcm-sansaconnect.c b/firmware/target/arm/tms320dm320/sansa-connect/pcm-sansaconnect.c index bda000e68f..95c3e456fa 100644 --- a/firmware/target/arm/tms320dm320/sansa-connect/pcm-sansaconnect.c +++ b/firmware/target/arm/tms320dm320/sansa-connect/pcm-sansaconnect.c @@ -27,7 +27,6 @@ #include "file.h" #include "dsp-target.h" #include "dsp/ipc.h" -#include "mmu-arm.h" #include "pcm-internal.h" #include "dma-target.h" diff --git a/firmware/target/arm/tms320dm320/system-dm320.c b/firmware/target/arm/tms320dm320/system-dm320.c index 62eaf1f8ce..6df9868f1c 100644 --- a/firmware/target/arm/tms320dm320/system-dm320.c +++ b/firmware/target/arm/tms320dm320/system-dm320.c @@ -20,7 +20,6 @@ * ****************************************************************************/ #include "cpu.h" -#include "mmu-arm.h" #include "kernel.h" #include "system.h" #include "panic.h" diff --git a/firmware/target/arm/tms320dm320/system-target.h b/firmware/target/arm/tms320dm320/system-target.h index 9aa8b3e213..d228129e0f 100644 --- a/firmware/target/arm/tms320dm320/system-target.h +++ b/firmware/target/arm/tms320dm320/system-target.h @@ -23,6 +23,7 @@ #include "system-arm.h" #include "mmu-arm.h" +#include "cpucache-arm.h" #ifdef SANSA_CONNECT #define CPUFREQ_DEFAULT 74250000