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4d3190f416
Cortex-M processors don't have an MMU, but can still have caches that need software management, so on those platforms we don't want to include the MMU related functions. While here, remove an outdated section of a comment referring to deprecated cache maintenance functions which no longer exist. Change-Id: I6f0fe694560bdee25ed7c69a846bf46e3e544cb1
385 lines
10 KiB
C
385 lines
10 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2008-2009 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "audio.h"
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#include "string.h"
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#include "as3525.h"
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#include "pl081.h"
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#include "dma-target.h"
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#include "clock-target.h"
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#include "panic.h"
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#include "as3514.h"
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#include "audiohw.h"
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#include "mmu-arm.h"
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#include "cpucache-arm.h"
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#include "pcm-internal.h"
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#define MAX_TRANSFER (4*((1<<11)-1)) /* maximum data we can transfer via DMA
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* i.e. 32 bits at once (size of I2SO_DATA)
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* and the number of 32bits words has to
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* fit in 11 bits of DMA register */
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static const void *dma_start_addr; /* Pointer to callback buffer */
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static size_t dma_start_size; /* Size of callback buffer */
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static const void *dma_sub_addr; /* Pointer to sub buffer */
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static size_t dma_rem_size; /* Remaining size - in 4*32 bits */
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static size_t play_sub_size; /* size of current subtransfer */
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static void dma_callback(void);
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static int locked = 0;
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static bool volatile is_playing = false;
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static bool play_callback_pending = false;
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#ifdef HAVE_RECORDING
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/* Stopping playback gates clock if not recording */
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static bool volatile is_recording = false;
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#endif
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/* Mask the DMA interrupt */
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void pcm_play_lock(void)
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{
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++locked;
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}
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/* Unmask the DMA interrupt if enabled */
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void pcm_play_unlock(void)
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{
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if(--locked == 0 && is_playing)
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{
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int old = disable_irq_save();
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if(play_callback_pending)
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{
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play_callback_pending = false;
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dma_callback();
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}
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restore_irq(old);
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}
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}
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static void play_start_pcm(void)
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{
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const void *addr = dma_sub_addr;
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size_t size = dma_rem_size;
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if(size > MAX_TRANSFER)
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size = MAX_TRANSFER;
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play_sub_size = size;
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dma_enable_channel(0, (void*)addr, (void*)I2SOUT_DATA, DMA_PERI_I2SOUT,
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DMAC_FLOWCTRL_DMAC_MEM_TO_PERI, true, false, size >> 2,
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DMA_S16, dma_callback);
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}
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static void dma_callback(void)
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{
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dma_sub_addr += play_sub_size;
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dma_rem_size -= play_sub_size;
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play_sub_size = 0; /* Might get called again if locked */
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if(locked)
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{
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play_callback_pending = is_playing;
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return;
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}
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if(!dma_rem_size)
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{
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if(!pcm_play_dma_complete_callback(PCM_DMAST_OK, &dma_start_addr,
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&dma_start_size))
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return;
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dma_sub_addr = dma_start_addr;
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dma_rem_size = dma_start_size;
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/* force writeback */
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commit_dcache_range(dma_start_addr, dma_start_size);
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play_start_pcm();
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pcm_play_dma_status_callback(PCM_DMAST_STARTED);
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}
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else
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{
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play_start_pcm();
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}
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}
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void pcm_play_dma_start(const void *addr, size_t size)
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{
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is_playing = true;
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dma_start_addr = addr;
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dma_start_size = size;
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dma_sub_addr = dma_start_addr;
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dma_rem_size = size;
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dma_retain();
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/* force writeback */
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commit_dcache_range(dma_start_addr, dma_start_size);
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play_start_pcm();
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}
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void pcm_play_dma_stop(void)
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{
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is_playing = false;
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dma_disable_channel(0);
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/* Ensure byte counts read back 0 */
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DMAC_CH_SRC_ADDR(0) = 0;
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dma_start_addr = NULL;
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dma_start_size = 0;
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dma_rem_size = 0;
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dma_release();
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play_callback_pending = false;
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}
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void pcm_play_dma_init(void)
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{
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bitset32(&CGU_PERI, CGU_I2SOUT_APB_CLOCK_ENABLE);
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I2SOUT_CONTROL = (1<<6) | (1<<3); /* enable dma, stereo */
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audiohw_preinit();
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pcm_dma_apply_settings();
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}
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void pcm_play_dma_postinit(void)
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{
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audiohw_postinit();
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}
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/* divider is 9 bits but the highest one (for 8kHz) fit in 8 bits */
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static const unsigned char divider[SAMPR_NUM_FREQ] = {
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[HW_FREQ_96] = ((AS3525_MCLK_FREQ/128 + SAMPR_96/2) / SAMPR_96) - 1,
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[HW_FREQ_88] = ((AS3525_MCLK_FREQ/128 + SAMPR_88/2) / SAMPR_88) - 1,
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[HW_FREQ_64] = ((AS3525_MCLK_FREQ/128 + SAMPR_64/2) / SAMPR_64) - 1,
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[HW_FREQ_48] = ((AS3525_MCLK_FREQ/128 + SAMPR_48/2) / SAMPR_48) - 1,
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[HW_FREQ_44] = ((AS3525_MCLK_FREQ/128 + SAMPR_44/2) / SAMPR_44) - 1,
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[HW_FREQ_32] = ((AS3525_MCLK_FREQ/128 + SAMPR_32/2) / SAMPR_32) - 1,
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[HW_FREQ_24] = ((AS3525_MCLK_FREQ/128 + SAMPR_24/2) / SAMPR_24) - 1,
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[HW_FREQ_22] = ((AS3525_MCLK_FREQ/128 + SAMPR_22/2) / SAMPR_22) - 1,
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[HW_FREQ_16] = ((AS3525_MCLK_FREQ/128 + SAMPR_16/2) / SAMPR_16) - 1,
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[HW_FREQ_12] = ((AS3525_MCLK_FREQ/128 + SAMPR_12/2) / SAMPR_12) - 1,
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[HW_FREQ_11] = ((AS3525_MCLK_FREQ/128 + SAMPR_11/2) / SAMPR_11) - 1,
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[HW_FREQ_8 ] = ((AS3525_MCLK_FREQ/128 + SAMPR_8 /2) / SAMPR_8 ) - 1,
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};
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static inline unsigned char mclk_divider(void)
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{
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return divider[pcm_fsel];
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}
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void pcm_dma_apply_settings(void)
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{
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bitmod32(&CGU_AUDIO,
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(0<<24) | /* I2SI_MCLK2PAD_EN = disabled */
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(0<<23) | /* I2SI_MCLK_EN = disabled */
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(0<<14) | /* I2SI_MCLK_DIV_SEL = unused */
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(0<<12) | /* I2SI_MCLK_SEL = clk_main */
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(1<<11) | /* I2SO_MCLK_EN */
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(mclk_divider() << 2) | /* I2SO_MCLK_DIV_SEL */
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(AS3525_MCLK_SEL << 0), /* I2SO_MCLK_SEL */
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0x01ffffff);
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}
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#ifdef HAVE_PCM_DMA_ADDRESS
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void * pcm_dma_addr(void *addr)
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{
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if (addr != NULL)
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addr = AS3525_UNCACHED_ADDR(addr);
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return addr;
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}
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#endif
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/****************************************************************************
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** Recording DMA transfer
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**/
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#ifdef HAVE_RECORDING
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static int rec_locked = 0;
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static uint32_t *rec_dma_addr;
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static size_t rec_dma_size;
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static int keep_sample = 0; /* In nonzero, keep the sample; else, discard it */
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void pcm_rec_lock(void)
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{
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int oldlevel = disable_irq_save();
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if (++rec_locked == 1)
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{
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bitset32(&CGU_PERI, CGU_I2SIN_APB_CLOCK_ENABLE);
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VIC_INT_EN_CLEAR = INTERRUPT_I2SIN;
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I2SIN_MASK = 0; /* disables all interrupts */
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}
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restore_irq(oldlevel);
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}
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void pcm_rec_unlock(void)
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{
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int oldlevel = disable_irq_save();
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if (--rec_locked == 0 && is_recording)
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{
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VIC_INT_ENABLE = INTERRUPT_I2SIN;
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I2SIN_MASK = (1<<2); /* I2SIN_MASK_POAF */
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}
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restore_irq(oldlevel);
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}
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void INT_I2SIN(void)
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{
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#if CONFIG_CPU == AS3525
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if (audio_channels == 1)
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{
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/* RX is left-channel-only mono */
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while (rec_dma_size > 0)
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{
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if (I2SIN_RAW_STATUS & (1<<5))
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return; /* empty */
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uint32_t value = *I2SIN_DATA;
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/* Discard every other sample since ADC clock is 1/2 LRCK */
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keep_sample ^= 1;
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if (keep_sample)
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{
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/* Data is in left channel only - copy to right channel
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14-bit => 16-bit samples */
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value = (uint16_t)(value << 2) | (value << 18);
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if (audio_output_source != AUDIO_SRC_PLAYBACK && !is_playing)
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{
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/* In this case, loopback is manual so that both output
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channels have audio */
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if (I2SOUT_RAW_STATUS & (1<<5))
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{
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/* Sync output fifo so it goes empty not before input is
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filled */
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for (unsigned i = 0; i < 4; i++)
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*I2SOUT_DATA = 0;
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}
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*I2SOUT_DATA = value;
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*I2SOUT_DATA = value;
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}
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*rec_dma_addr++ = value;
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rec_dma_size -= 4;
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}
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}
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}
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else
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#endif /* CONFIG_CPU == AS3525 */
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{
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/* RX is stereo */
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while (rec_dma_size > 0)
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{
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if (I2SIN_RAW_STATUS & (1<<5))
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return; /* empty */
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uint32_t value = *I2SIN_DATA;
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/* Discard every other sample since ADC clock is 1/2 LRCK */
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keep_sample ^= 1;
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if (keep_sample)
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{
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/* Loopback is in I2S hardware */
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/* 14-bit => 16-bit samples */
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*rec_dma_addr++ = (value << 2) & ~0x00030000;
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rec_dma_size -= 4;
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}
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}
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}
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/* Inform middle layer */
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if (pcm_rec_dma_complete_callback(PCM_DMAST_OK, (void **)&rec_dma_addr,
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&rec_dma_size))
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{
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pcm_rec_dma_status_callback(PCM_DMAST_STARTED);
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}
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}
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void pcm_rec_dma_stop(void)
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{
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is_recording = false;
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VIC_INT_EN_CLEAR = INTERRUPT_I2SIN;
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I2SIN_MASK = 0; /* disables all interrupts */
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rec_dma_addr = NULL;
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rec_dma_size = 0;
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bitclr32(&CGU_PERI, CGU_I2SIN_APB_CLOCK_ENABLE);
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}
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void pcm_rec_dma_start(void *addr, size_t size)
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{
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is_recording = true;
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rec_dma_addr = addr;
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rec_dma_size = size;
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keep_sample = 0;
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/* ensure empty FIFO */
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while (!(I2SIN_RAW_STATUS & (1<<5)))
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*I2SIN_DATA;
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I2SIN_CLEAR = (1<<6) | (1<<0); /* push error, pop error */
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}
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void pcm_rec_dma_close(void)
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{
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bitset32(&CGU_PERI, CGU_I2SIN_APB_CLOCK_ENABLE);
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pcm_rec_dma_stop();
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}
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void pcm_rec_dma_init(void)
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{
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bitset32(&CGU_PERI, CGU_I2SIN_APB_CLOCK_ENABLE);
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I2SIN_MASK = 0; /* disables all interrupts */
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/* 14 bits samples, i2c clk src = I2SOUTIF, sdata src = AFE,
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* data valid at positive edge of SCLK */
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I2SIN_CONTROL = (1<<5) | (1<<2);
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}
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const void * pcm_rec_dma_get_peak_buffer(void)
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{
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return rec_dma_addr;
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}
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#endif /* HAVE_RECORDING */
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