Richard Barry
db750d0c82
Update RSIC-V port layer after testing saving and receiving of chip specific registers.
2018-12-30 23:11:40 +00:00
Richard Barry
60b133b2c6
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
2018-12-30 20:00:43 +00:00
Richard Barry
d369110167
Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings.
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Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
2018-12-28 00:44:18 +00:00
Richard Barry
ce36928ea8
Rename directories in the RISC-V port.
2018-12-24 17:37:02 +00:00
Richard Barry
148f588f56
Remove "FromISR' functions from the list of functions that switch to a privileged mode as IRQs are privileged already.
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Add the vTimerSetReloadMode() API function.
2018-12-17 22:04:18 +00:00
Richard Barry
101806906d
Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT.
2018-12-16 23:59:49 +00:00
Richard Barry
7cc42b2ab6
Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
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+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
2018-12-16 20:21:29 +00:00
Richard Barry
65f7a2dc19
Update RISC-V port to use a separate interrupt stack.
2018-12-04 01:23:41 +00:00
Richard Barry
e85ea96f78
Some efficiency improvements in Risc-V port.
2018-11-28 19:35:40 +00:00
Richard Barry
dc99300fa9
First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.
2018-11-24 20:59:07 +00:00
Richard Barry
db64297487
Provide each Risc V task with an initial mstatus register value.
2018-11-20 20:12:35 +00:00
Richard Barry
8cef339aec
Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.
2018-11-19 06:01:29 +00:00
Richard Barry
baee711cb6
Continue work on Risc V port.
2018-11-06 02:04:28 +00:00
Richard Barry
6fab2b9e0d
Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom().
2018-10-08 15:10:18 +00:00
Richard Barry
c6de0001fa
Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type.
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Allows the task name parameter passed into xTaskCreate() to be NULL.
2018-09-30 21:50:05 +00:00
Richard Barry
e3dc5e934b
RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet.
2018-09-27 17:25:17 +00:00
Richard Barry
2bcb1ab02b
Add trap handler to RISC-V port so there is no dependency on third party code.
2018-09-23 03:52:23 +00:00
Richard Barry
32f35e9130
RISC-V:
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Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
2018-09-12 16:33:05 +00:00
Richard Barry
b11eb3a59c
RISC-V work in progress:
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+ Initialise task stack.
+ Successfully jump to start of first task.
2018-09-10 20:50:05 +00:00
Richard Barry
92ae8e7aff
Update version numbers ready for release.
2018-09-07 18:13:20 +00:00
Richard Barry
e2750cd388
Case unused return values for memset and memcpy to void in stream_buffer.c to avoid compiler warnings when the warning level is turned up.
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Remove duplicate comment in heap_1.c.
2018-08-29 15:43:41 +00:00
Richard Barry
3a1631fda3
Update copyright date ready for tagging V10.1.0.
2018-08-22 23:23:03 +00:00
Richard Barry
fb9de58f56
Update version numbers in preparation for a new release.
2018-08-21 19:50:48 +00:00
Richard Barry
722ca8fb2b
Update demo project for Tensilita - work in progres..
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Add support for POSIX style errno - work in progress.
2018-08-21 19:37:04 +00:00
Gaurav Aggarwal
56dc0dd9b4
Merge bug fixes from Cadence
2018-08-07 07:21:07 +00:00
Richard Barry
f6cbf20019
Update RISC-V project to used official port stubs in place of third party port.
2018-07-07 21:54:41 +00:00
Richard Barry
3bfc32d444
Add stubs for official RISC-V RV32 port.
2018-07-07 21:47:31 +00:00
Richard Barry
483f4a8c4b
Small change to the directory name in which the RISC-V port is stored.
2018-06-20 21:15:04 +00:00
Richard Barry
3d8d2f3cc8
Add RISCV port layer.
2018-06-20 19:21:18 +00:00
Gaurav Aggarwal
c4b1afc4ef
Add Xtensa port
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The project file is for Xtensa Xplorer simulator.
Also add tests for one size stream buffer.
2018-06-14 19:43:17 +00:00
Richard Barry
4fbcdbf13b
Fix misra violations in queue.c by introducing a union that allows the correct data types to be used in place of void *, then tidy up where the union is used.
2018-06-11 18:51:53 +00:00
Richard Barry
390fb06b49
First pass at updating from MISRA 2004 to MISRA 2012:
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Updated pvContainer member of list items to List_t * rather than void * as they are always contained in a list if anywhere.
Made EventGroupHandle_t typesafe pointer to forward referenced struct rather than void pointer.
Made TaskHandle_t typesafe pointer to forward referenced struct, rather than a void pointer.
2018-06-03 22:57:46 +00:00
Richard Barry
5bebf10fa4
Minor updates to comments only.
2018-05-17 17:50:14 +00:00
Richard Barry
aec45f2479
Import the code coverage test additions from the (unpublished) Visual Studio project to the (published) MingW/Eclipse project.
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Update the MingW/Eclipse project to add a code coverage build configuration in addition to the existing Debug build configuration.
Update StreamBufferDemo.c so functions are called directly, rather than via configASSERT(), so their code coverage can be measured when configASSERT() is not defined.
In the Win32 port, replace the call to TerminateProcess() in vPortEndScheduler() with exit( 0 ) - which triggers the writing of the code coverage data to the disk.
Fix bug in ucStreamBufferGetStreamBufferType() - which is only used by the Percepio trace tool.
Update the line within vTaskStartScheduler() that was setting xTickCount to 0 to instead set it to configINITIAL_TICK_COUNT.
2018-03-14 15:58:47 +00:00
Richard Barry
f9bef06ec0
Introduce xMessageBufferNextLengthBytes() and tests for the same.
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Add call to traceTASK_SWITCHED_IN() in vTaskStartScheduler() so trace tools can see the first task to run.
2018-03-04 19:25:14 +00:00
Richard Barry
7ddb8b342d
Microblaze port: Place critical section around XIntc_Enable() to protect read/modify/write operation performed inside the library.
2018-01-30 17:42:12 +00:00
Richard Barry
13651934be
Roll up the minor changes checked into svn since V10.0.0 into new V10.0.1 ready for release.
2017-12-18 22:54:18 +00:00
Richard Barry
cfc268814a
Update to MIT licensed FreeRTOS V10.0.0 - see https://www.freertos.org/History.txt
2017-11-29 16:53:26 +00:00
Richard Barry
037abdddf2
Update TriCore port to work with latest GCC compiler.
2017-08-09 16:57:35 +00:00
Richard Barry
6eea3d8d4b
Correct long time mis-spelled portINITIAL_EXEC_RETURN to portINITIAL_EXC_RETURN
2017-05-30 00:36:09 +00:00
Richard Barry
b080f13543
Add more "memory" clobbers into the MPU ports to make them robust to more aggressive optimisation in newer GCC version.
2017-04-10 01:58:01 +00:00
Richard Barry
0f85ead175
Add more "memory" clobbers into asm code of GCC/ARM_CRx_No_GIC port to make it robust with higher optimisation in newer versions of GCC.
2017-04-10 01:01:11 +00:00
Richard Barry
0a7a0a79d6
Updates to prevent warnings when compiled with LLVM.
2017-04-10 00:26:22 +00:00
Richard Barry
8ca40d80a9
Ensure the PIC32 interrupt stack is 8 byte aligned for all values of configISR_STACK_SIZE.
2017-04-09 20:13:48 +00:00
Richard Barry
464c2660ad
Updates to the Cortex-M tickless idle code to reduce clock slippage.
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Updates to prevent the vTaskSwitchContext() function being removed from GCC builds when link time optimisation is used.
2017-03-28 03:13:48 +00:00
Richard Barry
ad5659e93d
Housekeeping check-in, no code changes.
2017-03-08 22:19:14 +00:00
Richard Barry
b9fe24962e
Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across asm code as optimisers get more aggressive.
2017-03-07 04:06:10 +00:00
Richard Barry
c3acc441ac
Introduce vTaskInternalSetTimeOutState() which does not have a critical section, and add a critical section to the public version of the same.
2017-02-24 02:16:54 +00:00
Richard Barry
8d041c8e21
Update version number in preparation for maintenance release.
2017-01-22 05:28:13 +00:00
Richard Barry
992a3c8c71
Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions.
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Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
2017-01-19 04:11:21 +00:00
