mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
This commit is contained in:
Richard Barry
parent
911a1de273
commit
60b133b2c6
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@ -107,6 +107,7 @@
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#define configUSE_APPLICATION_TASK_TAG 0
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#define configUSE_COUNTING_SEMAPHORES 1
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#define configGENERATE_RUN_TIME_STATS 0
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
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/* Co-routine definitions. */
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#define configUSE_CO_ROUTINES 0
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@ -142,7 +143,4 @@ to exclude the API function. */
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header file. */
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#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); }
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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#endif /* FREERTOS_CONFIG_H */
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@ -57,6 +57,6 @@
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<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
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<listEntry value="4"/>
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</listAttribute>
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<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"> <memoryBlockExpression address="2147525816" label="0x8000a4b8"/> </memoryBlockExpressionList> "/>
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<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"> <memoryBlockExpression address="2147504144" label="0x80005010"/> </memoryBlockExpressionList> "/>
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<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
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</launchConfiguration>
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@ -44,7 +44,7 @@
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* regiters.
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* registers.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
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@ -62,5 +62,15 @@
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define portasmHAS_CLINT 1
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#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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/* No additional registers to save, so this macro does nothing. */
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.endm
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/* Restore the additional registers found on the Pulpino. */
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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/* No additional registers to restore, so this macro does nothing. */
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.endm
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -44,7 +44,7 @@
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* regiters.
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* registers.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
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@ -62,12 +62,49 @@
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#define portasmHAS_CLINT 0
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/* Constants to define the additional registers found on the Pulpino RI5KY. */
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#define lpstart0 0x7b0
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#define lpend0 0x7b1
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#define lpcount0 0x7b2
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#define lpstart1 0x7b4
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#define lpend1 0x7b5
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#define lpcount1 0x7b6
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/* Six additional registers to save and restore, as per the #defines above. */
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#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
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/* Save additional registers found on the Pulpino. */
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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addi sp, sp, -portasmADDITIONAL_CONTEXT_SIZE /* Make room for the additional registers. */
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csrr t0, lpstart0 /* Load additional registers into accessable temporary registers. */
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csrr t1, lpend0
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csrr t2, lpcount0
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csrr t3, lpstart1
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csrr t4, lpend1
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csrr t5, lpcount1
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sw t0, 1 * portWORD_SIZE( sp )
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sw t1, 2 * portWORD_SIZE( sp )
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sw t2, 3 * portWORD_SIZE( sp )
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sw t3, 4 * portWORD_SIZE( sp )
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sw t4, 5 * portWORD_SIZE( sp )
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sw t5, 6 * portWORD_SIZE( sp )
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.endm
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/* Restore the additional registers found on the Pulpino. */
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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/* This file is for use with chips that do not add to the standard RISC-V
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* register set, so there is nothing to do here. */
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lw t0, 1 * portWORD_SIZE( sp ) /* Load additional registers into accessable temporary registers. */
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lw t1, 2 * portWORD_SIZE( sp )
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lw t2, 3 * portWORD_SIZE( sp )
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lw t3, 4 * portWORD_SIZE( sp )
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lw t4, 5 * portWORD_SIZE( sp )
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lw t5, 6 * portWORD_SIZE( sp )
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csrw lpstart0, t0
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csrw lpend0, t1
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csrw lpcount0, t2
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csrw lpstart1, t3
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csrw lpend1, t4
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csrw lpcount1, t5
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addi sp, sp, -portasmADDITIONAL_CONTEXT_SIZE /* Remove space added for additional registers. */
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.endm
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -34,13 +34,28 @@
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#include "task.h"
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#include "portmacro.h"
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#ifdef configISR_STACK_SIZE
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/* The stack used by interrupt service routines. */
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static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
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const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 1 ] );
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/* Let the user override the pre-loading of the initial LR with the address of
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prvTaskExitError() in case it messes up unwinding of the stack in the
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debugger. */
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#ifdef configTASK_RETURN_ADDRESS
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#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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#else
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#define portTASK_RETURN_ADDRESS prvTaskExitError
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#endif
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/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
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to use a statically allocated array as the interrupt stack. Alternative leave
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configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
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linker variable names __freertos_irq_stack_top has the same value as the top
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of the stack used by main. Using the linker script method will repurpose the
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stack that was used by main before the scheduler was started for use as the
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interrupt stack after the scheduler has started. */
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#ifdef configISR_STACK_SIZE_WORDS
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static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
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const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ ( configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ) - 1 ] );
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#else
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extern const uint32_t __freertos_irq_stack_top[];
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const uint32_t xISRStackTop = ( uint32_t ) __freertos_irq_stack_top;
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const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
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#endif
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/*
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@ -89,10 +104,10 @@ task stack, not the ISR stack). */
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/*-----------------------------------------------------------*/
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void prvTaskExitError( void )
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static void prvTaskExitError( void )
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{
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volatile uint32_t ulx = 0;
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#warning Not currently used
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/* A function that implements a task must not exit or attempt to return to
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its caller as there is nothing to return to. If a task wants to exit it
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should instead call vTaskDelete( NULL ).
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@ -105,107 +120,6 @@ volatile uint32_t ulx = 0;
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}
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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{
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uint32_t mstatus;
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const uint32_t ulMPIE_Bit = 0x80, ulMPP_Bits = 0x1800;
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/*
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X1 to X31 integer registers for the 'I' profile, X1 to X15 for the 'E' profile.
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Register ABI Name Description Saver
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x0 zero Hard-wired zero -
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x1 ra Return address Caller
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x2 sp Stack pointer Callee
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x3 gp Global pointer -
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x4 tp Thread pointer -
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x5-7 t0-2 Temporaries Caller
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x8 s0/fp Saved register/Frame pointer Callee
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x9 s1 Saved register Callee
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x10-11 a0-1 Function Arguments/return values Caller
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x12-17 a2-7 Function arguments Caller
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x18-27 s2-11 Saved registers Callee
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x28-31 t3-6 Temporaries Caller
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*/
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/* Start task with interrupt enabled. */
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__asm volatile ("csrr %0, mstatus" : "=r"(mstatus));
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mstatus |= ulMPIE_Bit | ulMPP_Bits;
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pxTopOfStack--;
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*pxTopOfStack = mstatus;
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/* Numbers correspond to the x register number. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 31;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 30;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 29;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 28;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 27;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 26;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 25;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 24;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 23;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 22;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 21;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 20;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 19;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 18;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 17;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 16;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 15;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 14;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 13;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 12;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 11;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pvParameters;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 9;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 8;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 7;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 6;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 5;
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pxTopOfStack--;
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// *pxTopOfStack = ( StackType_t ) 4; /* Thread pointer. */
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// pxTopOfStack--;
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// *pxTopOfStack = ( StackType_t ) 3; /* Global pointer. */
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// pxTopOfStack--;
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// *pxTopOfStack = ( StackType_t ) 2; /* Stack pointer. */
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// pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) prvTaskExitError;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode;
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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#if( configCLINT_BASE_ADDRESS != 0 )
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void vPortSetupTimerInterrupt( void )
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@ -25,6 +25,15 @@
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* 1 tab == 4 spaces!
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*/
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#if __riscv_xlen == 64
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#error Not implemented yet - change lw to ld, and sw to sd.
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#define portWORD_SIZE 8
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#elif __riscv_xlen == 32
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#define portWORD_SIZE 4
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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@ -42,7 +51,7 @@
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* regiters.
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* registers.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
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@ -67,27 +76,6 @@ definitions. */
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#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_port_specific_extensions.h header file.
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#endif
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#ifndef portasmSAVE_ADDITIONAL_REGISTERS
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/* portasmSAVE_ADDITIONAL_REGISTERS is not defined so assume no additional
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registers need to be saved. */
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#define portasmSAVE_ADDITIONAL_REGISTERS
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#endif
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#ifndef portasmRESTORE_ADDITIONAL_REGISTERS
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/* portasmRESTORE_ADDITIONAL_REGISTERS is not defined so assume no
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additional registers need to be restored. */
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#define portasmRESTORE_ADDITIONAL_REGISTERS
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#endif
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#if __riscv_xlen == 64
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#error Not implemented yet - change lw to ld, and sw to sd.
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#define portWORD_SIZE 8
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#elif __riscv_xlen == 32
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#define portWORD_SIZE 4
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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/* Only the standard core registers are stored by default. Any additional
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registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
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portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
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@ -97,6 +85,7 @@ at the top of this file. */
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.global xPortStartFirstTask
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.global vFreeRTOSPortTrapHandler
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.global pxPortInitialiseStack
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.extern pxCurrentTCB
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.extern ulPortTrapHandler
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.extern vTaskSwitchContext
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@ -105,11 +94,11 @@ at the top of this file. */
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.extern pullNextTime
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.extern ulTimerIncrementsForOneTick
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.extern xISRStackTop
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.extern vPortHandleInterrupt
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/*-----------------------------------------------------------*/
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.align 16
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.align 8
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.func
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vFreeRTOSPortTrapHandler:
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addi sp, sp, -portCONTEXT_SIZE
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sw x1, 1 * portWORD_SIZE( sp )
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@ -141,11 +130,11 @@ vFreeRTOSPortTrapHandler:
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sw x30, 27 * portWORD_SIZE( sp )
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sw x31, 28 * portWORD_SIZE( sp )
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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csrr t0, mstatus /* Required for MPIE bit. */
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sw t0, 29 * portWORD_SIZE( sp )
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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sw sp, 0( t0 ) /* Write sp to first TCB member. */
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@ -217,16 +206,16 @@ processed_source:
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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/* Load mret with the address of the next task. */
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/* Load mret with the address of the next instruction in the task to run next. */
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lw t0, 0( sp )
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csrw mepc, t0
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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/* Load mstatus with the interrupt enable bits used by the task. */
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lw t0, 29 * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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lw x1, 1 * portWORD_SIZE( sp )
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lw x5, 2 * portWORD_SIZE( sp ) /* t0 */
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lw x6, 3 * portWORD_SIZE( sp ) /* t1 */
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@ -255,12 +244,14 @@ processed_source:
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lw x29, 26 * portWORD_SIZE( sp ) /* t4 */
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lw x30, 27 * portWORD_SIZE( sp ) /* t5 */
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lw x31, 28 * portWORD_SIZE( sp ) /* t6 */
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addi sp, sp, portCONTEXT_SIZE
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addi sp, sp, portCONTEXT_SIZE
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mret
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.endfunc
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/*-----------------------------------------------------------*/
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.align 16
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.align 8
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.func
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xPortStartFirstTask:
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#if( portasmHAS_CLINT != 0 )
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@ -275,6 +266,12 @@ xPortStartFirstTask:
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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|
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
|
||||
|
||||
lw t0, 29 * portWORD_SIZE( sp ) /* mstatus */
|
||||
csrrw x0, mstatus, t0 /* Interrupts enabled from here! */
|
||||
|
||||
lw x5, 2 * portWORD_SIZE( sp ) /* t0 */
|
||||
lw x6, 3 * portWORD_SIZE( sp ) /* t1 */
|
||||
lw x7, 4 * portWORD_SIZE( sp ) /* t2 */
|
||||
|
|
@ -303,8 +300,98 @@ xPortStartFirstTask:
|
|||
lw x30, 27 * portWORD_SIZE( sp ) /* t5 */
|
||||
lw x31, 28 * portWORD_SIZE( sp ) /* t6 */
|
||||
addi sp, sp, portCONTEXT_SIZE
|
||||
csrs mstatus, 8 /* Enable machine interrupts. */
|
||||
ret
|
||||
|
||||
.endfunc
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Unlike other ports pxPortInitialiseStack() is written in assembly code as it
|
||||
* needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
|
||||
* for the function is as per the other ports:
|
||||
* StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
|
||||
*
|
||||
* As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
|
||||
* a1, and pvParameters in a2. The new top of stack is passed out in a0.
|
||||
*
|
||||
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
|
||||
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
|
||||
*
|
||||
* Register ABI Name Description Saver
|
||||
* x0 zero Hard-wired zero -
|
||||
* x1 ra Return address Caller
|
||||
* x2 sp Stack pointer Callee
|
||||
* x3 gp Global pointer -
|
||||
* x4 tp Thread pointer -
|
||||
* x5-7 t0-2 Temporaries Caller
|
||||
* x8 s0/fp Saved register/Frame pointer Callee
|
||||
* x9 s1 Saved register Callee
|
||||
* x10-11 a0-1 Function Arguments/return values Caller
|
||||
* x12-17 a2-7 Function arguments Caller
|
||||
* x18-27 s2-11 Saved registers Callee
|
||||
* x28-31 t3-6 Temporaries Caller
|
||||
*
|
||||
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
|
||||
* where the global and thread pointers are currently assumed to be constant so
|
||||
* are not saved:
|
||||
*
|
||||
* mstatus
|
||||
* x31
|
||||
* x30
|
||||
* x29
|
||||
* x28
|
||||
* x27
|
||||
* x26
|
||||
* x25
|
||||
* x24
|
||||
* x23
|
||||
* x22
|
||||
* x21
|
||||
* x20
|
||||
* x19
|
||||
* x18
|
||||
* x17
|
||||
* x16
|
||||
* x15
|
||||
* x14
|
||||
* x13
|
||||
* x12
|
||||
* x11
|
||||
* pvParameters
|
||||
* x9
|
||||
* x8
|
||||
* x7
|
||||
* x6
|
||||
* x5
|
||||
* portTASK_RETURN_ADDRESS
|
||||
* pxCode
|
||||
*/
|
||||
.align 8
|
||||
.func
|
||||
pxPortInitialiseStack:
|
||||
|
||||
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
|
||||
|
||||
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
|
||||
beq t0, x0, standard_stack_frame /* No more chip specific registers to save. */
|
||||
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
|
||||
sw x0, 0(a0) /* Give the chip specific register an initial value of zero. */
|
||||
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
|
||||
j chip_specific_stack_frame /* Until no more chip specific registers. */
|
||||
|
||||
standard_stack_frame: /* Now create the stack frame for the standard registers. */
|
||||
csrr t0, mstatus /* Obtain current mstatus value. */
|
||||
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
|
||||
slli t1, t1, 4
|
||||
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
|
||||
|
||||
addi a0, a0, -portWORD_SIZE
|
||||
sw t0, 0(a0) /* mstatus onto the stack. */
|
||||
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
|
||||
sw a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
|
||||
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
|
||||
sw x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
|
||||
addi a0, a0, -portWORD_SIZE
|
||||
sw a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
|
||||
ret
|
||||
.endfunc
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
Loading…
Reference in a new issue