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Microblaze port: Place critical section around XIntc_Enable() to protect read/modify/write operation performed inside the library.

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This commit is contained in:
Richard Barry 2018-01-30 17:42:12 +00:00
parent 208cc18a90
commit 7ddb8b342d
2 changed files with 10 additions and 4 deletions
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2
FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c
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@ -210,7 +210,7 @@ portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
static void prvTxHandler( void *pvUnused, unsigned portBASE_TYPE uxUnused )
{
BaseType_t xHigherPriorityTaskWoken = NULL;
BaseType_t xHigherPriorityTaskWoken = ( BaseType_t ) NULL;
( void ) pvUnused;
( void ) uxUnused;

12
FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
View file

@ -47,7 +47,7 @@ the scheduler being commenced interrupts should not be enabled, so the critical
nesting variable is initialised to a non-zero value. */
#define portINITIAL_NESTING_VALUE ( 0xff )
/* The bit within the MSR register that enabled/disables interrupts and
/* The bit within the MSR register that enabled/disables interrupts and
exceptions respectively. */
#define portMSR_IE ( 0x02U )
#define portMSR_EE ( 0x100U )
@ -131,7 +131,7 @@ extern void _start1( void );
disabled. Each task will enable interrupts automatically when it enters
the running state for the first time. */
*pxTopOfStack = mfmsr() & ~portMSR_IE;
#if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
{
/* Ensure exceptions are enabled for the task. */
@ -305,7 +305,13 @@ int32_t lReturn;
lReturn = prvEnsureInterruptControllerIsInitialised();
if( lReturn == pdPASS )
{
XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
/* Critical section protects read/modify/writer operation inside
XIntc_Enable(). */
portENTER_CRITICAL();
{
XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
}
portEXIT_CRITICAL();
}
configASSERT( lReturn );