Gaurav Aggarwal
b9e379951a
Do not strip required symbols when LTO is on
...
Link time optimization was stripping off some symbols which were
accessed from assembly code.
2019-05-09 22:04:29 +00:00
Gaurav Aggarwal
ae448fc952
Add Cortex M23 GCC and IAR ports. Add demo projects for Nuvoton NuMaker-PFM-2351.
2019-05-02 21:08:28 +00:00
Richard Barry
079d081346
Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit.
2019-04-29 00:57:14 +00:00
Richard Barry
27ca5c8341
Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM Cortex-M33 ports to assist with link time optimisation.
2019-04-25 19:49:50 +00:00
Richard Barry
84377442fc
Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation.
2019-04-21 20:15:34 +00:00
Richard Barry
606845492b
Fix potential memory leak in the Win32 FreeRTOS+TCP network interface initialisation sequence.
...
Introduce portMEMORY_BARRIER() macro to assist with memory access ordering when suspending the scheduler if link time optimization is used.
2019-04-17 17:16:04 +00:00
Gaurav Aggarwal
dd9a9710c6
Export port architecture name for COrtex-M33. This can be used by debuggers to find the port in-use to be able to correctly decode the context stored on the stack.
2019-03-28 00:00:46 +00:00
Gaurav Aggarwal
ba39a958b5
Fix spelling of priority in comments.
2019-03-18 23:28:03 +00:00
Richard Barry
2265d70499
Correcting spelling mistakes in comments only.
2019-03-08 17:30:49 +00:00
Richard Barry
06596c3192
Prepare the RISC-V port layer for addition of 64-bit port.
2019-03-08 17:03:43 +00:00
Gaurav Aggarwal
5623c69748
Fix Build and Links failure in MPU projects. Minor cosmetic changes in some V8M files.
2019-02-20 20:27:07 +00:00
Richard Barry
8b6ab5f197
Add instructions on building the Cortex-M33 secure and non secure projects into the comments of that project and into a readme.txt file.
...
Enable configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES setting to be used in statically allocated systems.
2019-02-20 17:55:59 +00:00
Gaurav Aggarwal
5849459c65
Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change spaces to tabs.
2019-02-20 00:25:45 +00:00
Gaurav Aggarwal
ce576f3683
First Official Release of ARMV8M Support. This release removes Pre-Release from all the ARMv8M files licensees.
2019-02-19 02:30:32 +00:00
Richard Barry
58ba10eee8
Update version number in readiness for V10.2.0 release.
2019-02-17 22:36:16 +00:00
Richard Barry
6844bef74f
Replace the pdf RISC-V documentation with links to the documentation web pages.
2019-02-16 01:15:33 +00:00
Richard Barry
b2b1b09ea5
Fix bug in core_cm3.c atomic macros.
...
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
2019-02-16 01:08:38 +00:00
Richard Barry
fb73829148
Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState().
...
Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
2019-02-08 01:18:08 +00:00
Richard Barry
df5952f655
Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations.
2019-01-21 23:39:48 +00:00
Richard Barry
11d9c440b8
Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason).
...
Add a project for the Vega board's RI5CY core.
2018-12-31 18:19:52 +00:00
Richard Barry
e2af102c80
Re-org of RISC-V file structure and naming step 2.
2018-12-30 23:53:47 +00:00
Richard Barry
818eeccc0c
Re-org of RISC-V file structure and naming step 1.
2018-12-30 23:20:26 +00:00
Richard Barry
db750d0c82
Update RSIC-V port layer after testing saving and receiving of chip specific registers.
2018-12-30 23:11:40 +00:00
Richard Barry
60b133b2c6
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
2018-12-30 20:00:43 +00:00
Richard Barry
d369110167
Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings.
...
Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
2018-12-28 00:44:18 +00:00
Richard Barry
ce36928ea8
Rename directories in the RISC-V port.
2018-12-24 17:37:02 +00:00
Richard Barry
101806906d
Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT.
2018-12-16 23:59:49 +00:00
Richard Barry
7cc42b2ab6
Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
...
+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
2018-12-16 20:21:29 +00:00
Richard Barry
65f7a2dc19
Update RISC-V port to use a separate interrupt stack.
2018-12-04 01:23:41 +00:00
Richard Barry
e85ea96f78
Some efficiency improvements in Risc-V port.
2018-11-28 19:35:40 +00:00
Richard Barry
dc99300fa9
First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.
2018-11-24 20:59:07 +00:00
Richard Barry
db64297487
Provide each Risc V task with an initial mstatus register value.
2018-11-20 20:12:35 +00:00
Richard Barry
8cef339aec
Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.
2018-11-19 06:01:29 +00:00
Richard Barry
baee711cb6
Continue work on Risc V port.
2018-11-06 02:04:28 +00:00
Richard Barry
e3dc5e934b
RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet.
2018-09-27 17:25:17 +00:00
Richard Barry
2bcb1ab02b
Add trap handler to RISC-V port so there is no dependency on third party code.
2018-09-23 03:52:23 +00:00
Richard Barry
32f35e9130
RISC-V:
...
Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
2018-09-12 16:33:05 +00:00
Richard Barry
b11eb3a59c
RISC-V work in progress:
...
+ Initialise task stack.
+ Successfully jump to start of first task.
2018-09-10 20:50:05 +00:00
Richard Barry
92ae8e7aff
Update version numbers ready for release.
2018-09-07 18:13:20 +00:00
Richard Barry
3a1631fda3
Update copyright date ready for tagging V10.1.0.
2018-08-22 23:23:03 +00:00
Richard Barry
fb9de58f56
Update version numbers in preparation for a new release.
2018-08-21 19:50:48 +00:00
Richard Barry
f6cbf20019
Update RISC-V project to used official port stubs in place of third party port.
2018-07-07 21:54:41 +00:00
Richard Barry
3bfc32d444
Add stubs for official RISC-V RV32 port.
2018-07-07 21:47:31 +00:00
Richard Barry
5bebf10fa4
Minor updates to comments only.
2018-05-17 17:50:14 +00:00
Richard Barry
7ddb8b342d
Microblaze port: Place critical section around XIntc_Enable() to protect read/modify/write operation performed inside the library.
2018-01-30 17:42:12 +00:00
Richard Barry
13651934be
Roll up the minor changes checked into svn since V10.0.0 into new V10.0.1 ready for release.
2017-12-18 22:54:18 +00:00
Richard Barry
cfc268814a
Update to MIT licensed FreeRTOS V10.0.0 - see https://www.freertos.org/History.txt
2017-11-29 16:53:26 +00:00
Richard Barry
037abdddf2
Update TriCore port to work with latest GCC compiler.
2017-08-09 16:57:35 +00:00
Richard Barry
6eea3d8d4b
Correct long time mis-spelled portINITIAL_EXEC_RETURN to portINITIAL_EXC_RETURN
2017-05-30 00:36:09 +00:00
Richard Barry
b080f13543
Add more "memory" clobbers into the MPU ports to make them robust to more aggressive optimisation in newer GCC version.
2017-04-10 01:58:01 +00:00
