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https://github.com/Rockbox/rockbox.git
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93 lines
4.7 KiB
C
93 lines
4.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* cortex_m7 version: 1.0
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* cortex_m7 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __ARM_CORTEX_M_SCB_H__
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#define __ARM_CORTEX_M_SCB_H__
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#include "macro.h"
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#define REG_SCB_VTOR cm_reg(SCB_VTOR)
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#define CMA_SCB_VTOR (0xe000e000 + 0xd08)
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#define CMT_SCB_VTOR CMIO_32_RW
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#define CMN_SCB_VTOR SCB_VTOR
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#define REG_SCB_CCR cm_reg(SCB_CCR)
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#define CMA_SCB_CCR (0xe000e000 + 0xd14)
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#define CMT_SCB_CCR CMIO_32_RW
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#define CMN_SCB_CCR SCB_CCR
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#define BP_SCB_CCR_BP 18
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#define BM_SCB_CCR_BP 0x40000
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#define BF_SCB_CCR_BP(v) (((v) & 0x1) << 18)
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#define BFM_SCB_CCR_BP(v) BM_SCB_CCR_BP
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#define BF_SCB_CCR_BP_V(e) BF_SCB_CCR_BP(BV_SCB_CCR_BP__##e)
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#define BFM_SCB_CCR_BP_V(v) BM_SCB_CCR_BP
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#define BP_SCB_CCR_IC 17
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#define BM_SCB_CCR_IC 0x20000
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#define BF_SCB_CCR_IC(v) (((v) & 0x1) << 17)
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#define BFM_SCB_CCR_IC(v) BM_SCB_CCR_IC
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#define BF_SCB_CCR_IC_V(e) BF_SCB_CCR_IC(BV_SCB_CCR_IC__##e)
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#define BFM_SCB_CCR_IC_V(v) BM_SCB_CCR_IC
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#define BP_SCB_CCR_DC 16
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#define BM_SCB_CCR_DC 0x10000
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#define BF_SCB_CCR_DC(v) (((v) & 0x1) << 16)
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#define BFM_SCB_CCR_DC(v) BM_SCB_CCR_DC
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#define BF_SCB_CCR_DC_V(e) BF_SCB_CCR_DC(BV_SCB_CCR_DC__##e)
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#define BFM_SCB_CCR_DC_V(v) BM_SCB_CCR_DC
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#define BP_SCB_CCR_STKALIGN 9
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#define BM_SCB_CCR_STKALIGN 0x200
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#define BF_SCB_CCR_STKALIGN(v) (((v) & 0x1) << 9)
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#define BFM_SCB_CCR_STKALIGN(v) BM_SCB_CCR_STKALIGN
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#define BF_SCB_CCR_STKALIGN_V(e) BF_SCB_CCR_STKALIGN(BV_SCB_CCR_STKALIGN__##e)
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#define BFM_SCB_CCR_STKALIGN_V(v) BM_SCB_CCR_STKALIGN
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#define BP_SCB_CCR_BFHFNMIGN 8
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#define BM_SCB_CCR_BFHFNMIGN 0x100
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#define BF_SCB_CCR_BFHFNMIGN(v) (((v) & 0x1) << 8)
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#define BFM_SCB_CCR_BFHFNMIGN(v) BM_SCB_CCR_BFHFNMIGN
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#define BF_SCB_CCR_BFHFNMIGN_V(e) BF_SCB_CCR_BFHFNMIGN(BV_SCB_CCR_BFHFNMIGN__##e)
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#define BFM_SCB_CCR_BFHFNMIGN_V(v) BM_SCB_CCR_BFHFNMIGN
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#define BP_SCB_CCR_DIV_0_TRP 4
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#define BM_SCB_CCR_DIV_0_TRP 0x10
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#define BF_SCB_CCR_DIV_0_TRP(v) (((v) & 0x1) << 4)
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#define BFM_SCB_CCR_DIV_0_TRP(v) BM_SCB_CCR_DIV_0_TRP
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#define BF_SCB_CCR_DIV_0_TRP_V(e) BF_SCB_CCR_DIV_0_TRP(BV_SCB_CCR_DIV_0_TRP__##e)
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#define BFM_SCB_CCR_DIV_0_TRP_V(v) BM_SCB_CCR_DIV_0_TRP
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#define BP_SCB_CCR_UNALIGN_TRP 3
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#define BM_SCB_CCR_UNALIGN_TRP 0x8
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#define BF_SCB_CCR_UNALIGN_TRP(v) (((v) & 0x1) << 3)
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#define BFM_SCB_CCR_UNALIGN_TRP(v) BM_SCB_CCR_UNALIGN_TRP
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#define BF_SCB_CCR_UNALIGN_TRP_V(e) BF_SCB_CCR_UNALIGN_TRP(BV_SCB_CCR_UNALIGN_TRP__##e)
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#define BFM_SCB_CCR_UNALIGN_TRP_V(v) BM_SCB_CCR_UNALIGN_TRP
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#define BP_SCB_CCR_USERETMPEND 1
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#define BM_SCB_CCR_USERETMPEND 0x2
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#define BF_SCB_CCR_USERETMPEND(v) (((v) & 0x1) << 1)
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#define BFM_SCB_CCR_USERETMPEND(v) BM_SCB_CCR_USERETMPEND
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#define BF_SCB_CCR_USERETMPEND_V(e) BF_SCB_CCR_USERETMPEND(BV_SCB_CCR_USERETMPEND__##e)
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#define BFM_SCB_CCR_USERETMPEND_V(v) BM_SCB_CCR_USERETMPEND
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#define BP_SCB_CCR_NONBASETHRDENA 0
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#define BM_SCB_CCR_NONBASETHRDENA 0x1
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#define BF_SCB_CCR_NONBASETHRDENA(v) (((v) & 0x1) << 0)
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#define BFM_SCB_CCR_NONBASETHRDENA(v) BM_SCB_CCR_NONBASETHRDENA
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#define BF_SCB_CCR_NONBASETHRDENA_V(e) BF_SCB_CCR_NONBASETHRDENA(BV_SCB_CCR_NONBASETHRDENA__##e)
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#define BFM_SCB_CCR_NONBASETHRDENA_V(v) BM_SCB_CCR_NONBASETHRDENA
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#endif /* __ARM_CORTEX_M_SCB_H__*/
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