/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * cortex_m7 version: 1.0
 * cortex_m7 authors: Aidan MacDonald
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __ARM_CORTEX_M_SCB_H__
#define __ARM_CORTEX_M_SCB_H__

#include "macro.h"

#define REG_SCB_VTOR    cm_reg(SCB_VTOR)
#define CMA_SCB_VTOR    (0xe000e000 + 0xd08)
#define CMT_SCB_VTOR    CMIO_32_RW
#define CMN_SCB_VTOR    SCB_VTOR

#define REG_SCB_CCR                     cm_reg(SCB_CCR)
#define CMA_SCB_CCR                     (0xe000e000 + 0xd14)
#define CMT_SCB_CCR                     CMIO_32_RW
#define CMN_SCB_CCR                     SCB_CCR
#define BP_SCB_CCR_BP                   18
#define BM_SCB_CCR_BP                   0x40000
#define BF_SCB_CCR_BP(v)                (((v) & 0x1) << 18)
#define BFM_SCB_CCR_BP(v)               BM_SCB_CCR_BP
#define BF_SCB_CCR_BP_V(e)              BF_SCB_CCR_BP(BV_SCB_CCR_BP__##e)
#define BFM_SCB_CCR_BP_V(v)             BM_SCB_CCR_BP
#define BP_SCB_CCR_IC                   17
#define BM_SCB_CCR_IC                   0x20000
#define BF_SCB_CCR_IC(v)                (((v) & 0x1) << 17)
#define BFM_SCB_CCR_IC(v)               BM_SCB_CCR_IC
#define BF_SCB_CCR_IC_V(e)              BF_SCB_CCR_IC(BV_SCB_CCR_IC__##e)
#define BFM_SCB_CCR_IC_V(v)             BM_SCB_CCR_IC
#define BP_SCB_CCR_DC                   16
#define BM_SCB_CCR_DC                   0x10000
#define BF_SCB_CCR_DC(v)                (((v) & 0x1) << 16)
#define BFM_SCB_CCR_DC(v)               BM_SCB_CCR_DC
#define BF_SCB_CCR_DC_V(e)              BF_SCB_CCR_DC(BV_SCB_CCR_DC__##e)
#define BFM_SCB_CCR_DC_V(v)             BM_SCB_CCR_DC
#define BP_SCB_CCR_STKALIGN             9
#define BM_SCB_CCR_STKALIGN             0x200
#define BF_SCB_CCR_STKALIGN(v)          (((v) & 0x1) << 9)
#define BFM_SCB_CCR_STKALIGN(v)         BM_SCB_CCR_STKALIGN
#define BF_SCB_CCR_STKALIGN_V(e)        BF_SCB_CCR_STKALIGN(BV_SCB_CCR_STKALIGN__##e)
#define BFM_SCB_CCR_STKALIGN_V(v)       BM_SCB_CCR_STKALIGN
#define BP_SCB_CCR_BFHFNMIGN            8
#define BM_SCB_CCR_BFHFNMIGN            0x100
#define BF_SCB_CCR_BFHFNMIGN(v)         (((v) & 0x1) << 8)
#define BFM_SCB_CCR_BFHFNMIGN(v)        BM_SCB_CCR_BFHFNMIGN
#define BF_SCB_CCR_BFHFNMIGN_V(e)       BF_SCB_CCR_BFHFNMIGN(BV_SCB_CCR_BFHFNMIGN__##e)
#define BFM_SCB_CCR_BFHFNMIGN_V(v)      BM_SCB_CCR_BFHFNMIGN
#define BP_SCB_CCR_DIV_0_TRP            4
#define BM_SCB_CCR_DIV_0_TRP            0x10
#define BF_SCB_CCR_DIV_0_TRP(v)         (((v) & 0x1) << 4)
#define BFM_SCB_CCR_DIV_0_TRP(v)        BM_SCB_CCR_DIV_0_TRP
#define BF_SCB_CCR_DIV_0_TRP_V(e)       BF_SCB_CCR_DIV_0_TRP(BV_SCB_CCR_DIV_0_TRP__##e)
#define BFM_SCB_CCR_DIV_0_TRP_V(v)      BM_SCB_CCR_DIV_0_TRP
#define BP_SCB_CCR_UNALIGN_TRP          3
#define BM_SCB_CCR_UNALIGN_TRP          0x8
#define BF_SCB_CCR_UNALIGN_TRP(v)       (((v) & 0x1) << 3)
#define BFM_SCB_CCR_UNALIGN_TRP(v)      BM_SCB_CCR_UNALIGN_TRP
#define BF_SCB_CCR_UNALIGN_TRP_V(e)     BF_SCB_CCR_UNALIGN_TRP(BV_SCB_CCR_UNALIGN_TRP__##e)
#define BFM_SCB_CCR_UNALIGN_TRP_V(v)    BM_SCB_CCR_UNALIGN_TRP
#define BP_SCB_CCR_USERETMPEND          1
#define BM_SCB_CCR_USERETMPEND          0x2
#define BF_SCB_CCR_USERETMPEND(v)       (((v) & 0x1) << 1)
#define BFM_SCB_CCR_USERETMPEND(v)      BM_SCB_CCR_USERETMPEND
#define BF_SCB_CCR_USERETMPEND_V(e)     BF_SCB_CCR_USERETMPEND(BV_SCB_CCR_USERETMPEND__##e)
#define BFM_SCB_CCR_USERETMPEND_V(v)    BM_SCB_CCR_USERETMPEND
#define BP_SCB_CCR_NONBASETHRDENA       0
#define BM_SCB_CCR_NONBASETHRDENA       0x1
#define BF_SCB_CCR_NONBASETHRDENA(v)    (((v) & 0x1) << 0)
#define BFM_SCB_CCR_NONBASETHRDENA(v)   BM_SCB_CCR_NONBASETHRDENA
#define BF_SCB_CCR_NONBASETHRDENA_V(e)  BF_SCB_CCR_NONBASETHRDENA(BV_SCB_CCR_NONBASETHRDENA__##e)
#define BFM_SCB_CCR_NONBASETHRDENA_V(v) BM_SCB_CCR_NONBASETHRDENA

#endif /* __ARM_CORTEX_M_SCB_H__*/