Normally the bootloader won't enable the LCD, but we
still want to call lcd_init() at startup to keep the
code simple.
Change-Id: I866ecd7c81b6c5e6acdd57f5d7680400df3f54f4
The clock helpers are only used for leaf clocks of single
peripherals, which don't benefit from reference counting.
Change-Id: Ica5685e7bc0fce621ae46f758f0ad0b1dcfb2789
Make systick setup less hardcoded, and create a public API
for use by targets, in preparation for moving system_init()
into target-specific code.
Improve the implementation of udelay to make it more robust
against timer wraparound.
Change-Id: I21bb8821cfd1d7e4049fac6e6a4548d80a4276f7
This is mainly useful for bootloaders that want to safely
disable the SD/MMC controller before booting. Disabling a
controller will reset and power down the bus; all attempts
to read or write to a disabled controller will fail.
Change-Id: I4a7ec4287f2b8510a35d964cc806c74be8c86406
FIFO errors shouldn't be possible with hardware flow
control enabled. DMA errors shouldn't occur unless a
bad memory address was passed.
Don't bother checking for ITCM/DTCM in the transfer
setup and instead just wait for the IDMATE error; if
the RM0433 reference manual is to be believed then
SDMMC1 _only_ has access to AXI bus memories, and
checking for all invalid destinations would be very
verbose.
Change-Id: I2b22b56009933e16c5adde4d36b7a906cee57791
Hardware flow control prevents FIFO underruns/overruns
by stopping the bus clock if one would occur. This can
slow down transfers, but that's better than having data
transfer fail due to AXI/AHB bus contention.
Change-Id: I8696d3aff78c17dbbe85907160fa37fd4ee11e85
The following inline assembly in set_irq_level() turned out
to have incorrect constraints:
int newvalue = /* input parameter */;
int oldvalue;
asm volatile ("mrs %0, primask\n"
"msr primask, %1\n"
: "=r"(oldvalue) : "r"(newvalue));
leading to incorrect code generation for common cases like
disable_irq_save(), which compiles to:
mov r5, #1
mrs r5, primask
msr primask, r5
...which doesn't disable IRQs at all, since both of the
operands got assigned to the same register; the write of
'oldvalue' clobbers the 'newvalue' input before it's used.
Apparently GCC assumes that input operands are read before
output operands are written. One way to fix this is adding
the '&' constraint: "=&r"(oldvalue), but it's better to
break things down into separate, simpler asm statements
which GCC can figure out itself.
Also add compiler memory barriers where primask is modified
to ensure loads/stores aren't incorrectly moved outside of
critical sections.
While here, optimize disable_irq_save() a bit by using the
cpsid instruction, which avoids the extra "mov" and register
allocation needed by "msr primask".
Change-Id: Iac94a76db5bac399a1cf028da4241a0473259a46
This enables deeper sleep. On touchscreen devices (HiBy R1) it shuts down both screen and touch (touchscreen needs few seconds before it's actually disabled)
Change-Id: I5e8a7dae840227ddf4433daa461cc7124db7676a
While the binary firmware build succeeded, the 'make zip' process failed
because the script that put the default wps image together runs the
device config header through CPP while only looking into the
configuration header directory.
So move the imx233-config.h header out of the target/arm/imx233 and into
export/config where everything is copacetic.
Change-Id: I9914558a892f8ff7ad839818f0a5ef687cc7b997
3a4da9381e change an underdocumented definition that turns
out to be important, yet not documented in the linux uapi definitions.
Revert that change, and document the magic values so this doesn't happen again.
Change-Id: I0fac4a9d68170920bb5db1018d765e8a2994a95f
Bootloaders don't have support for queue_peek or other advanced
queue functionality, so USB-enabled bootloaders can't play these games.
Change-Id: Ib807b57b84433e7a2ad019648a6c588ab424c6cd
mmc_sleepnow() was accidentally removed from the imx233 sdmmc code,
causing the sansa fuze+ build to fail.
Change-Id: I935f7f4fe99e7353a84dc26e81d85ee55afa0de3
Note that USB current limiting is more or less wishful
thinking; only the charge current is limited, but the
system could easily draw more than 100 mA by itself.
Change-Id: I1083b015f0abea5a39a602ca8d7b142d3613b46b
storage_sleepnow() is the one that is actually implemented
by storage drivers. storage_sleep() sends a Q_STORAGE_SLEEP
event to the storage thread, which will normally end up
calling the driver's sleepnow() function.
Change-Id: Ib6523073348431dcc75c0f10ef99060c6960efd8
For commit-type operations it's useful to be able to pass
unaligned addresses, so round the address/size to ensure
all cache lines in the address range are hit.
Change-Id: Ibb23050ecf11b6ef6ab1dd517990a68ef62ecfa9
Enable high speed USB for the Echo R1. Includes reasonably
complete support for full speed USB on the STM32H743 since
that was necessary to debug why it wasn't working at first
(which turned out to be a bug in memcpy, not a hardware or
driver issue).
Change-Id: Ie713195b22ba88c79b9b0d6eb289cb9ccd2763c2
The "mov lr, pc" instruction doesn't link a proper return
address in Thumb mode: bit 0 will be unset, leading to a
UsageFault exception when returning from the thread's main
function.
Cortex-M has the "blx" instruction to automatically branch
and link the correct return address, so use that.
Change-Id: I4c0ca55b1b2204286343f906f0b53be0c0ddc392
The implementations diverge enough that it is too confusing
to support them in the same source file; split them so it
is easier to understand.
Change-Id: Ic2f91c75e8a9bb605241441f2caed841585f5b87
This supply is shared by the USB PHY and the audio codec,
so it needs to be reference counted to allow them to be
powered up & down independently (and not just leave the
1V8 regulator enabled all the time).
Change-Id: Ib99b41c2a94b9f0c378153b33c6f91b4370ee998
This allows targets to select full speed operation instead
of the default high-speed mode, which is mainly interesting
for debugging USB communication.
Change-Id: I405ff63c6660ca03ea04282a12b59dac06ca46f5
If the PHY doesn't correctly report the ID pin state,
then the DWC2 core may operate in host mode by default.
Defining USB_DW_FORCE_DEVICE_MODE in the target config
will set the FDMOD bit in the GUSBCFG register to force
the core into device mode regardless of what the PHY
reports.
Change-Id: If2391aaa4a7c65ba6c90dd56074faeb3ed1ac2ca
Two cache discards for targets with POST_DMA_FLUSH were
not properly guarded by USB_DW_ARCH_SLAVE, which causes
data loss when DMA is disabled.
Change-Id: If14ffdc5662f77b3ff57a04c5b9f94d4cac7e514
