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arm: handle unaligned addresses in Cortex-M cache ops

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For commit-type operations it's useful to be able to pass
unaligned addresses, so round the address/size to ensure
all cache lines in the address range are hit.

Change-Id: Ibb23050ecf11b6ef6ab1dd517990a68ef62ecfa9
This commit is contained in:
Aidan MacDonald 2026-01-12 23:03:06 +00:00
parent 74d86ab965
commit adb5e2e44f
1 changed files with 4 additions and 2 deletions
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6
firmware/target/arm/cpucache-armv7m.c
View file

@ -19,6 +19,7 @@
*
****************************************************************************/
#include "cpucache-armv7m.h"
#include "system.h"
#include "regs/cortex-m/cm_cache.h"
/*
@ -56,8 +57,9 @@ static inline void range_dcache_op(const void *base, unsigned int size,
{
arm_dsb();
uint32_t addr = (uint32_t)base;
uint32_t endaddr = addr + size;
uint32_t base_addr = (uint32_t)base;
uint32_t addr = CACHEALIGN_DOWN(base_addr);
uint32_t endaddr = CACHEALIGN_UP(base_addr + size);
while (addr < endaddr)
{