len0rd/rockbox
1
0
Fork 1
mirror of https://github.com/Rockbox/rockbox.git synced 2026-04-12 00:47:49 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

echoplayer: replace stm32 clock init with target specific init

Browse source 
Change-Id: Ib858f95b4cedba261ea669d3339ea1497e970982
This commit is contained in:
Aidan MacDonald 2026-01-16 15:31:18 +00:00
parent eea0c128f4
commit 65b97917ca
4 changed files with 11 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

15
firmware/target/arm/stm32/clock-stm32h7.h
View file

@ -36,21 +36,6 @@ struct stm32_clock
uint32_t lpen_bit;
};
/*
* Implemented by the target to initialize all oscillators,
* system, CPU, and bus clocks that need to be enabled from
* early boot.
*/
void stm_target_clock_init(void) INIT_ATTR;
/*
* Called by system_init() to setup target clocks.
*/
static inline void stm_clock_init(void)
{
stm_target_clock_init();
}
/*
* Enables a clock by setting its enable bits in the RCC.
*/

14
firmware/target/arm/stm32/echoplayer/clock-echoplayer.c
View file

@ -32,14 +32,14 @@
/* Flag to use VOS0 */
#define STM32H743_USE_VOS0 (CPU_FREQ > 400000000)
static void init_hse(void)
INIT_ATTR static void init_hse(void)
{
reg_writef(RCC_CR, HSEON(1));
while (!reg_readf(RCC_CR, HSERDY));
}
static void init_pll(void)
INIT_ATTR static void init_pll(void)
{
/* For simplicity, PLL parameters are hardcoded */
_Static_assert(STM32_HSE_FREQ == 24000000,
@ -97,7 +97,7 @@ static void init_pll(void)
while (!reg_readf(RCC_CR, PLL3RDY));
}
static void init_vos(void)
INIT_ATTR static void init_vos(void)
{
reg_writef(PWR_D3CR, VOS_V(VOS1));
while (!reg_readf(PWR_D3CR, VOSRDY));
@ -114,7 +114,7 @@ static void init_vos(void)
}
}
static void init_system_clock(void)
INIT_ATTR static void init_system_clock(void)
{
/* Enable HCLK /2 divider (CPU is at 480 MHz, HCLK limit is 240 MHz) */
reg_writef(RCC_D1CFGR, HPRE(8));
@ -134,7 +134,7 @@ static void init_system_clock(void)
while (reg_readf(FLASH_ACR, LATENCY) != 4);
}
static void init_lse(void)
INIT_ATTR static void init_lse(void)
{
/*
* Skip if LSE and RTC are already enabled.
@ -161,7 +161,7 @@ static void init_lse(void)
reg_writef(PWR_CR1, DBP(0));
}
static void init_periph_clock(void)
INIT_ATTR static void init_periph_clock(void)
{
reg_writef(RCC_D1CCIPR, SDMMCSEL_V(PLL1Q));
reg_writef(RCC_D2CCIP1R, SPI45SEL_V(HSE));
@ -170,7 +170,7 @@ static void init_periph_clock(void)
reg_writef(RCC_AHB3LPENR, AXISRAMEN(1));
}
void stm_target_clock_init(void)
void echoplayer_clock_init(void)
{
init_hse();
init_pll();

2
firmware/target/arm/stm32/echoplayer/clock-echoplayer.h
View file

@ -23,6 +23,8 @@
#include "clock-stm32h7.h"
void echoplayer_clock_init(void) INIT_ATTR;
extern struct stm32_clock sdmmc1_ker_clock;
extern struct stm32_clock ltdc_ker_clock;
extern struct stm32_clock spi5_ker_clock;

4
firmware/target/arm/stm32/echoplayer/system-echoplayer.c
View file

@ -20,8 +20,8 @@
****************************************************************************/
#include "system.h"
#include "button.h"
#include "clock-stm32h7.h"
#include "gpio-stm32h7.h"
#include "clock-echoplayer.h"
#include "regs/stm32h743/fmc.h"
#include "regs/stm32h743/rcc.h"
#include "regs/cortex-m/cm_scb.h"
@ -199,7 +199,7 @@ void system_init(void)
stm32_enable_caches();
/* Initialize system clocks */
stm_clock_init();
echoplayer_clock_init();
/* Enable systick early due to udelay() needed for FMC init */
stm32_systick_enable();