arm: implement get_sp for Cortex-M

On Cortex-M we can just return SP directly, which will return
PSP/MSP depending on the current processor mode.

Note that unwarminder doesn't handle Cortex-M exception frames
yet, so a panic from an interrupt handler will currently stop
at the exception boundary.

Change-Id: I8818126c065c896d781bd52b877965a4094dee2a
This commit is contained in:
Aidan MacDonald 2024-11-14 16:17:30 +00:00 committed by Solomon Peachy
parent 8d5fd1b20b
commit 96b6a7b4e4
2 changed files with 10 additions and 4 deletions

View file

@ -1,8 +1,10 @@
backtrace-unwarminder.c backtrace-unwarminder.c
get_sp.S
unwarm_arm.c unwarm_arm.c
unwarm.c unwarm.c
unwarminder.c unwarminder.c
unwarmmem.c unwarmmem.c
unwarm_thumb.c unwarm_thumb.c
safe_read.S safe_read.S
#if defined(CPU_ARM_CLASSIC)
get_sp.S
#endif

View file

@ -6,14 +6,18 @@
* *
* On RaaA we are called in USER mode most probably and * On RaaA we are called in USER mode most probably and
* cpsr mangling is restricted. We simply copy SP value * cpsr mangling is restricted. We simply copy SP value
* in this situation * in this situation.
*
* For Cortex-M, SP is banked to MSP/PSP based on the current
* processor mode. Exception stack frames can be detected and
* backtraced across, so we can just return SP like RaaA does.
*/ */
.section .text .section .text
.type __get_sp,%function .type __get_sp,%function
.global __get_sp .global __get_sp
__get_sp: __get_sp:
#if (CONFIG_PLATFORM & PLATFORM_NATIVE) #if (CONFIG_PLATFORM & PLATFORM_NATIVE) && defined(CPU_ARM_CLASSIC)
mrs r1, cpsr /* save current state */ mrs r1, cpsr /* save current state */
orr r0, r1, #0xc0 orr r0, r1, #0xc0
msr cpsr_c, r0 /* disable IRQ and FIQ */ msr cpsr_c, r0 /* disable IRQ and FIQ */
@ -28,7 +32,7 @@ call_from_exception:
get_sp: get_sp:
#endif #endif
mov r0, sp /* get SP */ mov r0, sp /* get SP */
#if (CONFIG_PLATFORM & PLATFORM_NATIVE) #if (CONFIG_PLATFORM & PLATFORM_NATIVE) && defined(CPU_ARM_CLASSIC)
msr cpsr_c, r1 /* restore mode */ msr cpsr_c, r1 /* restore mode */
#endif #endif
bx lr bx lr