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96b6a7b4e4
On Cortex-M we can just return SP directly, which will return PSP/MSP depending on the current processor mode. Note that unwarminder doesn't handle Cortex-M exception frames yet, so a panic from an interrupt handler will currently stop at the exception boundary. Change-Id: I8818126c065c896d781bd52b877965a4094dee2a
39 lines
1.4 KiB
ArmAsm
39 lines
1.4 KiB
ArmAsm
#include "config.h"
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/* On native platform we protect ourself by disabling interrupts
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* then we check current processor mode. If we are called
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* from exception we need to save state and switch to SYS and
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* after obtaining SP we restore everything from saved state.
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*
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* On RaaA we are called in USER mode most probably and
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* cpsr mangling is restricted. We simply copy SP value
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* in this situation.
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*
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* For Cortex-M, SP is banked to MSP/PSP based on the current
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* processor mode. Exception stack frames can be detected and
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* backtraced across, so we can just return SP like RaaA does.
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*/
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.section .text
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.type __get_sp,%function
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.global __get_sp
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__get_sp:
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#if (CONFIG_PLATFORM & PLATFORM_NATIVE) && defined(CPU_ARM_CLASSIC)
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mrs r1, cpsr /* save current state */
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orr r0, r1, #0xc0
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msr cpsr_c, r0 /* disable IRQ and FIQ */
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and r0, r1, #0x1f /* get current mode */
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cmp r0, #0x1f /* are we in sys mode? */
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beq get_sp
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call_from_exception:
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mrs r0, spsr /* get saved state */
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and r0, r0, #0x1f /* get mode bits */
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orr r0, r0, #0xc0 /* no FIQ no IRQ */
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msr cpsr_c, r0 /* change mode */
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get_sp:
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#endif
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mov r0, sp /* get SP */
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#if (CONFIG_PLATFORM & PLATFORM_NATIVE) && defined(CPU_ARM_CLASSIC)
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msr cpsr_c, r1 /* restore mode */
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#endif
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bx lr
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.size __get_sp, . - __get_sp
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