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Author SHA1 Message Date
Gaurav Aggarwal ba39a958b5 Fix spelling of priority in comments. 2019-03-18 23:28:03 +00:00
Gaurav Aggarwal 12fb75be37 Fix warning portHAS_STACK_OVERFLOW_CHECKING not defined 
portHAS_STACK_OVERFLOW_CHECKING was getting defined too late before
being used in portable.h for the platforms that do not have stack
overflow checking registers. This commit ensures that it is defined
before it is used.
 2019-03-13 21:10:44 +00:00
Richard Barry 2265d70499 Correcting spelling mistakes in comments only. 2019-03-08 17:30:49 +00:00
Richard Barry 06596c3192 Prepare the RISC-V port layer for addition of 64-bit port. 2019-03-08 17:03:43 +00:00
Gaurav Aggarwal 5fe8465a35 Change type of usStackDepth to configSTACK_DEPTH_TYPE. 2019-02-21 03:25:30 +00:00
Gaurav Aggarwal 5623c69748 Fix Build and Links failure in MPU projects. Minor cosmetic changes in some V8M files. 2019-02-20 20:27:07 +00:00
Richard Barry 8b6ab5f197 Add instructions on building the Cortex-M33 secure and non secure projects into the comments of that project and into a readme.txt file. 
Enable configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES setting to be used in statically allocated systems.
 2019-02-20 17:55:59 +00:00
Gaurav Aggarwal ceeff14524 Set default value of configRUN_FREERTOS_SECURE_ONLY to 0. 2019-02-20 00:40:46 +00:00
Gaurav Aggarwal 5849459c65 Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change spaces to tabs. 2019-02-20 00:25:45 +00:00
Richard Barry c3c9c12ce2 Update the common demo death.c to use the updated macro name to give it a secure context. 2019-02-19 02:57:44 +00:00
Gaurav Aggarwal ce576f3683 First Official Release of ARMV8M Support. This release removes Pre-Release from all the ARMv8M files licensees. 2019-02-19 02:30:32 +00:00
Richard Barry 58ba10eee8 Update version number in readiness for V10.2.0 release. 2019-02-17 22:36:16 +00:00
Gaurav Aggarwal 55ad3861c5 Sync the Renesas port to AFR Git Repo 2019-02-17 01:27:16 +00:00
Gaurav Aggarwal 0de2a2758a Fix definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE 
tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE was not correctly defined resulting in
dynamically allocated TCB not being freed when MPU was enabled. This commit fixes
the definition to ensure that dynamically allocated RAM (Stack and TCB) is freed
always.
 2019-02-17 01:24:58 +00:00
Gaurav Aggarwal 2c88fb7fa1 Fix build failure when dynamic allocation is not enabled. 
When dynamic allocation is not enabled, vPortFree is not available. The current code used
vPortFree and this resulted in linker error. This commit removes the use of vPortFree when
dynamic allocation is not enabled.
 2019-02-16 20:21:47 +00:00
Richard Barry 6844bef74f Replace the pdf RISC-V documentation with links to the documentation web pages. 2019-02-16 01:15:33 +00:00
Richard Barry b2b1b09ea5 Fix bug in core_cm3.c atomic macros. 
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
 2019-02-16 01:08:38 +00:00
Richard Barry 3153131fa7 Add Dornerworks attribution to makefiles that build the Freedom Studio RISC-V project. 2019-02-12 02:43:28 +00:00
Richard Barry 7e08fd6d07 Add makefiles that build the FreedomStudio project (provided by Dornerworks - thanks). 2019-02-11 19:44:13 +00:00
Richard Barry fb73829148 Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState(). 
Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
 2019-02-08 01:18:08 +00:00
Richard Barry df5952f655 Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations. 2019-01-21 23:39:48 +00:00
Gaurav Aggarwal 817783d75c Copyright updates from Cadence. 
e1df894752
 2019-01-16 19:01:25 +00:00
Richard Barry a4941ac5db Update main.c() for the WIN32-MingW project so the trace recorder is initialized even when the simple blinky demo is used - otherwise the trace recorder causes an exception as it is used without first being initialized. 2019-01-07 19:40:13 +00:00
Richard Barry 80df5cd517 Update the pin mux setup on the Vega board demo to enable the LED. 2018-12-31 20:14:34 +00:00
Richard Barry 11d9c440b8 Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason). 
Add a project for the Vega board's RI5CY core.
 2018-12-31 18:19:52 +00:00
Richard Barry e2af102c80 Re-org of RISC-V file structure and naming step 2. 2018-12-30 23:53:47 +00:00
Richard Barry 818eeccc0c Re-org of RISC-V file structure and naming step 1. 2018-12-30 23:20:26 +00:00
Richard Barry db750d0c82 Update RSIC-V port layer after testing saving and receiving of chip specific registers. 2018-12-30 23:11:40 +00:00
Richard Barry 60b133b2c6 Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack. 2018-12-30 20:00:43 +00:00
Richard Barry 911a1de273 Correct accidental deletion in GenQTest.c. 2018-12-28 03:38:27 +00:00
Richard Barry d369110167 Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings. 
Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
 2018-12-28 00:44:18 +00:00
Richard Barry 178fe4f143 Update the Freedom Studio RISC-V project so the gdbinit options are now specified on the command line. 2018-12-27 04:57:49 +00:00
Richard Barry e5daf23d75 Update Freedom Studio RISC-V demo for the latest GCC RISC-V port - not yet tested. 2018-12-27 04:34:08 +00:00
Richard Barry 80f6f3e59b Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running. 2018-12-24 17:48:10 +00:00
Richard Barry ce36928ea8 Rename directories in the RISC-V port. 2018-12-24 17:37:02 +00:00
Richard Barry 2181c0375e Backup Microsemi Renode project before adding a build configuration for the target hardware. 2018-12-19 02:56:13 +00:00
Richard Barry 8d213b42f2 Add vTimerSetReloadMode() calls to the code coverage tests. 2018-12-17 23:19:23 +00:00
Richard Barry 6edabbe7ea Update the the MPU simulator project to exercise the timer API. 2018-12-17 22:06:58 +00:00
Richard Barry 148f588f56 Remove "FromISR' functions from the list of functions that switch to a privileged mode as IRQs are privileged already. 
Add the vTimerSetReloadMode() API function.
 2018-12-17 22:04:18 +00:00
Richard Barry 8285ca6b5f Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode. 2018-12-17 00:01:36 +00:00
Richard Barry 101806906d Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT. 2018-12-16 23:59:49 +00:00
Richard Barry 7cc42b2ab6 Save changes to the RISC-V port layer before making changes necessary to support pulpino too: 
+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
 2018-12-16 20:21:29 +00:00
Richard Barry 866635d2ad Microsemi RISC-V project: 
Reorganize project to separate Microsemi code into its own directory.
    Add many more demo and tests.
 2018-12-10 20:55:32 +00:00
Richard Barry 6b37800ade Backup checkin of MiFive demo running in ReNode emulator. 2018-12-10 05:28:05 +00:00
Richard Barry 9a136a52df Backup check in of the Microsemi IGLOO2 Creative Board RISC-V demo - still a work in progress. 2018-12-04 01:27:06 +00:00
Richard Barry 4b9dd38d1c Backup checking of the Freedom Studio RISC-V project - still a work in progress. 2018-12-04 01:25:53 +00:00
Richard Barry 65f7a2dc19 Update RISC-V port to use a separate interrupt stack. 2018-12-04 01:23:41 +00:00
Richard Barry e85ea96f78 Some efficiency improvements in Risc-V port. 2018-11-28 19:35:40 +00:00
Richard Barry dc99300fa9 First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo. 2018-11-24 20:59:07 +00:00
Richard Barry d0ef322b13 Add kernel code to the RISC-V-Qemu-sifive_e-FreedomStudio demo. 2018-11-24 04:42:20 +00:00
Richard Barry f7102f2342 Add a starting point for a Freedom Studio Risc V project. 2018-11-24 03:48:55 +00:00
Richard Barry db64297487 Provide each Risc V task with an initial mstatus register value. 2018-11-20 20:12:35 +00:00
Richard Barry 8cef339aec Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress. 2018-11-19 06:01:29 +00:00
Richard Barry baee711cb6 Continue work on Risc V port. 2018-11-06 02:04:28 +00:00
Richard Barry 74d0d16aab Update xTaskRemoveFromEventList() so when tickless idle is used prvResetNextTaskUnblockTime() only gets called if the scheduler is not locked, as it would get called when the scheduler is unlocked in any case. 2018-11-05 19:35:54 +00:00
Richard Barry 55ff89373a Update the method used to detect if a timer is active. Previously the timer was deemed to be inactive if it was not referenced from a list. However, when a timer is updated it is temporarily removed from, then re-added to a list, so now the timer's active status is stored separately. 2018-10-24 21:37:59 +00:00
Richard Barry 6fab2b9e0d Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom(). 2018-10-08 15:10:18 +00:00
Gaurav Aggarwal 1af80854e6 Fix Xtensa project file and some documentation improvements. 2018-10-02 23:54:51 +00:00
Richard Barry c6de0001fa Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type. 
Allows the task name parameter passed into xTaskCreate() to be NULL.
 2018-09-30 21:50:05 +00:00
Richard Barry e3dc5e934b RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet. 2018-09-27 17:25:17 +00:00
Richard Barry 2bcb1ab02b Add trap handler to RISC-V port so there is no dependency on third party code. 2018-09-23 03:52:23 +00:00
Richard Barry 32f35e9130 RISC-V: 
Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
 2018-09-12 16:33:05 +00:00
Richard Barry b11eb3a59c RISC-V work in progress: 
+ Initialise task stack.
    + Successfully jump to start of first task.
 2018-09-10 20:50:05 +00:00
Richard Barry 0c0f0d0f8f Minor synching - no functional changes. 2018-09-07 22:24:51 +00:00
Richard Barry 92ae8e7aff Update version numbers ready for release. 2018-09-07 18:13:20 +00:00
Richard Barry 1a235efd2b Update trace configuration files for the updated trace recorder code. 2018-09-06 18:52:45 +00:00
Richard Barry be9c0730c3 Update trace recorder code to the latest. 
Some minor changes to enable the configREMOVE_STATIC_QUALIFIER constant to be used by those debuggers that cannot cope with statics being used.
 2018-09-06 03:23:03 +00:00
Richard Barry 21a8ff35dd Two minor updates in the comments to fix html formatting that was preventing doxygen creating documents correctly. 2018-09-01 02:42:34 +00:00
Richard Barry e2750cd388 Case unused return values for memset and memcpy to void in stream_buffer.c to avoid compiler warnings when the warning level is turned up. 
Remove duplicate comment in heap_1.c.
 2018-08-29 15:43:41 +00:00
Richard Barry 0d6e3df7ec Minor updates to fix issues with the Segger kernel aware plug since V10.1.0. 2018-08-28 18:10:42 +00:00
Richard Barry 893db45834 Changes required for the IAR StateViewer plug-in to work with FreeRTOS V10.1.0. 2018-08-27 23:11:28 +00:00
Richard Barry b0ce1f61c9 Move some variables from function scope back to being file scope for the benefit of some kernel aware debuggers that were left working in a non-functioning mode after the V10.1.0 release - not last change for this purpose. 2018-08-27 21:59:26 +00:00
Richard Barry a11b1a494d FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP, 
which was brought into the main download in FreeRTOS V10.0.0.  FreeRTOS+TCP can
be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches
applied to FreeRTOS+TCP.
 2018-08-23 00:00:20 +00:00
Richard Barry 3a1631fda3 Update copyright date ready for tagging V10.1.0. 2018-08-22 23:23:03 +00:00
Richard Barry bdb088e66f Fix some build issues in older kernel demo projects. 
Update to V2.0.7 of the TCP/IP stack:
   + Multiple security improvements and fixes in packet parsing routines, DNS
     caching, and TCP sequence number and ID generation.
   + Disable NBNS and LLMNR by default.
   + Add TCP hang protection by default.

We thank Ori Karliner of Zimperium zLabs Team for reporting these issues.
 2018-08-22 21:29:21 +00:00
Richard Barry fb9de58f56 Update version numbers in preparation for a new release. 2018-08-21 19:50:48 +00:00
Richard Barry 722ca8fb2b Update demo project for Tensilita - work in progres.. 
Add support for POSIX style errno - work in progress.
 2018-08-21 19:37:04 +00:00
Richard Barry 78d20e2854 Only include the static definition of freertos_tasks_c_additions_init if FREERTOS_TASKS_C_ADDITIONS_INIT is defined, matching the guide used to include the function's prototype. 2018-08-20 15:08:35 +00:00
Gaurav Aggarwal 56dc0dd9b4 Merge bug fixes from Cadence 2018-08-07 07:21:07 +00:00
Richard Barry f6cbf20019 Update RISC-V project to used official port stubs in place of third party port. 2018-07-07 21:54:41 +00:00
Richard Barry 3bfc32d444 Add stubs for official RISC-V RV32 port. 2018-07-07 21:47:31 +00:00
Richard Barry f7fc215247 Update stream buffer tests to try resetting a statically allocated stream buffer before deleting it (tests fix in code). 
Update trace recorder library.
 2018-07-02 21:58:28 +00:00
Richard Barry 0887713969 Fix issues whereby vStreamBufferReset() clobbered the flag that indicated the stream buffer was statically allocated. 2018-06-20 21:21:55 +00:00
Richard Barry 9119e1e0e3 Add starting point for IGLOO2 RISV-V demo project. 2018-06-20 21:18:14 +00:00
Richard Barry 483f4a8c4b Small change to the directory name in which the RISC-V port is stored. 2018-06-20 21:15:04 +00:00
Richard Barry 3d8d2f3cc8 Add RISCV port layer. 2018-06-20 19:21:18 +00:00
Richard Barry 10eea4aded Remove period from the URL that links to the web page that describes the FreeRTOSConfig.h parameters. 2018-06-15 00:03:20 +00:00
Gaurav Aggarwal c4b1afc4ef Add Xtensa port 
The project file is for Xtensa Xplorer simulator.
Also add tests for one size stream buffer.
 2018-06-14 19:43:17 +00:00
Richard Barry d6fcd5dbba Add the option to specify a stack size in the standard demo MessageBuffer tests. 
Add stream and message buffer tests into the Zynq demo project.
 2018-06-13 16:50:16 +00:00
Richard Barry 4fbcdbf13b Fix misra violations in queue.c by introducing a union that allows the correct data types to be used in place of void *, then tidy up where the union is used. 2018-06-11 18:51:53 +00:00
Richard Barry 4a8c4c9eaf TimerHandle_t is now type safe instead of void *. 
Remove casts that are no longer required not type safe handles are used.
 2018-06-11 04:43:12 +00:00
Richard Barry 3d8681de9e Continue updating to MISRA 2012 from 2004 - currently working on queue.c and committing as working copy prior to making larger change. 
Change QueueHandle_t to be typesafe from void *.
Change StreamBuffer_t to be typesafe from void *.
 2018-06-11 01:56:32 +00:00
Richard Barry 7a9f453f96 Remove casts from EventGroupHandle_t to EventGroup_t, and corresponding lint comments, which are not required now EventGroupHandle_t is type safe. 
Fix the prototype of prvTimerCallback() in the MPU simulator demo (caught due to the new type safety in tasks.c).
 2018-06-04 04:02:57 +00:00
Richard Barry 390fb06b49 First pass at updating from MISRA 2004 to MISRA 2012: 
Updated pvContainer member of list items to List_t * rather than void * as they are always contained in a list if anywhere.
Made EventGroupHandle_t typesafe pointer to forward referenced struct rather than void pointer.
Made TaskHandle_t typesafe pointer to forward referenced struct, rather than a void pointer.
 2018-06-03 22:57:46 +00:00
Richard Barry 5bebf10fa4 Minor updates to comments only. 2018-05-17 17:50:14 +00:00
Richard Barry 585b16a39f Update definition of StaticTimer_t so its size is correct on MSP403X large memory model builds. 2018-05-07 16:31:50 +00:00
Richard Barry d30249789b Previously the MPSoC Cortex-A53 demo was updated to the latest Xilinx SDK tools to the point where it was building, but not tested. This check in modifies the project files slightly following testing. 2018-05-04 15:06:50 +00:00
Richard Barry 26d8c76996 Update Zynq, MPSoc Cortex-A53 and MPSoc Cortex-R5 demo projects to build with the 18.1 version of the Xilinx SDK - building BUT NOT YET TESTED. 2018-05-02 04:04:54 +00:00
Richard Barry a3148ba638 xTaskGenericNotify() now sets xYieldPending to pdTRUE even when the 'higher priority task woken' parameter is provided - making its behaviour consistent with event objects. 
Ensure tasks that are blocked indefinitely on a direct to task notification return their state as eBlocked, previously was returned as eSuspended - making its behaviour consistent with event objects.
Fix typo in stream_buffer.c where "size_t xBytesAvailable ); PRIVILEGED_FUNCTION" had the semicolon in the wrong place.
Add testing of Stream Buffers to the AbortDelay.c tests.
Guard inclusion of C code when FreeRTOSConfig.h is included from an assembly file in the ARM7_LPC2129_IAR demo.
Fix minor typos in the Windows demo comment blocks.
 2018-04-29 18:15:38 +00:00
Richard Barry 025088c280 Fix regressions introduced by introduction of configMESSAGE_BUFFER_LENGTH_TYPE constant - specifically enabling big endian support and updates to xStreamBufferNextMessageLengthBytes. 2018-03-15 18:31:02 +00:00