Richard Barry
b2b1b09ea5
Fix bug in core_cm3.c atomic macros.
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Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
2019-02-16 01:08:38 +00:00
Richard Barry
fb73829148
Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState().
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Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
2019-02-08 01:18:08 +00:00
Richard Barry
df5952f655
Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations.
2019-01-21 23:39:48 +00:00
Richard Barry
60b133b2c6
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
2018-12-30 20:00:43 +00:00
Richard Barry
ce36928ea8
Rename directories in the RISC-V port.
2018-12-24 17:37:02 +00:00
Richard Barry
7cc42b2ab6
Save changes to the RISC-V port layer before making changes necessary to support pulpino too:
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+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
2018-12-16 20:21:29 +00:00
Richard Barry
65f7a2dc19
Update RISC-V port to use a separate interrupt stack.
2018-12-04 01:23:41 +00:00
Richard Barry
e85ea96f78
Some efficiency improvements in Risc-V port.
2018-11-28 19:35:40 +00:00
Richard Barry
dc99300fa9
First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.
2018-11-24 20:59:07 +00:00
Richard Barry
db64297487
Provide each Risc V task with an initial mstatus register value.
2018-11-20 20:12:35 +00:00
Richard Barry
8cef339aec
Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.
2018-11-19 06:01:29 +00:00
Richard Barry
baee711cb6
Continue work on Risc V port.
2018-11-06 02:04:28 +00:00
Richard Barry
e3dc5e934b
RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet.
2018-09-27 17:25:17 +00:00
Richard Barry
2bcb1ab02b
Add trap handler to RISC-V port so there is no dependency on third party code.
2018-09-23 03:52:23 +00:00
Richard Barry
32f35e9130
RISC-V:
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Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
2018-09-12 16:33:05 +00:00
Richard Barry
b11eb3a59c
RISC-V work in progress:
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+ Initialise task stack.
+ Successfully jump to start of first task.
2018-09-10 20:50:05 +00:00
Richard Barry
3a1631fda3
Update copyright date ready for tagging V10.1.0.
2018-08-22 23:23:03 +00:00
Richard Barry
fb9de58f56
Update version numbers in preparation for a new release.
2018-08-21 19:50:48 +00:00
Richard Barry
f6cbf20019
Update RISC-V project to used official port stubs in place of third party port.
2018-07-07 21:54:41 +00:00
Richard Barry
3bfc32d444
Add stubs for official RISC-V RV32 port.
2018-07-07 21:47:31 +00:00
