Aniruddha Kanhere
1bc759d413
Aws only files spell check ( #593 )
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* Added spell check
* All words
* Add a missing word
* Fix header checks
* Fix header checks v1
* Fix header check v2
* Updated freertos link in header
* Fixed afr link in the header
* Fix last of header checks
* Update the spell check script to check amazon licensed files only
* Fixed paths and added comments
* Try with modified repo
* Add inplace substitute option to sed
* Use official repo as the spell checker source
* Add vendor file to the ignored list
Co-authored-by: root <root@ip-172-31-5-28.us-west-2.compute.internal>
2021-05-13 16:07:56 -07:00
Archit Aggarwal
971a6e1d22
Merge FreeRTOS 202104.00 to main ( #585 )
2021-04-29 14:53:40 -07:00
Joseph Julicher
da9b9a800d
[AUTO][RELEASE]: Bump file header version to "202012.00"
2020-12-15 11:50:37 -07:00
David Chalco
07f3cbafee
[AUTO][RELEASE]: Bump file header version to "202011.00"
2020-11-10 14:45:34 -08:00
David Chalco
0573fea3ee
Update (.s, .S) kernel version numbers to 10.4.1 ( #283 )
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* version bump to 10.4.1
* update .s file version numbers
* Update FreeRTOS/History.txt
2020-09-18 10:55:01 -07:00
Cobus van Eeden
d5862dbe01
Sync back V10.4.1 ( #282 )
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* Move Kernel submodule pointer to 10.4.1
* Update version number to V10.4.1 (#281 )
2020-09-17 17:16:33 -07:00
David Chalco
89d475e9b1
Update Version number to 10.4.0 ( #237 )
2020-09-10 19:40:24 -07:00
Yuhui.Zheng
589dd9f149
Update version number in readiness for V10.3.0 release. Sync SVN with reviewed release candidate.
2020-02-07 20:14:50 +00:00
Richard Barry
7bea399061
Update libraries and sundry check-ins ready for the V10.3.0 kernel release.
2020-02-06 18:52:35 +00:00
Richard Barry
07622ed3ee
Remove driver files that generate compiler warnings from the RISC-V_Renode_Emulator_SoftConsole project.
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Update RISC-V ports so the interrupt stack is set to a known value before the scheduler is started if the interrupt stack is statically defined rather than re-using the main.c() stack.
2019-11-18 17:23:14 +00:00
Richard Barry
c0741e36ed
Fix spelling mistakes copied and pasted into a couple of RISC-V demo main.c files.
2019-10-22 16:31:57 +00:00
Richard Barry
11c391dfb3
Tidy up main_full.c and change alignment of variable accesses in RegTest.S for the RISC-V_Renode_Emulator_SoftConsole demo.
2019-10-22 02:15:28 +00:00
Richard Barry
a83244a37e
Add the miv-basic.resc reNode script into the RISC-V_Renode_Emulator_SoftConsole demo as it is no longer shipped with the Microsemi tools.
2019-10-17 20:39:40 +00:00
Richard Barry
fa404422b9
Add link to dual core blog post into STM32H745I demo.
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Doxygen corrections in list.h.
Use #error to check FreeRTOS.h is included before message_buffer.h and stream_buffer.h.
2019-07-04 21:18:36 +00:00
Richard Barry
b51529a284
Update version number ready for next release.
2019-05-11 01:47:37 +00:00
Richard Barry
53cb12e389
Add M7/M4 AMP demo.
2019-05-10 18:25:10 +00:00
Richard Barry
58ba10eee8
Update version number in readiness for V10.2.0 release.
2019-02-17 22:36:16 +00:00
Richard Barry
6844bef74f
Replace the pdf RISC-V documentation with links to the documentation web pages.
2019-02-16 01:15:33 +00:00
Richard Barry
b2b1b09ea5
Fix bug in core_cm3.c atomic macros.
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Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
2019-02-16 01:08:38 +00:00
Richard Barry
fb73829148
Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState().
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Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
2019-02-08 01:18:08 +00:00
Richard Barry
11d9c440b8
Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason).
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Add a project for the Vega board's RI5CY core.
2018-12-31 18:19:52 +00:00
Richard Barry
e2af102c80
Re-org of RISC-V file structure and naming step 2.
2018-12-30 23:53:47 +00:00
Richard Barry
60b133b2c6
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
2018-12-30 20:00:43 +00:00
Richard Barry
80f6f3e59b
Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.
2018-12-24 17:48:10 +00:00
