Richard Barry b2b1b09ea5 Fix bug in core_cm3.c atomic macros. ... Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.		2019-02-16 01:08:38 +00:00
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.settings	Fix bug in core_cm3.c atomic macros.	2019-02-16 01:08:38 +00:00
blinky_demo	Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.	2018-12-24 17:48:10 +00:00
full_demo	Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState().	2019-02-08 01:18:08 +00:00
Microsemi_Code	Re-org of RISC-V file structure and naming step 2.	2018-12-30 23:53:47 +00:00
.cproject	Fix bug in core_cm3.c atomic macros.	2019-02-16 01:08:38 +00:00
.project	Fix bug in core_cm3.c atomic macros.	2019-02-16 01:08:38 +00:00
FreeRTOSConfig.h	Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.	2018-12-30 20:00:43 +00:00
hw_platform.h	Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.	2018-12-24 17:48:10 +00:00
main.c	Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.	2018-12-24 17:48:10 +00:00
microsemi-riscv-renode.ld	Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.	2018-12-24 17:48:10 +00:00
RTOSDemo Debug Renode.launch	Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.	2018-12-30 20:00:43 +00:00
RTOSDemo-start-renode-emulator-and-attach.launch	Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.	2018-12-24 17:48:10 +00:00