15 commits

Author	SHA1	Message	Date
Richard Barry	e2af102c80	Re-org of RISC-V file structure and naming step 2.	2018-12-30 23:53:47 +00:00
Richard Barry	db750d0c82	Update RSIC-V port layer after testing saving and receiving of chip specific registers.	2018-12-30 23:11:40 +00:00
Richard Barry	60b133b2c6	Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.	2018-12-30 20:00:43 +00:00
Richard Barry	d369110167	Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings. ... Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.	2018-12-28 00:44:18 +00:00
Richard Barry	ce36928ea8	Rename directories in the RISC-V port.	2018-12-24 17:37:02 +00:00
Richard Barry	101806906d	Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT.	2018-12-16 23:59:49 +00:00
Richard Barry	7cc42b2ab6	Save changes to the RISC-V port layer before making changes necessary to support pulpino too: ... + Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other. + Handle external interrupts (working with Renode emulator). + The _sp linker variable is now called __freertos_irq_stack_top.	2018-12-16 20:21:29 +00:00
Richard Barry	65f7a2dc19	Update RISC-V port to use a separate interrupt stack.	2018-12-04 01:23:41 +00:00
Richard Barry	e85ea96f78	Some efficiency improvements in Risc-V port.	2018-11-28 19:35:40 +00:00
Richard Barry	dc99300fa9	First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.	2018-11-24 20:59:07 +00:00
Richard Barry	db64297487	Provide each Risc V task with an initial mstatus register value.	2018-11-20 20:12:35 +00:00
Richard Barry	8cef339aec	Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress.	2018-11-19 06:01:29 +00:00
Richard Barry	baee711cb6	Continue work on Risc V port.	2018-11-06 02:04:28 +00:00
Richard Barry	e3dc5e934b	RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet.	2018-09-27 17:25:17 +00:00
Richard Barry	2bcb1ab02b	Add trap handler to RISC-V port so there is no dependency on third party code.	2018-09-23 03:52:23 +00:00