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Author SHA1 Message Date
Gaurav Aggarwal ae448fc952 Add Cortex M23 GCC and IAR ports. Add demo projects for Nuvoton NuMaker-PFM-2351. 2019-05-02 21:08:28 +00:00
Richard Barry 079d081346 Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit. 2019-04-29 00:57:14 +00:00
Richard Barry 27ca5c8341 Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM Cortex-M33 ports to assist with link time optimisation. 2019-04-25 19:49:50 +00:00
Richard Barry 84377442fc Added portMEMORY_BARRIER() implemented as __asm volatile( "" ::: "memory" ) into ARM GCC ports to assist with link time optimisation. 2019-04-21 20:15:34 +00:00
Richard Barry 606845492b Fix potential memory leak in the Win32 FreeRTOS+TCP network interface initialisation sequence. 
Introduce portMEMORY_BARRIER() macro to assist with memory access ordering when suspending the scheduler if link time optimization is used.
 2019-04-17 17:16:04 +00:00
Gaurav Aggarwal dd9a9710c6 Export port architecture name for COrtex-M33. This can be used by debuggers to find the port in-use to be able to correctly decode the context stored on the stack. 2019-03-28 00:00:46 +00:00
Gaurav Aggarwal ba39a958b5 Fix spelling of priority in comments. 2019-03-18 23:28:03 +00:00
Richard Barry 2265d70499 Correcting spelling mistakes in comments only. 2019-03-08 17:30:49 +00:00
Richard Barry 06596c3192 Prepare the RISC-V port layer for addition of 64-bit port. 2019-03-08 17:03:43 +00:00
Gaurav Aggarwal 5fe8465a35 Change type of usStackDepth to configSTACK_DEPTH_TYPE. 2019-02-21 03:25:30 +00:00
Gaurav Aggarwal 5623c69748 Fix Build and Links failure in MPU projects. Minor cosmetic changes in some V8M files. 2019-02-20 20:27:07 +00:00
Richard Barry 8b6ab5f197 Add instructions on building the Cortex-M33 secure and non secure projects into the comments of that project and into a readme.txt file. 
Enable configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES setting to be used in statically allocated systems.
 2019-02-20 17:55:59 +00:00
Gaurav Aggarwal 5849459c65 Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change spaces to tabs. 2019-02-20 00:25:45 +00:00
Richard Barry c3c9c12ce2 Update the common demo death.c to use the updated macro name to give it a secure context. 2019-02-19 02:57:44 +00:00
Gaurav Aggarwal ce576f3683 First Official Release of ARMV8M Support. This release removes Pre-Release from all the ARMv8M files licensees. 2019-02-19 02:30:32 +00:00
Richard Barry 58ba10eee8 Update version number in readiness for V10.2.0 release. 2019-02-17 22:36:16 +00:00
Gaurav Aggarwal 55ad3861c5 Sync the Renesas port to AFR Git Repo 2019-02-17 01:27:16 +00:00
Richard Barry 6844bef74f Replace the pdf RISC-V documentation with links to the documentation web pages. 2019-02-16 01:15:33 +00:00
Richard Barry b2b1b09ea5 Fix bug in core_cm3.c atomic macros. 
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
 2019-02-16 01:08:38 +00:00
Richard Barry fb73829148 Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState(). 
Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
 2019-02-08 01:18:08 +00:00
Richard Barry df5952f655 Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations. 2019-01-21 23:39:48 +00:00
Gaurav Aggarwal 817783d75c Copyright updates from Cadence. 
e1df894752
 2019-01-16 19:01:25 +00:00
Richard Barry 11d9c440b8 Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason). 
Add a project for the Vega board's RI5CY core.
 2018-12-31 18:19:52 +00:00
Richard Barry e2af102c80 Re-org of RISC-V file structure and naming step 2. 2018-12-30 23:53:47 +00:00
Richard Barry 818eeccc0c Re-org of RISC-V file structure and naming step 1. 2018-12-30 23:20:26 +00:00
Richard Barry db750d0c82 Update RSIC-V port layer after testing saving and receiving of chip specific registers. 2018-12-30 23:11:40 +00:00
Richard Barry 60b133b2c6 Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack. 2018-12-30 20:00:43 +00:00
Richard Barry d369110167 Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings. 
Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
 2018-12-28 00:44:18 +00:00
Richard Barry ce36928ea8 Rename directories in the RISC-V port. 2018-12-24 17:37:02 +00:00
Richard Barry 148f588f56 Remove "FromISR' functions from the list of functions that switch to a privileged mode as IRQs are privileged already. 
Add the vTimerSetReloadMode() API function.
 2018-12-17 22:04:18 +00:00
Richard Barry 101806906d Rework RISC-V portASM.S to make it easier to add in chip specific RISC-V extensions and accommodate chips that don't include the CLINT. 2018-12-16 23:59:49 +00:00
Richard Barry 7cc42b2ab6 Save changes to the RISC-V port layer before making changes necessary to support pulpino too: 
+ Switch positions of the asm functions used to start the kernel and handle traps to enable one to reference to the other.
+ Handle external interrupts (working with Renode emulator).
+ The _sp linker variable is now called __freertos_irq_stack_top.
 2018-12-16 20:21:29 +00:00
Richard Barry 65f7a2dc19 Update RISC-V port to use a separate interrupt stack. 2018-12-04 01:23:41 +00:00
Richard Barry e85ea96f78 Some efficiency improvements in Risc-V port. 2018-11-28 19:35:40 +00:00
Richard Barry dc99300fa9 First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo. 2018-11-24 20:59:07 +00:00
Richard Barry db64297487 Provide each Risc V task with an initial mstatus register value. 2018-11-20 20:12:35 +00:00
Richard Barry 8cef339aec Update Risc-V port to use environment call in place of software interrupt - still very much a work in progress. 2018-11-19 06:01:29 +00:00
Richard Barry baee711cb6 Continue work on Risc V port. 2018-11-06 02:04:28 +00:00
Richard Barry 6fab2b9e0d Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom(). 2018-10-08 15:10:18 +00:00
Richard Barry c6de0001fa Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type. 
Allows the task name parameter passed into xTaskCreate() to be NULL.
 2018-09-30 21:50:05 +00:00
Richard Barry e3dc5e934b RISC-V tasks now context switching to each other using taskYIELD() - not fully tested yet. 2018-09-27 17:25:17 +00:00
Richard Barry 2bcb1ab02b Add trap handler to RISC-V port so there is no dependency on third party code. 2018-09-23 03:52:23 +00:00
Richard Barry 32f35e9130 RISC-V: 
Added code to setup the timer interrupt - not tested yet.
Added the taskYIELD() implementation - so far just checked it generates an interrupt.
 2018-09-12 16:33:05 +00:00
Richard Barry b11eb3a59c RISC-V work in progress: 
+ Initialise task stack.
    + Successfully jump to start of first task.
 2018-09-10 20:50:05 +00:00
Richard Barry 92ae8e7aff Update version numbers ready for release. 2018-09-07 18:13:20 +00:00
Richard Barry e2750cd388 Case unused return values for memset and memcpy to void in stream_buffer.c to avoid compiler warnings when the warning level is turned up. 
Remove duplicate comment in heap_1.c.
 2018-08-29 15:43:41 +00:00
Richard Barry 3a1631fda3 Update copyright date ready for tagging V10.1.0. 2018-08-22 23:23:03 +00:00
Richard Barry fb9de58f56 Update version numbers in preparation for a new release. 2018-08-21 19:50:48 +00:00
Richard Barry 722ca8fb2b Update demo project for Tensilita - work in progres.. 
Add support for POSIX style errno - work in progress.
 2018-08-21 19:37:04 +00:00
Gaurav Aggarwal 56dc0dd9b4 Merge bug fixes from Cadence 2018-08-07 07:21:07 +00:00
Richard Barry f6cbf20019 Update RISC-V project to used official port stubs in place of third party port. 2018-07-07 21:54:41 +00:00
Richard Barry 3bfc32d444 Add stubs for official RISC-V RV32 port. 2018-07-07 21:47:31 +00:00
Richard Barry 483f4a8c4b Small change to the directory name in which the RISC-V port is stored. 2018-06-20 21:15:04 +00:00
Richard Barry 3d8d2f3cc8 Add RISCV port layer. 2018-06-20 19:21:18 +00:00
Gaurav Aggarwal c4b1afc4ef Add Xtensa port 
The project file is for Xtensa Xplorer simulator.
Also add tests for one size stream buffer.
 2018-06-14 19:43:17 +00:00
Richard Barry 4fbcdbf13b Fix misra violations in queue.c by introducing a union that allows the correct data types to be used in place of void *, then tidy up where the union is used. 2018-06-11 18:51:53 +00:00
Richard Barry 390fb06b49 First pass at updating from MISRA 2004 to MISRA 2012: 
Updated pvContainer member of list items to List_t * rather than void * as they are always contained in a list if anywhere.
Made EventGroupHandle_t typesafe pointer to forward referenced struct rather than void pointer.
Made TaskHandle_t typesafe pointer to forward referenced struct, rather than a void pointer.
 2018-06-03 22:57:46 +00:00
Richard Barry 5bebf10fa4 Minor updates to comments only. 2018-05-17 17:50:14 +00:00
Richard Barry aec45f2479 Import the code coverage test additions from the (unpublished) Visual Studio project to the (published) MingW/Eclipse project. 
Update the MingW/Eclipse project to add a code coverage build configuration in addition to the existing Debug build configuration.
Update StreamBufferDemo.c so functions are called directly, rather than via configASSERT(), so their code coverage can be measured when configASSERT() is not defined.
In the Win32 port, replace the call to TerminateProcess() in vPortEndScheduler() with exit( 0 ) - which triggers the writing of the code coverage data to the disk.
Fix bug in ucStreamBufferGetStreamBufferType() - which is only used by the Percepio trace tool.
Update the line within vTaskStartScheduler() that was setting xTickCount to 0 to instead set it to configINITIAL_TICK_COUNT.
 2018-03-14 15:58:47 +00:00
Richard Barry f9bef06ec0 Introduce xMessageBufferNextLengthBytes() and tests for the same. 
Add call to traceTASK_SWITCHED_IN() in vTaskStartScheduler() so trace tools can see the first task to run.
 2018-03-04 19:25:14 +00:00
Richard Barry 7ddb8b342d Microblaze port: Place critical section around XIntc_Enable() to protect read/modify/write operation performed inside the library. 2018-01-30 17:42:12 +00:00
Richard Barry 13651934be Roll up the minor changes checked into svn since V10.0.0 into new V10.0.1 ready for release. 2017-12-18 22:54:18 +00:00
Richard Barry cfc268814a Update to MIT licensed FreeRTOS V10.0.0 - see https://www.freertos.org/History.txt 2017-11-29 16:53:26 +00:00
Richard Barry 037abdddf2 Update TriCore port to work with latest GCC compiler. 2017-08-09 16:57:35 +00:00
Richard Barry 6eea3d8d4b Correct long time mis-spelled portINITIAL_EXEC_RETURN to portINITIAL_EXC_RETURN 2017-05-30 00:36:09 +00:00
Richard Barry b080f13543 Add more "memory" clobbers into the MPU ports to make them robust to more aggressive optimisation in newer GCC version. 2017-04-10 01:58:01 +00:00
Richard Barry 0f85ead175 Add more "memory" clobbers into asm code of GCC/ARM_CRx_No_GIC port to make it robust with higher optimisation in newer versions of GCC. 2017-04-10 01:01:11 +00:00
Richard Barry 0a7a0a79d6 Updates to prevent warnings when compiled with LLVM. 2017-04-10 00:26:22 +00:00
Richard Barry 8ca40d80a9 Ensure the PIC32 interrupt stack is 8 byte aligned for all values of configISR_STACK_SIZE. 2017-04-09 20:13:48 +00:00
Richard Barry 464c2660ad Updates to the Cortex-M tickless idle code to reduce clock slippage. 
Updates to prevent the vTaskSwitchContext() function being removed from GCC builds when link time optimisation is used.
 2017-03-28 03:13:48 +00:00
Richard Barry ad5659e93d Housekeeping check-in, no code changes. 2017-03-08 22:19:14 +00:00
Richard Barry b9fe24962e Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across asm code as optimisers get more aggressive. 2017-03-07 04:06:10 +00:00
Richard Barry c3acc441ac Introduce vTaskInternalSetTimeOutState() which does not have a critical section, and add a critical section to the public version of the same. 2017-02-24 02:16:54 +00:00
Richard Barry 8d041c8e21 Update version number in preparation for maintenance release. 2017-01-22 05:28:13 +00:00
Richard Barry 992a3c8c71 Update BSP source files for UltraScale Cortex-A53 and Cortex-R5 and Microblaze to the 2016.4 versions. 
Correct alignment issue in GCC Cortex-R port that was preventing full floating point usage in interrupts (other ports will be updated likewise).
Update the UltraScale R5 demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
 2017-01-19 04:11:21 +00:00
Richard Barry 6ffaa6f018 Correct alignment issue in GCC and RVDS Cortex-A9 port that was preventing full floating point usage in interrupts (other ports will be updated likewise). 
Update the Zynq demo to test the GCC Cortex-A9 port layer modification mentioned on the line above.
 2017-01-18 18:33:48 +00:00
Richard Barry ca9edf3531 Increase the priority of the Windows threads used by the FreeRTOS Windows port, and, because the threads have high priority and run on the same core, prevent the port running on single core hosts so as to avoid locking up the host. 2017-01-04 04:48:22 +00:00
Richard Barry 225f13bac2 Update TaskNotify.c to test the condition where a direct to task notification is sent to a suspended task. 
Introduce configSTACK_DEPTH_TYPE so the application writer change the type used to specify a stack size from uint16_t to whatever they like.  Defaults to uint16_t if not defined.
Introduce configINITIAL_TICK_COUNT to allow users to start the tick count at something other than 0.  Used for testing, but overflows can be better tested by setting configUSE_16_BIT_TICKS to 1.
Split xQueueGenericReceive() into xQueueReceive(), xQueuePeek() and xQueueSemaphoreTake() as the first step in refactoring xQueueGenericReceive().
Add Cortex-M3 port layer for Code Composer Studio - previously there was only a Cortex-M4F port.
Introduce configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING() to allow applications to prevent portSUPPRESS_TICKS_AND_SLEEP() being called.  Previously the portPRE_SLEEP_PROCESSING() macro could only be used to abort entry into sleep time after clocks had been re-programmed for the distant wake time.
 2016-11-25 21:07:56 +00:00
Richard Barry 7cce089e40 Add support for statically allocated memory protected tasks - previously only dynamically allocated tasks could be memory protected. 2016-09-20 13:54:28 +00:00
Richard Barry 75ffac21d7 Changes to core code and port layer: 
+ Add configASSERT() into ARM Cortex-M ports to check the number of priority
      bit settings.
    + Clear the 'control' register before starting ARM Cortex-M4F ports in case
      the FPU is used before the scheduler is started.  This just saves a few
      bytes on the main stack as it prevents space being left for a later save
      of FPU registers.
    + Added xSemaphoreGetMutexHolderFromISR().
    + Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports.
 2016-08-16 11:38:58 +00:00
Richard Barry bdbf347c22 Remove clrex instruction from Cortex-M ports again as it is implicit in interrupt entry. 2016-06-28 10:39:25 +00:00
Richard Barry c296e2cff8 Improvements to the Cortex-M ports: 
- Clear the SysTick current value register before starting the SysTick (only required if something uses SysTick before starting the scheduler).
- Ensure atomic operations are thread safe by executing clrex in the context switch.
 2016-06-27 13:13:05 +00:00
Richard Barry 2bd7884ace Prepare for V9.0.0 release: 
+ Change version number from V9.0.0rc2 to V9.0.0.
 2016-05-20 18:05:46 +00:00
Richard Barry 0063b29cdf Prepare for V9.0.0 release. 
+ Set flash wait states on MSP432 demos.
+ Remove use of obsolete IO library in PIC32 demos.
+ Remove obsolete item left on stack of first task to run in the Cortex-M0 ports.
+ Correct IA32 GCC vPortExitCritical() implementation when configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY.
 2016-05-19 13:28:12 +00:00
Richard Barry e10647f9c0 Increase the test coverage of the GCC MPU demo that runs in the Keil simulator. 
Add an MPU demo that uses the Keil simulator that also uses the Keil compiler.
Correct a few version numbers for files recently added to the repository.
 2016-05-18 19:51:14 +00:00
Richard Barry ee9cd40b6d Add GCC ARM Cortex-M4F MPU port. 
Add RVDS ARM Cortex-M4F MPU port.
Increase the size of each buffer allocated to pbufs in the Microblaze lwIP demo to prevent pbufs chaining.
Use _start as the top of the stack for each Microblaze task, rather than NULL, as NULL was causing the Xilinx SDK to try and unwind the stack too far.
 2016-05-18 10:41:28 +00:00
Richard Barry fedb98c5f6 Recreated MicroBlaze example using Vivado 2016.1 - the Microblaze project is still a work in progress - not yet fully functional. 2016-05-10 14:05:22 +00:00
Richard Barry 324127837c Update some more standard demos for use on 64-bit architectures. 
Update the Xilinx Ultrascale+ Cortex-A53 (64-bit) and Cortex-R5 (32-bit) demos to use version 2016.1 of the SDK.
 2016-05-06 12:40:27 +00:00
Richard Barry 0721cf102a Completely re-generate the Zynq 7000 demo using the 2016.1 SDK tools. 
Introduce configUSE_TASK_FPU_SUPPORT into the GCC Cortex-A9 port to allow tasks to have an FPU context by default.
Add MikroC Cortex-M4F port.
 2016-04-25 17:24:54 +00:00
Richard Barry 0b5906d404 Remove obsolete MPU demos. 
Separate the MPU wrappers into their own file so they can be used from future MPU ports.
 2016-04-25 12:03:47 +00:00
Richard Barry afd4b432f6 Improve coverage of the MPU API in the new MPU demo, fixing typos in the MPU port layer as they are found. 2016-04-24 18:33:16 +00:00
Richard Barry 345819d550 Update the GCC Cortex-A9 port to introduce a version of the IRQ handler that saves the FPU registers. 2016-04-23 10:53:57 +00:00
Richard Barry ac67c39be9 Update the MPU port so it supports all the public functions found in V9.0.0rc2. 2016-04-20 15:42:34 +00:00
Richard Barry 057b38ad23 Updates to support FreeRTOS MPU in FreeRTOS V9.0.0 - including a GCC project that runs in the Keil simulator to allow development and testing. 2016-04-18 10:49:24 +00:00
Richard Barry 255145bde1 xTaskGetTaskHandle() changed to xTaskGetHandle(). 
Tidy up CEC1302 demo.
Ensure bit 0 of the task address is clear when setting up stack of initial Cortex-M3/4/7 stacks (for strict compliance, although not practically necessary).
vTaskGetTaskInfo() changed to vTaskGetInfo() - with a macro added for backward compatibility.
 2016-04-15 11:48:07 +00:00
Richard Barry f1725afbe5 Remove compiler warning by ensure prvInitialiseMutex() is not included if configUSE_MUTEXES is 0. 
Reduce the number of xTaskCreateStatic() parameters by having the function return the task handle, rather than pass the task handle out using a parameter.  This is also consistent with other objectCreate() functions.
 2016-03-31 15:22:10 +00:00
Richard Barry 07ac1399ee Update version number to 9.0.0rc2. 2016-03-30 12:20:36 +00:00
Richard Barry b9b64c0889 Make the pcObjectGetName() API function naming consistent - so rename pcTaskGetTaskName() to pcTaskGetName(), rename pcTimerGetTimerName() to pcTimerGetName() and add a #defines in FreeRTOS.h to make the changes backward compatible. 2016-03-29 17:16:34 +00:00
Richard Barry aeb03e5fa0 Create minor optimisations (just an asm instruction or two) by using consts in a few places where previously a volatile variable that didn't change was used. 
Add the simple xTimerGetPeriod() and xTimerGetExpiryTime() functions.
 2016-03-29 13:07:27 +00:00
Richard Barry 9dda62372c Update the documentation contained in the header files to be correct for V9.0.0 release candidate 2. 2016-03-26 11:05:42 +00:00