Yuhui.Zheng
589dd9f149
Update version number in readiness for V10.3.0 release. Sync SVN with reviewed release candidate.
2020-02-07 20:14:50 +00:00
Richard Barry
7bea399061
Update libraries and sundry check-ins ready for the V10.3.0 kernel release.
2020-02-06 18:52:35 +00:00
Richard Barry
066e2bc7d2
Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the IAR RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old.
2020-01-09 02:23:51 +00:00
Richard Barry
fbb23055cd
Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the GCC RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old.
2020-01-07 01:14:36 +00:00
Richard Barry
eaf9318df8
Add Source/portable/ARMClang file that directs users to the GCC port if they which to use the ARMClang compiler.
2020-01-04 00:14:18 +00:00
Richard Barry
07622ed3ee
Remove driver files that generate compiler warnings from the RISC-V_Renode_Emulator_SoftConsole project.
...
Update RISC-V ports so the interrupt stack is set to a known value before the scheduler is started if the interrupt stack is statically defined rather than re-using the main.c() stack.
2019-11-18 17:23:14 +00:00
Richard Barry
da3d370ff7
RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.
2019-09-04 15:46:45 +00:00
Richard Barry
973a4f9869
Correct alignment of stack top in RISC-V port when configISR_STACK_SIZE_WORDS is defined to a non zero value.
2019-08-27 15:57:45 +00:00
Richard Barry
b51529a284
Update version number ready for next release.
2019-05-11 01:47:37 +00:00
Richard Barry
079d081346
Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit.
2019-04-29 00:57:14 +00:00
Richard Barry
58ba10eee8
Update version number in readiness for V10.2.0 release.
2019-02-17 22:36:16 +00:00
Richard Barry
b2b1b09ea5
Fix bug in core_cm3.c atomic macros.
...
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
2019-02-16 01:08:38 +00:00
