Gaurav Aggarwal
5623c69748
Fix Build and Links failure in MPU projects. Minor cosmetic changes in some V8M files.
2019-02-20 20:27:07 +00:00
Richard Barry
8b6ab5f197
Add instructions on building the Cortex-M33 secure and non secure projects into the comments of that project and into a readme.txt file.
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Enable configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES setting to be used in statically allocated systems.
2019-02-20 17:55:59 +00:00
Gaurav Aggarwal
5849459c65
Add support for running FreeRTOS on Secure Side only in Cortex M33 port. Also, change spaces to tabs.
2019-02-20 00:25:45 +00:00
Richard Barry
c3c9c12ce2
Update the common demo death.c to use the updated macro name to give it a secure context.
2019-02-19 02:57:44 +00:00
Gaurav Aggarwal
ce576f3683
First Official Release of ARMV8M Support. This release removes Pre-Release from all the ARMv8M files licensees.
2019-02-19 02:30:32 +00:00
Richard Barry
58ba10eee8
Update version number in readiness for V10.2.0 release.
2019-02-17 22:36:16 +00:00
Richard Barry
6844bef74f
Replace the pdf RISC-V documentation with links to the documentation web pages.
2019-02-16 01:15:33 +00:00
Richard Barry
b2b1b09ea5
Fix bug in core_cm3.c atomic macros.
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Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
2019-02-16 01:08:38 +00:00
Richard Barry
3153131fa7
Add Dornerworks attribution to makefiles that build the Freedom Studio RISC-V project.
2019-02-12 02:43:28 +00:00
Richard Barry
7e08fd6d07
Add makefiles that build the FreedomStudio project (provided by Dornerworks - thanks).
2019-02-11 19:44:13 +00:00
Richard Barry
fb73829148
Ensure eTaskGetState() is brought in automatically if INCLUDE_xTaskAbortDelay is set to 1, as it is a dependency of eTaskGetState().
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Added the portTASK_FUNCTION_PROTO macros around the timer task, as the macros are already used by the idle task.
Add a PDF of the RISC-V documentation into the repo as the web page is not yet live.
2019-02-08 01:18:08 +00:00
Richard Barry
df5952f655
Add xTaskGetIdleRunTimeCounter() API function to return the run time stats counter for the idle task - useful for POSIX time implementations.
2019-01-21 23:39:48 +00:00
Richard Barry
a4941ac5db
Update main.c() for the WIN32-MingW project so the trace recorder is initialized even when the simple blinky demo is used - otherwise the trace recorder causes an exception as it is used without first being initialized.
2019-01-07 19:40:13 +00:00
Richard Barry
80df5cd517
Update the pin mux setup on the Vega board demo to enable the LED.
2018-12-31 20:14:34 +00:00
Richard Barry
11d9c440b8
Move the 'generic' version of freertos_risc_v_chip_specific_extensions.h back to a sub-directory as having it in the RISC-V port's base directory was causing SoftConsole to pick up the wrong version (for an unknown reason).
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Add a project for the Vega board's RI5CY core.
2018-12-31 18:19:52 +00:00
Richard Barry
e2af102c80
Re-org of RISC-V file structure and naming step 2.
2018-12-30 23:53:47 +00:00
Richard Barry
60b133b2c6
Move the RISC-V pxPortInitialiseStack() implementation to the assembly port file from the C port file so it can have access to the number of chip specific registers it needs to save space for on the stack.
2018-12-30 20:00:43 +00:00
Richard Barry
911a1de273
Correct accidental deletion in GenQTest.c.
2018-12-28 03:38:27 +00:00
Richard Barry
d369110167
Allow the size of the stack used by many of the standard demo/test tasks to be overridden by FreeRTOSConfig.h settings.
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Update the Freedom Studio RISC-V project so the 'full' build configuration is now functional.
2018-12-28 00:44:18 +00:00
Richard Barry
178fe4f143
Update the Freedom Studio RISC-V project so the gdbinit options are now specified on the command line.
2018-12-27 04:57:49 +00:00
Richard Barry
e5daf23d75
Update Freedom Studio RISC-V demo for the latest GCC RISC-V port - not yet tested.
2018-12-27 04:34:08 +00:00
Richard Barry
80f6f3e59b
Retarget Softconsole RISC-V demo from IGLOO2 to Renode as it can have more RAM and therefore have more test tasks running.
2018-12-24 17:48:10 +00:00
Richard Barry
2181c0375e
Backup Microsemi Renode project before adding a build configuration for the target hardware.
2018-12-19 02:56:13 +00:00
Richard Barry
8d213b42f2
Add vTimerSetReloadMode() calls to the code coverage tests.
2018-12-17 23:19:23 +00:00
Richard Barry
6edabbe7ea
Update the the MPU simulator project to exercise the timer API.
2018-12-17 22:06:58 +00:00
Richard Barry
8285ca6b5f
Update RISC-V_IGLOO2_Creative_SoftConsole demo to make use of new RISC-V porting layer structure and exercise some external interrupts - all tests currently passing in Renode.
2018-12-17 00:01:36 +00:00
Richard Barry
866635d2ad
Microsemi RISC-V project:
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Reorganize project to separate Microsemi code into its own directory.
Add many more demo and tests.
2018-12-10 20:55:32 +00:00
Richard Barry
6b37800ade
Backup checkin of MiFive demo running in ReNode emulator.
2018-12-10 05:28:05 +00:00
Richard Barry
9a136a52df
Backup check in of the Microsemi IGLOO2 Creative Board RISC-V demo - still a work in progress.
2018-12-04 01:27:06 +00:00
Richard Barry
4b9dd38d1c
Backup checking of the Freedom Studio RISC-V project - still a work in progress.
2018-12-04 01:25:53 +00:00
Richard Barry
dc99300fa9
First task running in RISC-V-Qemu-sifive_e-FreedomStudio demo.
2018-11-24 20:59:07 +00:00
Richard Barry
d0ef322b13
Add kernel code to the RISC-V-Qemu-sifive_e-FreedomStudio demo.
2018-11-24 04:42:20 +00:00
Richard Barry
f7102f2342
Add a starting point for a Freedom Studio Risc V project.
2018-11-24 03:48:55 +00:00
Richard Barry
6fab2b9e0d
Add xTaskGetApplicationTaskTagFromISR(), which is an interrupt safe version of xTaskGetApplicationTaskTagFrom().
2018-10-08 15:10:18 +00:00
Gaurav Aggarwal
1af80854e6
Fix Xtensa project file and some documentation improvements.
2018-10-02 23:54:51 +00:00
Richard Barry
c6de0001fa
Added uxTaskGetStackHighWaterMark2(), which is the same as uxTaskGetStackHighWaterMark() other than the return type.
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Allows the task name parameter passed into xTaskCreate() to be NULL.
2018-09-30 21:50:05 +00:00
Richard Barry
92ae8e7aff
Update version numbers ready for release.
2018-09-07 18:13:20 +00:00
Richard Barry
1a235efd2b
Update trace configuration files for the updated trace recorder code.
2018-09-06 18:52:45 +00:00
Richard Barry
be9c0730c3
Update trace recorder code to the latest.
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Some minor changes to enable the configREMOVE_STATIC_QUALIFIER constant to be used by those debuggers that cannot cope with statics being used.
2018-09-06 03:23:03 +00:00
Richard Barry
893db45834
Changes required for the IAR StateViewer plug-in to work with FreeRTOS V10.1.0.
2018-08-27 23:11:28 +00:00
Richard Barry
b0ce1f61c9
Move some variables from function scope back to being file scope for the benefit of some kernel aware debuggers that were left working in a non-functioning mode after the V10.1.0 release - not last change for this purpose.
2018-08-27 21:59:26 +00:00
Richard Barry
a11b1a494d
FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by FreeRTOS+TCP,
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which was brought into the main download in FreeRTOS V10.0.0. FreeRTOS+TCP can
be configured as a UDP only stack, and FreeRTOS+UDP does not contain the patches
applied to FreeRTOS+TCP.
2018-08-23 00:00:20 +00:00
Richard Barry
3a1631fda3
Update copyright date ready for tagging V10.1.0.
2018-08-22 23:23:03 +00:00
Richard Barry
bdb088e66f
Fix some build issues in older kernel demo projects.
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Update to V2.0.7 of the TCP/IP stack:
+ Multiple security improvements and fixes in packet parsing routines, DNS
caching, and TCP sequence number and ID generation.
+ Disable NBNS and LLMNR by default.
+ Add TCP hang protection by default.
We thank Ori Karliner of Zimperium zLabs Team for reporting these issues.
2018-08-22 21:29:21 +00:00
Richard Barry
fb9de58f56
Update version numbers in preparation for a new release.
2018-08-21 19:50:48 +00:00
Richard Barry
722ca8fb2b
Update demo project for Tensilita - work in progres..
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Add support for POSIX style errno - work in progress.
2018-08-21 19:37:04 +00:00
Gaurav Aggarwal
56dc0dd9b4
Merge bug fixes from Cadence
2018-08-07 07:21:07 +00:00
Richard Barry
f6cbf20019
Update RISC-V project to used official port stubs in place of third party port.
2018-07-07 21:54:41 +00:00
Richard Barry
f7fc215247
Update stream buffer tests to try resetting a statically allocated stream buffer before deleting it (tests fix in code).
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Update trace recorder library.
2018-07-02 21:58:28 +00:00
Richard Barry
9119e1e0e3
Add starting point for IGLOO2 RISV-V demo project.
2018-06-20 21:18:14 +00:00
