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armv9: register port in CMake, fix Coverity/MISRA findings
Register GCC_ARM_AARCH64_ARMV9 in portable/CMakeLists.txt so the port is selectable via CMake (source files and include directory). Address actionable findings from Coverity 2025.6.0 static analysis (--all --aggressiveness-level high) with MISRA C:2012 checking: Fixes: - Rule 7.2: add ULL suffix to portMAX_DELAY literal - Rule 8.4: add extern declarations in portmacro.h for port variables accessed from portASM.S - Rule 12.1: add explicit parentheses in PRNG shift macros and preprocessor #if expressions - Rule 17.7: explicitly discard uxPortSetInterruptMask() return value in vPortEnterCritical() - Rule 20.9: provide default for configUSE_TASK_FPU_SUPPORT before use in #if - PW.SET_BUT_NOT_USED: add (void) cast for variable used only in configASSERT Document remaining deviations (52 findings, 0 quality/security defects): - Directive 4.3: inline assembly for system register access - Rule 10.x: integer type casts for 64-bit register operations - Rule 11.x: pointer casts for stack init and MTE tag manipulation - Rule 5.8: pvPortMalloc/vPortFree macro redirect (with rationale and alternative noted) - Rule 8.6: functions defined in portASM.S invisible to C analysis - Rule 2.8: variables consumed by assembly only
This commit is contained in:
Richard Elberger
parent
a84f51003a
commit
c1b37ea35f
4 changed files with 71 additions and 7 deletions
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@ -75,6 +75,12 @@ add_library(freertos_kernel_port OBJECT
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GCC/ARM_AARCH64_SRE/port.c
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GCC/ARM_AARCH64_SRE/portASM.S>
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# ARMv9-A port for GCC (SVE2, MTE, PAC, BTI)
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$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_ARMV9>:
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GCC/ARM_AARCH64_ARMV9/port.c
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GCC/ARM_AARCH64_ARMV9/mte_port.c
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GCC/ARM_AARCH64_ARMV9/portASM.S>
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# ARMv6-M port for GCC
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$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:
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GCC/ARM_CM0/port.c
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@ -1014,6 +1020,9 @@ target_include_directories(freertos_kernel_port_headers INTERFACE
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$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_AARCH64>
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$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_SRE>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_AARCH64_SRE>
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# ARMv9-A port for GCC
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$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_AARCH64_ARMV9>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_AARCH64_ARMV9>
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# ARMv6-M port for GCC
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$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CM0>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM0>
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@ -19,6 +19,8 @@
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void * pvPortMallocTagged( size_t xSize )
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{
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/* MISRA Ref 11.5.1 [Void pointer assignment] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
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void * pv = pvPortMalloc( xSize );
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if( pv == NULL )
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@ -31,6 +33,9 @@ void * pvPortMallocTagged( size_t xSize )
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/* Tag all 16-byte granules in the allocation */
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size_t xRounded = ( xSize + 15U ) & ~15U;
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/* MISRA Ref 11.5.1 [Void pointer assignment] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
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uint8_t * pucTagPtr = ( uint8_t * ) pv;
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for( size_t i = 0; i < xRounded; i += 16U )
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@ -49,11 +54,15 @@ void vPortFreeTagged( void * pv )
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}
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/* Strip tag (top byte) to recover the canonical address for the allocator */
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/* MISRA Ref 11.6.1 [Pointer to integer conversion] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-116 */
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uintptr_t xAddr = ( uintptr_t ) pv & 0x00FFFFFFFFFFFFFFULL;
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void * pvUntagged = ( void * ) xAddr;
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/* Re-tag freed region with tag 0 (use-after-free detection).
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* Tag the first 64 bytes (covers most small allocations). */
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/* MISRA Ref 11.5.1 [Void pointer assignment] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
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uint8_t * pucPtr = ( uint8_t * ) pvUntagged;
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for( size_t i = 0; i < 64U; i += 16U )
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@ -70,6 +79,8 @@ void vPortFreeTagged( void * pv )
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void vPortMteTagStack( StackType_t * pxStack, uint32_t ulStackDepth )
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{
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/* MISRA Ref 11.5.1 [Void pointer assignment] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-115 */
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void * pvAddr = ( void * ) pxStack;
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size_t xBytes = ( size_t ) ulStackDepth * sizeof( StackType_t );
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@ -30,6 +30,20 @@
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#include <stdlib.h>
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#include <arm_acle.h>
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/*
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* MISRA C:2012 Deviations for this port file:
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*
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* MISRA Ref 4.3.1 [Inline assembly usage]
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* Rationale: This is a hardware port — inline assembly is required
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* to access AArch64 system registers (GIC, generic timer, PAC keys,
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* MTE configuration) that have no C-language equivalent.
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*
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* MISRA Ref 11.1.1, 11.5.1, 11.6.1 [Pointer type conversions]
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* Rationale: Pointer casts between void*, integer types, and function
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* pointers are required for stack initialisation, MTE tag manipulation,
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* and setting task entry points in the initial context frame.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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@ -162,20 +176,30 @@ void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
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* a non zero value to ensure interrupts don't inadvertently become unmasked before
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* the scheduler starts. As it is stored as part of the task context it will
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* automatically be set to 0 when the first task is started. */
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/* MISRA Ref 8.4.1 [Declaration shall be visible] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
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volatile uint64_t ullCriticalNesting = 9999ULL;
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/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
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* then floating point context must be saved and restored for the task. */
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/* MISRA Ref 8.4.1 [Declaration shall be visible] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
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uint64_t ullPortTaskHasFPUContext = pdFALSE;
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/* Set to 1 to pend a context switch from an ISR. */
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/* MISRA Ref 8.4.1 [Declaration shall be visible] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
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uint64_t ullPortYieldRequired = pdFALSE;
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/* Counts the interrupt nesting depth. A context switch is only performed if
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* if the nesting depth is 0. */
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/* MISRA Ref 8.4.1 [Declaration shall be visible] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
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uint64_t ullPortInterruptNesting = 0;
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/* Used in the ASM code. */
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/* MISRA Ref 8.4.1 [Declaration shall be visible] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
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__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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/*-----------------------------------------------------------*/
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@ -287,12 +311,12 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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* when configARMV9_PAC_DETERMINISTIC_KEYS is defined (for testing). */
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{
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uint64_t k0, k1, k2, k3, k4, k5, k6, k7;
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#if ( defined( configARMV9_PAC_DETERMINISTIC_KEYS ) && configARMV9_PAC_DETERMINISTIC_KEYS == 1 )
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#if ( ( defined( configARMV9_PAC_DETERMINISTIC_KEYS ) ) && ( configARMV9_PAC_DETERMINISTIC_KEYS == 1 ) )
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{
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/* Deterministic PRNG for reproducible test runs.
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* xorshift64* seeded from the stack address. */
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static uint64_t ullPacPrngState = 0xA5A5A5A5DEADBEEFULL;
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#define PAC_PRNG_NEXT( s ) do { (s) ^= (s) >> 12; (s) ^= (s) << 25; (s) ^= (s) >> 27; (s) *= 0x2545F4914F6CDD1DULL; } while(0)
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#define PAC_PRNG_NEXT( s ) do { (s) ^= ((s) >> 12); (s) ^= ((s) << 25); (s) ^= ((s) >> 27); (s) *= 0x2545F4914F6CDD1DULL; } while(0)
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PAC_PRNG_NEXT( ullPacPrngState ); k0 = ullPacPrngState;
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PAC_PRNG_NEXT( ullPacPrngState ); k1 = ullPacPrngState;
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PAC_PRNG_NEXT( ullPacPrngState ); k2 = ullPacPrngState;
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@ -422,7 +446,7 @@ void vPortEndScheduler( void )
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void vPortEnterCritical( void )
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{
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/* Mask interrupts up to the max syscall interrupt priority. */
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uxPortSetInterruptMask();
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( void ) uxPortSetInterruptMask();
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/* Now interrupts are disabled ullCriticalNesting can be accessed
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* directly. Increment ullCriticalNesting to keep a count of how many times
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@ -470,6 +494,7 @@ void FreeRTOS_Tick_Handler( void )
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/* s3_0_c12_c11_3 is ICC_RPR_EL1. */
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__asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) );
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configASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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( void ) ullRunningInterruptPriority;
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}
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#endif
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@ -618,10 +643,10 @@ void vPortTaskRegeneratePACKeys( void )
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* Called from task context. Keys take effect immediately (MSR + ISB). */
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uint64_t k0, k1, k2, k3, k4, k5, k6, k7;
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#if ( defined( configARMV9_PAC_DETERMINISTIC_KEYS ) && configARMV9_PAC_DETERMINISTIC_KEYS == 1 )
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#if ( ( defined( configARMV9_PAC_DETERMINISTIC_KEYS ) ) && ( configARMV9_PAC_DETERMINISTIC_KEYS == 1 ) )
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{
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static uint64_t ullRegenState = 0xDEADC0DEBEEF1234ULL;
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#define PAC_REGEN_NEXT( s ) do { (s) ^= (s) >> 12; (s) ^= (s) << 25; (s) ^= (s) >> 27; (s) *= 0x2545F4914F6CDD1DULL; } while(0)
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#define PAC_REGEN_NEXT( s ) do { (s) ^= ((s) >> 12); (s) ^= ((s) << 25); (s) ^= ((s) >> 27); (s) *= 0x2545F4914F6CDD1DULL; } while(0)
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PAC_REGEN_NEXT( ullRegenState ); k0 = ullRegenState;
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PAC_REGEN_NEXT( ullRegenState ); k1 = ullRegenState;
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PAC_REGEN_NEXT( ullRegenState ); k2 = ullRegenState;
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@ -59,7 +59,7 @@ typedef portBASE_TYPE BaseType_t;
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typedef uint64_t UBaseType_t;
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typedef uint64_t TickType_t;
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#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
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#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffffULL )
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/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
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* not need to be guarded with a critical section. */
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@ -105,6 +105,13 @@ extern UBaseType_t uxPortSetInterruptMask( void );
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extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
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extern void vPortInstallFreeRTOSVectorTable( void );
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/* Port variables accessed from portASM.S. */
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extern volatile uint64_t ullCriticalNesting;
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extern uint64_t ullPortTaskHasFPUContext;
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extern uint64_t ullPortYieldRequired;
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extern uint64_t ullPortInterruptNesting;
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extern const uint64_t ullMaxAPIPriorityMask;
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#define portDISABLE_INTERRUPTS() \
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__asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
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__asm volatile ( "DSB SY" ); \
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@ -140,6 +147,10 @@ void FreeRTOS_Tick_Handler( void );
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* themselves an FPU context before using any FPU instructions. If
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* configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
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* by default. */
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#ifndef configUSE_TASK_FPU_SUPPORT
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#define configUSE_TASK_FPU_SUPPORT 1
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#endif
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#if ( configUSE_TASK_FPU_SUPPORT != 2 )
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void vPortTaskUsesFPU( void );
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#else
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@ -214,7 +225,15 @@ void FreeRTOS_Tick_Handler( void );
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void *pvPortMallocTagged( size_t xSize );
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void vPortFreeTagged( void *pv );
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/* Transparent redirect: all pvPortMalloc/vPortFree calls get MTE tagging.
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* Excluded from allocator implementation files via PORTMEMORY_IMPLEMENTATION. */
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* Excluded from allocator implementation files via PORTMEMORY_IMPLEMENTATION.
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*
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* MISRA Ref 5.8.1 [Identifier with external linkage reused as macro]
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* Rationale: The macro redirect keeps all MTE logic isolated in the port
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* directory without modifying shared upstream kernel files (heap_4.c).
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* An alternative that would eliminate this deviation is to integrate the
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* MTE tagging directly into heap_4.c, guarded by configARMV9_MTE_HEAP.
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* That approach trades this violation for a modification to a shared file
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* with associated rebase/merge risk and cross-platform #include concerns. */
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#if !defined( PORTMEMORY_IMPLEMENTATION )
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#define pvPortMalloc pvPortMallocTagged
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#define vPortFree vPortFreeTagged
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