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c1b37ea35f
Register GCC_ARM_AARCH64_ARMV9 in portable/CMakeLists.txt so the port is selectable via CMake (source files and include directory). Address actionable findings from Coverity 2025.6.0 static analysis (--all --aggressiveness-level high) with MISRA C:2012 checking: Fixes: - Rule 7.2: add ULL suffix to portMAX_DELAY literal - Rule 8.4: add extern declarations in portmacro.h for port variables accessed from portASM.S - Rule 12.1: add explicit parentheses in PRNG shift macros and preprocessor #if expressions - Rule 17.7: explicitly discard uxPortSetInterruptMask() return value in vPortEnterCritical() - Rule 20.9: provide default for configUSE_TASK_FPU_SUPPORT before use in #if - PW.SET_BUT_NOT_USED: add (void) cast for variable used only in configASSERT Document remaining deviations (52 findings, 0 quality/security defects): - Directive 4.3: inline assembly for system register access - Rule 10.x: integer type casts for 64-bit register operations - Rule 11.x: pointer casts for stack init and MTE tag manipulation - Rule 5.8: pvPortMalloc/vPortFree macro redirect (with rationale and alternative noted) - Rule 8.6: functions defined in portASM.S invisible to C analysis - Rule 2.8: variables consumed by assembly only
702 lines
No EOL
28 KiB
C
702 lines
No EOL
28 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Standard includes. */
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#include <stdlib.h>
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#include <arm_acle.h>
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/*
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* MISRA C:2012 Deviations for this port file:
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*
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* MISRA Ref 4.3.1 [Inline assembly usage]
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* Rationale: This is a hardware port — inline assembly is required
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* to access AArch64 system registers (GIC, generic timer, PAC keys,
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* MTE configuration) that have no C-language equivalent.
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*
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* MISRA Ref 11.1.1, 11.5.1, 11.6.1 [Pointer type conversions]
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* Rationale: Pointer casts between void*, integer types, and function
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* pointers are required for stack initialisation, MTE tag manipulation,
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* and setting task entry points in the initial context frame.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#ifndef configUNIQUE_INTERRUPT_PRIORITIES
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#error "configUNIQUE_INTERRUPT_PRIORITIES must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
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#endif
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#ifndef configSETUP_TICK_INTERRUPT
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#error "configSETUP_TICK_INTERRUPT() must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
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#endif /* configSETUP_TICK_INTERRUPT */
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#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
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#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html"
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#endif
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#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
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#error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
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#endif
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#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
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#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
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#endif
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Check the configuration. */
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#if ( configMAX_PRIORITIES > 32 )
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#error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice."
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#endif
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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/* In case security extensions are implemented. */
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#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
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#endif
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/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
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* portmacro.h. */
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#ifndef configCLEAR_TICK_INTERRUPT
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#define configCLEAR_TICK_INTERRUPT()
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#endif
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/* A critical section is exited when the critical section nesting count reaches
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* this value. */
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#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
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/* In all GICs 255 can be written to the priority mask register to unmask all
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* (but the lowest) interrupt priority. */
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#define portUNMASK_VALUE ( 0xFFUL )
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/* Tasks are not created with a floating point context, but can be given a
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* floating point context after they have been created. A variable is stored as
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* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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* does not have an FPU context, or any other value if the task does have an FPU
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* context. */
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#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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/* Constants required to setup the initial task context. */
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#define portSP_ELx ( ( StackType_t ) 0x01 )
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#define portSP_EL0 ( ( StackType_t ) 0x00 )
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#if defined( GUEST )
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#define portEL1 ( ( StackType_t ) 0x04 )
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#define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
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#else
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#define portEL3 ( ( StackType_t ) 0x0c )
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/* At the time of writing, the BSP only supports EL3. */
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#define portINITIAL_PSTATE ( portEL3 | portSP_EL0 )
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#endif
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/* Masks all bits in the APSR other than the mode bits. */
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#define portAPSR_MODE_BITS_MASK ( 0x0C )
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/* The I bit in the DAIF bits. */
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#define portDAIF_I ( 0x80 )
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/* Macro to unmask all interrupt priorities. */
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/* s3_0_c4_c6_0 is ICC_PMR_EL1. */
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#define portCLEAR_INTERRUPT_MASK() \
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{ \
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__asm volatile ( "MSR DAIFSET, #2 \n" \
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"DSB SY \n" \
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"ISB SY \n" \
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"MSR s3_0_c4_c6_0, %0 \n" \
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"DSB SY \n" \
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"ISB SY \n" \
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"MSR DAIFCLR, #2 \n" \
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"DSB SY \n" \
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"ISB SY \n" \
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::"r" ( portUNMASK_VALUE ) ); \
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}
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/* The space on the stack required to hold the FPU registers.
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* There are 32 128-bit plus 2 64-bit status registers.*/
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#define portFPU_REGISTER_WORDS ( (32 * 2) + 2 )
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/*-----------------------------------------------------------*/
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/*
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* Starts the first task executing. This function is necessarily written in
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* assembly code so is implemented in portASM.s.
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*/
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extern void vPortRestoreTaskContext( void );
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/*
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* If the application provides an implementation of vApplicationIRQHandler(),
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* then it will get called directly without saving the FPU registers on
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* interrupt entry, and this weak implementation of
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* vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
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* it should never actually get called so its implementation contains a
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* call to configASSERT() that will always fail.
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*
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* If the application provides its own implementation of
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* vApplicationFPUSafeIRQHandler() then the implementation of
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* vApplicationIRQHandler() provided in portASM.S will save the FPU registers
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* before calling it.
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*
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* Therefore, if the application writer wants FPU registers to be saved on
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* interrupt entry their IRQ handler must be called
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* vApplicationFPUSafeIRQHandler(), and if the application writer does not want
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* FPU registers to be saved on interrupt entry their IRQ handler must be
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* called vApplicationIRQHandler().
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*/
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void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
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/*-----------------------------------------------------------*/
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/* A variable is used to keep track of the critical section nesting. This
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* variable has to be stored as part of the task context and must be initialised to
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* a non zero value to ensure interrupts don't inadvertently become unmasked before
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* the scheduler starts. As it is stored as part of the task context it will
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* automatically be set to 0 when the first task is started. */
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/* MISRA Ref 8.4.1 [Declaration shall be visible] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
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volatile uint64_t ullCriticalNesting = 9999ULL;
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/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
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* then floating point context must be saved and restored for the task. */
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/* MISRA Ref 8.4.1 [Declaration shall be visible] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
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uint64_t ullPortTaskHasFPUContext = pdFALSE;
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/* Set to 1 to pend a context switch from an ISR. */
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/* MISRA Ref 8.4.1 [Declaration shall be visible] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
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uint64_t ullPortYieldRequired = pdFALSE;
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/* Counts the interrupt nesting depth. A context switch is only performed if
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* if the nesting depth is 0. */
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/* MISRA Ref 8.4.1 [Declaration shall be visible] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
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uint64_t ullPortInterruptNesting = 0;
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/* Used in the ASM code. */
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/* MISRA Ref 8.4.1 [Declaration shall be visible] */
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/* More details at: https://github.com/FreeRTOS/FreeRTOS-Kernel/blob/main/MISRA.md#rule-84 */
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__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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/* Setup the initial stack of the task. The stack is set exactly as
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* expected by the portRESTORE_CONTEXT() macro. */
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#if ( configARMV9_MTE_STACK == 1 )
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/* Tag the entire stack with a random MTE tag using ACLE intrinsics.
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* No pointer-to-integer casts — MISRA C:2012 compliant. */
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{
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void * pvTagged = __arm_mte_create_random_tag( ( void * ) pxTopOfStack, 0 );
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size_t xStackBytes = ( size_t ) configMINIMAL_STACK_SIZE * sizeof( StackType_t );
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uint8_t * pucPtr = ( uint8_t * ) pvTagged - xStackBytes;
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for( size_t i = 0; i < xStackBytes; i += 16U )
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{
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__arm_mte_set_tag( &pucPtr[ i ] );
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}
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pxTopOfStack = ( StackType_t * ) pvTagged;
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}
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#endif /* configARMV9_MTE_STACK */
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/* First all the general purpose registers. */
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pxTopOfStack--;
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*pxTopOfStack = 0x0101010101010101ULL; /* R1 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0303030303030303ULL; /* R3 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0202020202020202ULL; /* R2 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0505050505050505ULL; /* R5 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0404040404040404ULL; /* R4 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0707070707070707ULL; /* R7 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0606060606060606ULL; /* R6 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0909090909090909ULL; /* R9 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0808080808080808ULL; /* R8 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1111111111111111ULL; /* R11 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1010101010101010ULL; /* R10 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1313131313131313ULL; /* R13 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1212121212121212ULL; /* R12 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1515151515151515ULL; /* R15 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1414141414141414ULL; /* R14 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1717171717171717ULL; /* R17 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1616161616161616ULL; /* R16 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1919191919191919ULL; /* R19 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1818181818181818ULL; /* R18 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2121212121212121ULL; /* R21 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2020202020202020ULL; /* R20 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2323232323232323ULL; /* R23 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2222222222222222ULL; /* R22 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2525252525252525ULL; /* R25 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2424242424242424ULL; /* R24 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2727272727272727ULL; /* R27 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2626262626262626ULL; /* R26 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2929292929292929ULL; /* R29 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2828282828282828ULL; /* R28 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_PSTATE;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
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#if ( configUSE_TASK_FPU_SUPPORT == 1 )
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{
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#if ( configARMV9_PAC == 1 )
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/* Per-task PAC keys: generate unique keys at creation for isolation.
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* Uses RNDR (FEAT_RNG) by default; falls back to a deterministic PRNG
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* when configARMV9_PAC_DETERMINISTIC_KEYS is defined (for testing). */
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{
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uint64_t k0, k1, k2, k3, k4, k5, k6, k7;
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#if ( ( defined( configARMV9_PAC_DETERMINISTIC_KEYS ) ) && ( configARMV9_PAC_DETERMINISTIC_KEYS == 1 ) )
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{
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/* Deterministic PRNG for reproducible test runs.
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* xorshift64* seeded from the stack address. */
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static uint64_t ullPacPrngState = 0xA5A5A5A5DEADBEEFULL;
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#define PAC_PRNG_NEXT( s ) do { (s) ^= ((s) >> 12); (s) ^= ((s) << 25); (s) ^= ((s) >> 27); (s) *= 0x2545F4914F6CDD1DULL; } while(0)
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PAC_PRNG_NEXT( ullPacPrngState ); k0 = ullPacPrngState;
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PAC_PRNG_NEXT( ullPacPrngState ); k1 = ullPacPrngState;
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PAC_PRNG_NEXT( ullPacPrngState ); k2 = ullPacPrngState;
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PAC_PRNG_NEXT( ullPacPrngState ); k3 = ullPacPrngState;
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PAC_PRNG_NEXT( ullPacPrngState ); k4 = ullPacPrngState;
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PAC_PRNG_NEXT( ullPacPrngState ); k5 = ullPacPrngState;
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PAC_PRNG_NEXT( ullPacPrngState ); k6 = ullPacPrngState;
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PAC_PRNG_NEXT( ullPacPrngState ); k7 = ullPacPrngState;
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#undef PAC_PRNG_NEXT
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}
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#else
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{
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/* Hardware RNG (FEAT_RNG): RNDR instruction. */
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__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k0));
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__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k1));
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__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k2));
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__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k3));
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__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k4));
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__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k5));
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__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k6));
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__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k7));
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}
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#endif
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/* Stack layout (reverse order — APDB first pushed, APIA last):
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* APDB Hi, APDB Lo, APDA Hi, APDA Lo, APIB Hi, APIB Lo, APIA Hi, APIA Lo */
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pxTopOfStack--; *pxTopOfStack = k7; /* APDB Hi */
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pxTopOfStack--; *pxTopOfStack = k6; /* APDB Lo */
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pxTopOfStack--; *pxTopOfStack = k5; /* APDA Hi */
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pxTopOfStack--; *pxTopOfStack = k4; /* APDA Lo */
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pxTopOfStack--; *pxTopOfStack = k3; /* APIB Hi */
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pxTopOfStack--; *pxTopOfStack = k2; /* APIB Lo */
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pxTopOfStack--; *pxTopOfStack = k1; /* APIA Hi */
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pxTopOfStack--; *pxTopOfStack = k0; /* APIA Lo */
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}
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#endif /* configARMV9_PAC */
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/* The task will start with a critical nesting count of 0 as interrupts are
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* enabled. */
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pxTopOfStack--;
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*pxTopOfStack = portNO_CRITICAL_NESTING;
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/* The task will start without a floating point context. A task that
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* uses the floating point hardware must call vPortTaskUsesFPU() before
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* executing any floating point instructions. */
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pxTopOfStack--;
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*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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#if ( configARMV9_TASK_VL == 1 )
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/* Initial ZCR_EL1: max VL (0xF = implementation maximum).
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* LDP X9, XZR reads X9 from [SP] (low addr), XZR from [SP+8] (high addr).
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* So ZCR value must be at the lower address. */
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pxTopOfStack--;
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*pxTopOfStack = 0; /* pad (XZR slot, higher address) */
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pxTopOfStack--;
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*pxTopOfStack = 0xF; /* ZCR_EL1 (X9 slot, lower address = SP) */
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#endif
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}
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#elif ( configUSE_TASK_FPU_SUPPORT == 2 )
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{
|
|
/* The task will start with a floating point context. Leave enough
|
|
* space for the registers - and ensure they are initialised to 0. */
|
|
pxTopOfStack -= portFPU_REGISTER_WORDS;
|
|
memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
|
|
|
|
/* The task will start with a critical nesting count of 0 as interrupts are
|
|
* enabled. */
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = portNO_CRITICAL_NESTING;
|
|
|
|
pxTopOfStack--;
|
|
*pxTopOfStack = pdTRUE;
|
|
ullPortTaskHasFPUContext = pdTRUE;
|
|
}
|
|
#else /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
|
{
|
|
#error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined."
|
|
}
|
|
#endif /* if ( configUSE_TASK_FPU_SUPPORT == 1 ) */
|
|
|
|
return pxTopOfStack;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
BaseType_t xPortStartScheduler( void )
|
|
{
|
|
uint64_t ulAPSR;
|
|
|
|
__asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
|
|
|
|
ulAPSR &= portAPSR_MODE_BITS_MASK;
|
|
|
|
#if defined( GUEST )
|
|
configASSERT( ulAPSR == portEL1 );
|
|
|
|
if( ulAPSR == portEL1 )
|
|
#else
|
|
configASSERT( ulAPSR == portEL3 );
|
|
|
|
if( ulAPSR == portEL3 )
|
|
#endif
|
|
{
|
|
/* Interrupts are turned off in the CPU itself to ensure a tick does
|
|
* not execute while the scheduler is being started. Interrupts are
|
|
* automatically turned back on in the CPU when the first task starts
|
|
* executing. */
|
|
portDISABLE_INTERRUPTS();
|
|
|
|
/* Start the timer that generates the tick ISR. */
|
|
configSETUP_TICK_INTERRUPT();
|
|
|
|
/* Start the first task executing. */
|
|
vPortRestoreTaskContext();
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEndScheduler( void )
|
|
{
|
|
/* Not implemented in ports where there is nothing to return to.
|
|
* Artificially force an assert. */
|
|
configASSERT( ullCriticalNesting == 1000ULL );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEnterCritical( void )
|
|
{
|
|
/* Mask interrupts up to the max syscall interrupt priority. */
|
|
( void ) uxPortSetInterruptMask();
|
|
|
|
/* Now interrupts are disabled ullCriticalNesting can be accessed
|
|
* directly. Increment ullCriticalNesting to keep a count of how many times
|
|
* portENTER_CRITICAL() has been called. */
|
|
ullCriticalNesting++;
|
|
|
|
/* This is not the interrupt safe version of the enter critical function so
|
|
* assert() if it is being called from an interrupt context. Only API
|
|
* functions that end in "FromISR" can be used in an interrupt. Only assert if
|
|
* the critical nesting count is 1 to protect against recursive calls if the
|
|
* assert function also uses a critical section. */
|
|
if( ullCriticalNesting == 1ULL )
|
|
{
|
|
configASSERT( ullPortInterruptNesting == 0 );
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortExitCritical( void )
|
|
{
|
|
if( ullCriticalNesting > portNO_CRITICAL_NESTING )
|
|
{
|
|
/* Decrement the nesting count as the critical section is being
|
|
* exited. */
|
|
ullCriticalNesting--;
|
|
|
|
/* If the nesting level has reached zero then all interrupt
|
|
* priorities must be re-enabled. */
|
|
if( ullCriticalNesting == portNO_CRITICAL_NESTING )
|
|
{
|
|
/* Critical nesting has reached zero so all interrupt priorities
|
|
* should be unmasked. */
|
|
portCLEAR_INTERRUPT_MASK();
|
|
}
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void FreeRTOS_Tick_Handler( void )
|
|
{
|
|
/* Must be the lowest possible priority. */
|
|
#if !defined( QEMU )
|
|
{
|
|
uint64_t ullRunningInterruptPriority;
|
|
/* s3_0_c12_c11_3 is ICC_RPR_EL1. */
|
|
__asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) );
|
|
configASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
|
|
( void ) ullRunningInterruptPriority;
|
|
}
|
|
#endif
|
|
|
|
/* Interrupts should not be enabled before this point. */
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
{
|
|
uint64_t ulMaskBits;
|
|
|
|
__asm volatile ( "MRS %0, DAIF" : "=r" ( ulMaskBits )::"memory" );
|
|
configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
|
|
}
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
/* Set interrupt mask before altering scheduler structures. The tick
|
|
* handler runs at the lowest priority, so interrupts cannot already be masked,
|
|
* so there is no need to save and restore the current mask value. It is
|
|
* necessary to turn off interrupts in the CPU itself while the ICCPMR is being
|
|
* updated. */
|
|
/* s3_0_c4_c6_0 is ICC_PMR_EL1. */
|
|
__asm volatile ( "MSR s3_0_c4_c6_0, %0 \n"
|
|
"DSB SY \n"
|
|
"ISB SY \n"
|
|
::"r" ( ( uint64_t ) configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
|
|
|
|
/* Ok to enable interrupts after the interrupt source has been cleared. */
|
|
configCLEAR_TICK_INTERRUPT();
|
|
/* NOTE: Do NOT call portENABLE_INTERRUPTS() here - we are inside the IRQ
|
|
* handler and re-enabling DAIF.I would allow nested timer interrupts that
|
|
* corrupt the handler's stack frame. The PMR-based priority masking is
|
|
* sufficient to allow higher-priority interrupts if needed. */
|
|
|
|
/* Increment the RTOS tick. */
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
{
|
|
ullPortYieldRequired = pdTRUE;
|
|
}
|
|
|
|
/* Restore interrupt priority mask (PMR) without enabling DAIF.I.
|
|
* The ERET at the end of the IRQ handler will restore PSTATE. */
|
|
__asm volatile ( "MSR s3_0_c4_c6_0, %0 \n"
|
|
"DSB SY \n"
|
|
"ISB SY \n"
|
|
::"r" ( ( uint64_t ) 0xff ) );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_TASK_FPU_SUPPORT != 2 )
|
|
|
|
void vPortTaskUsesFPU( void )
|
|
{
|
|
/* A task is registering the fact that it needs an FPU context. Set the
|
|
* FPU flag (which is saved as part of the task context). */
|
|
ullPortTaskHasFPUContext = pdTRUE;
|
|
|
|
/* Consider initialising the FPSR here - but probably not necessary in
|
|
* AArch64. */
|
|
}
|
|
|
|
#endif /* configUSE_TASK_FPU_SUPPORT */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
|
|
{
|
|
if( uxNewMaskValue == pdFALSE )
|
|
{
|
|
portCLEAR_INTERRUPT_MASK();
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxPortSetInterruptMask( void )
|
|
{
|
|
uint32_t ulReturn;
|
|
uint64_t ullPMRValue;
|
|
|
|
/* Interrupt in the CPU must be turned off while the ICCPMR is being
|
|
* updated. */
|
|
portDISABLE_INTERRUPTS();
|
|
/* s3_0_c4_c6_0 is ICC_PMR_EL1. */
|
|
__asm volatile ( "MRS %0, s3_0_c4_c6_0" : "=r" ( ullPMRValue ) );
|
|
|
|
if( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
|
|
{
|
|
/* Interrupts were already masked. */
|
|
ulReturn = pdTRUE;
|
|
}
|
|
else
|
|
{
|
|
ulReturn = pdFALSE;
|
|
/* s3_0_c4_c6_0 is ICC_PMR_EL1. */
|
|
__asm volatile ( "MSR s3_0_c4_c6_0, %0 \n"
|
|
"DSB SY \n"
|
|
"ISB SY \n"
|
|
::"r" ( ( uint64_t ) configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
|
|
}
|
|
|
|
/* Re-enable DAIF.I now that PMR is set. PMR-based priority masking
|
|
* prevents interrupts below configMAX_API_CALL_INTERRUPT_PRIORITY
|
|
* from being taken. This matches the upstream ARM_AARCH64_SRE port. */
|
|
portENABLE_INTERRUPTS();
|
|
|
|
return ulReturn;
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
|
|
void vPortValidateInterruptPriority( void )
|
|
{
|
|
/* The following assertion will fail if a service routine (ISR) for
|
|
* an interrupt that has been assigned a priority above
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
|
|
* function. ISR safe FreeRTOS API functions must *only* be called
|
|
* from interrupts that have been assigned a priority at or below
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
*
|
|
* Numerically low interrupt priority numbers represent logically high
|
|
* interrupt priorities, therefore the priority of the interrupt must
|
|
* be set to a value equal to or numerically *higher* than
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
*
|
|
* FreeRTOS maintains separate thread and ISR API functions to ensure
|
|
* interrupt entry is as fast and simple as possible. */
|
|
uint64_t ullRunningInterruptPriority;
|
|
/* s3_0_c12_c11_3 is ICC_RPR_EL1. */
|
|
__asm volatile ( "MRS %0, s3_0_c12_c11_3" : "=r" ( ullRunningInterruptPriority ) );
|
|
|
|
configASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
|
|
}
|
|
|
|
#endif /* configASSERT_DEFINED */
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
|
|
{
|
|
( void ) ulICCIAR;
|
|
configASSERT( ( volatile void * ) NULL );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configARMV9_PAC == 1 )
|
|
|
|
void vPortTaskRegeneratePACKeys( void )
|
|
{
|
|
/* Regenerate PAC keys for the current task using RNDR.
|
|
* Called from task context. Keys take effect immediately (MSR + ISB). */
|
|
uint64_t k0, k1, k2, k3, k4, k5, k6, k7;
|
|
|
|
#if ( ( defined( configARMV9_PAC_DETERMINISTIC_KEYS ) ) && ( configARMV9_PAC_DETERMINISTIC_KEYS == 1 ) )
|
|
{
|
|
static uint64_t ullRegenState = 0xDEADC0DEBEEF1234ULL;
|
|
#define PAC_REGEN_NEXT( s ) do { (s) ^= ((s) >> 12); (s) ^= ((s) << 25); (s) ^= ((s) >> 27); (s) *= 0x2545F4914F6CDD1DULL; } while(0)
|
|
PAC_REGEN_NEXT( ullRegenState ); k0 = ullRegenState;
|
|
PAC_REGEN_NEXT( ullRegenState ); k1 = ullRegenState;
|
|
PAC_REGEN_NEXT( ullRegenState ); k2 = ullRegenState;
|
|
PAC_REGEN_NEXT( ullRegenState ); k3 = ullRegenState;
|
|
PAC_REGEN_NEXT( ullRegenState ); k4 = ullRegenState;
|
|
PAC_REGEN_NEXT( ullRegenState ); k5 = ullRegenState;
|
|
PAC_REGEN_NEXT( ullRegenState ); k6 = ullRegenState;
|
|
PAC_REGEN_NEXT( ullRegenState ); k7 = ullRegenState;
|
|
#undef PAC_REGEN_NEXT
|
|
}
|
|
#else
|
|
{
|
|
__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k0));
|
|
__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k1));
|
|
__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k2));
|
|
__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k3));
|
|
__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k4));
|
|
__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k5));
|
|
__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k6));
|
|
__asm volatile("mrs %0, s3_3_c2_c4_0" : "=r"(k7));
|
|
}
|
|
#endif
|
|
|
|
__asm volatile(
|
|
"msr APIAKeyLo_EL1, %0\n"
|
|
"msr APIAKeyHi_EL1, %1\n"
|
|
"msr APIBKeyLo_EL1, %2\n"
|
|
"msr APIBKeyHi_EL1, %3\n"
|
|
"msr APDAKeyLo_EL1, %4\n"
|
|
"msr APDAKeyHi_EL1, %5\n"
|
|
"msr APDBKeyLo_EL1, %6\n"
|
|
"msr APDBKeyHi_EL1, %7\n"
|
|
"isb\n"
|
|
:: "r"(k0), "r"(k1), "r"(k2), "r"(k3),
|
|
"r"(k4), "r"(k5), "r"(k6), "r"(k7)
|
|
);
|
|
}
|
|
|
|
#endif /* configARMV9_PAC */
|
|
|
|
#if ( configARMV9_TASK_VL == 1 )
|
|
|
|
void vPortTaskSetVL( uint32_t ulVL )
|
|
{
|
|
/* Set the SVE vector length for the current task.
|
|
* ulVL is the ZCR_EL1.LEN field value: VL = (LEN+1) * 128 bits.
|
|
* E.g., ulVL=0 → 128-bit, ulVL=1 → 256-bit, ulVL=3 → 512-bit.
|
|
* The actual VL is clamped by the implementation's maximum.
|
|
* ZCR_EL1 = S3_0_C1_C2_0 */
|
|
__asm volatile( "MSR S3_0_C1_C2_0, %0\n ISB\n" :: "r"( (uint64_t)ulVL ) );
|
|
}
|
|
|
|
#endif /* configARMV9_TASK_VL */ |