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armv9: reconcile critical section, add stack overflow MTE fix, per-task VL
- Restore portENABLE_INTERRUPTS() in uxPortSetInterruptMask to match upstream ARM_AARCH64_SRE port behavior (PMR masking is sufficient). - Fix stack_macros.h method 2 overflow check: strip MTE address tags from pxStack before dereferencing watermark bytes (prevents tag mismatch fault) and before pointer comparison (prevents false trigger). - Add configARMV9_TASK_VL support: save/restore ZCR_EL1 per-task, vPortTaskSetVL() API, initial frame includes ZCR=0xF (max VL). Validated on FVP at sve.veclen=4; veclen=2 has a known RDVL coherency issue under investigation with Arm.
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3 changed files with 35 additions and 5 deletions
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@ -103,10 +103,10 @@
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#define taskCHECK_FOR_STACK_OVERFLOW() \
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do \
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{ \
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const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \
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const uint32_t * const pulStack = ( uint32_t * ) portSTRIP_ADDRESS_TAG( pxCurrentTCB->pxStack ); \
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const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5U; \
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\
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if( ( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) || \
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if( ( portSTRIP_ADDRESS_TAG( pxCurrentTCB->pxTopOfStack ) <= ( StackType_t * ) portSTRIP_ADDRESS_TAG( pxCurrentTCB->pxStack ) + portSTACK_LIMIT_PADDING ) || \
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( pulStack[ 0 ] != ulCheckValue ) || \
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( pulStack[ 1 ] != ulCheckValue ) || \
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( pulStack[ 2 ] != ulCheckValue ) || \
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@ -339,6 +339,16 @@ StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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* executing any floating point instructions. */
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pxTopOfStack--;
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*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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#if ( configARMV9_TASK_VL == 1 )
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/* Initial ZCR_EL1: max VL (0xF = implementation maximum).
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* LDP X9, XZR reads X9 from [SP] (low addr), XZR from [SP+8] (high addr).
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* So ZCR value must be at the lower address. */
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pxTopOfStack--;
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*pxTopOfStack = 0; /* pad (XZR slot, higher address) */
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pxTopOfStack--;
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*pxTopOfStack = 0xF; /* ZCR_EL1 (X9 slot, lower address = SP) */
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#endif
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}
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#elif ( configUSE_TASK_FPU_SUPPORT == 2 )
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{
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@ -556,9 +566,10 @@ UBaseType_t uxPortSetInterruptMask( void )
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::"r" ( ( uint64_t ) configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
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}
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/* Do NOT call portENABLE_INTERRUPTS() here. On FVP the timer PPI has
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* priority 0 which bypasses PMR masking. Keep DAIF.I=1 for the entire
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* critical section; vPortExitCritical will clear it. */
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/* Re-enable DAIF.I now that PMR is set. PMR-based priority masking
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* prevents interrupts below configMAX_API_CALL_INTERRUPT_PRIORITY
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* from being taken. This matches the upstream ARM_AARCH64_SRE port. */
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portENABLE_INTERRUPTS();
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return ulReturn;
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}
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@ -650,3 +661,17 @@ void vPortTaskRegeneratePACKeys( void )
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}
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#endif /* configARMV9_PAC */
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#if ( configARMV9_TASK_VL == 1 )
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void vPortTaskSetVL( uint32_t ulVL )
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{
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/* Set the SVE vector length for the current task.
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* ulVL is the ZCR_EL1.LEN field value: VL = (LEN+1) * 128 bits.
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* E.g., ulVL=0 → 128-bit, ulVL=1 → 256-bit, ulVL=3 → 512-bit.
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* The actual VL is clamped by the implementation's maximum.
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* ZCR_EL1 = S3_0_C1_C2_0 */
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__asm volatile( "MSR S3_0_C1_C2_0, %0\n ISB\n" :: "r"( (uint64_t)ulVL ) );
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}
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#endif /* configARMV9_TASK_VL */
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@ -226,6 +226,11 @@ void FreeRTOS_Tick_Handler( void );
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void vPortTaskRegeneratePACKeys( void );
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#endif
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/* ---- Armv9 per-task SVE vector length ---- */
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#if ( configARMV9_TASK_VL == 1 )
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void vPortTaskSetVL( uint32_t ulVL );
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#endif
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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}
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