The warnings triggered by -Wshift-negative-value are in the
upstream code, and presumably "correct"
Change-Id: I1cf20e12208f493c69e0852477d800cd417a67c6
It was actually defined but not actually mapped in.
Also shut up a warning in the peakmeter code when not using a color
display.
Both caught by -Wunused-const-variable
Change-Id: Ie2403c0cd77e6fdf3468fd45115a1e0f228238e8
-Wunterminates-string-initialization will complain if we try to shove
a "string" into a fixed array that is too small. Sometimes this is
intentional; when you are merely using "string" as a standin for
"non-terminated sequence of bytes". In these cases we need to mark
the "string" as "not actually a string" with an attribute. Applies to
GCC >=8, but this warning isn't pulled in by -Wextra until GCC >= 15.
Change-Id: Ib94410a22f4587940b16cf03d539fbadc3373686
This keeps all the old descriptions etc that were there before.
Had to fix up the tools some more, honestly feels better to just
rewrite this crap in perl.
Change-Id: Ic15deae200c143ba5457423e12c81f871c0fef09
To keep the code size small, this hardcodes the D-Cache line
size and set/way information (which is defined by the target
and should be fixed for a given CPU) and assumes there is only
one level of cache.
Change-Id: Ia6d0e6a87b5dbfc6c39bda83b58461ed8767edf6
Cortex-M processors don't have an MMU, but can still have caches
that need software management, so on those platforms we don't want
to include the MMU related functions.
While here, remove an outdated section of a comment referring to
deprecated cache maintenance functions which no longer exist.
Change-Id: I6f0fe694560bdee25ed7c69a846bf46e3e544cb1
This is an internal macro which is only used if has_sct()
is set by the generator, so don't generate it if we don't
need to.
Change-Id: I7ad51ad34ecabd833b84a270b5046e77131dcb41
When registers have lot of 1- and 2-bit fields it's possible
to exceed the 13 argument limit. Usually this only shows up
when programming a configuration register, but it's annoying
to have to split up the write. 20 arguments should be enough
to avoid that.
Change-Id: I6240fae4a51ae14600afcfb8a4e3f1e983cbffa6
Add a relative version of the register/field read/write operations
which takes a base address (which may be a void pointer or integer)
and computes the register address using offsets.
Change-Id: I7c012192e67adcd675a0fc1975ca4b16ed87bcac
Floating instances don't have an address and will only generate
child nodes and registers with offsets. The 'nochild' flag will
disable generating the children for a node but will generate the
node's own address, which can be used to generate base addresses.
Change-Id: Ib1014de94531436d5708db46aa684741e7740ace
Register offsets are defined as the address of the register minus
the address of the parent node. If enabled by the generator, these
will be emitted alongside defines for the node base addresses.
This allows the base address to be stored in a variable, and the
offset can be used to access registers relative to the base.
Change-Id: I15576aeb2945293a259007da7f00a26055f4d0f0
sample_to_chunk last value was ignored in some cases leading to invalid sample value in lookup_table.
Fixes FS#13600
Change-Id: I8f066966e15c384d3185f689b68a2cc2a3abad1d
Instead of 'this phrase missing entirely [...]' followed by the
verbatim phrase copied from English, instead the message now
reads 'the 'PHRASE_ID' is missing entirely [...]. This allows
the warning to be self-contained.
Change-Id: I413c29e0c1f6616e74d875d197b34c4724330d67
It may make sense to only show these in the
file browser, where you'd expect to do more
general file operations involving other folders.
Change-Id: I008569d2017811ee54b4449acb30359843f35294
Cortex-M7 support was added in GCC 5, while GCC 4.9 only
supports the M4. The instruction set is almost identical
between both processors; the only difference is that the
M7 supports double-precision floating point and the M4
doesn't.
Since Rockbox currently doesn't use the FPU, building M7
targets as M4 works fine.
Change-Id: I5880d6e81a85fa9b3e16e08d57e7955b4493df0b
Some assembly routines don't work on Thumb as-is. For now
just disable these so the codecs compile.
Affected codecs:
- libflac
- libmad
- libspeex
- libtta
- libwavpack
A few DSP routines need to be disabled for the same reason:
- crossfeed_process
- crossfeed_meier_process
- resample_hermite
- filter_process
- sample_output_stereo
Change-Id: I277e0719652096745a19a7e2b597eff32d8e1553
We can't use Operand2 with register based shifts on ARMv7-M as it
isn't supported in the Thumb encoding. Instead, perform the shift
separately.
Change-Id: Ie96aa0a565e98bbca724dffc2ffc6d64fdb5d7c3
GAS warns about unpredictable behavior of "ldr sp, [a1], #4"
that exists on Cortex-M3 (errata 752419) but this warning is
incorrectly issued on other cores too (eg, Cortex-M7).
Since the fix is just one extra instruction we may as well
apply the workaround for all Cortex-M targets.
Change-Id: I0c2aa46837f776d67d0236b627af1572aa5ab307
Even though ARMv7-M has a hardware divider, 64-bit division is
handled in software and needs a div0 handler. The libgcc routines
call __aeabi_{i,l}div0 so we alias those to __div0.
Change-Id: I5152c43d39e25e03f31404753f13978a614aca06
Currently, only the development bootloader can be built successfully.
This is a part of the large iPod Nano 3G and iPod Nano 4G support patch.
Credit: Cástor Muñoz <cmvidal@gmail.com>
Change-Id: I74ea0da999ddb1d8ce5d0f5434141b3f0b5f7448
Currently, only a bootloader can be built successfully. The development bootloader is functional, it enables further progress on the port.
This is a part of the large iPod Nano 3G and iPod Nano 4G support patch.
Credit: Cástor Muñoz <cmvidal@gmail.com>
Change-Id: Idf85e42334b0e0ae36f9ed273e2940d5d7736e34
M-profile cores manage interrupts differently from classic cores
and lack the FIQ. Split the interrupt management parts out into
separate headers but keep the endian swapping routines (which are
not profile-dependent) in the common system-arm header.
The initial part of the vector table is common to all Cortex-M
CPUs and is intended to be included by the target linker script,
with the vendor-specific part of the vector table appended to it.
Change-Id: Ib2ad5b9dc41db27940e39033cfef4308923db66d
On Cortex-M we can just return SP directly, which will return
PSP/MSP depending on the current processor mode.
Note that unwarminder doesn't handle Cortex-M exception frames
yet, so a panic from an interrupt handler will currently stop
at the exception boundary.
Change-Id: I8818126c065c896d781bd52b877965a4094dee2a
GCC cannot compile the existing assembly here on ARMv7-M,
claiming impossible constraints. It is actually possible to
compile if the input arguments (addresses and sizes) are
first moved to a high register so as not to conflict with
the use of r0-r7 in ldm/stm -- this is exactly what GCC does
for ARMv6, but it won't do it on ARMv7-M for some reason.
We can get a result similar to the ARMv6 code by manually
moving the inputs into temporaries, but the generated code
is a actually a bit smaller on ARMv7-M if the r0-r7 block is
shifted up to r3-r10. This only works since ARMv7-M supports
the 32-bit Thumb encoding -- 16-bit Thumb can't represent an
ldm/stm instruction of this type.
It's worth #ifdef'ing the code because although the ARMv7-M
version works on ARMv6 too, it spills a lot of registers on
the stack even though register use is mostly similar.
Change-Id: I9bc8b5c76e198aecfd0a0e7a2158b1c00f82c4df
