forked from len0rd/rockbox
arm: implement get_sp for Cortex-M
On Cortex-M we can just return SP directly, which will return PSP/MSP depending on the current processor mode. Note that unwarminder doesn't handle Cortex-M exception frames yet, so a panic from an interrupt handler will currently stop at the exception boundary. Change-Id: I8818126c065c896d781bd52b877965a4094dee2a
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8d5fd1b20b
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2 changed files with 10 additions and 4 deletions
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@ -1,8 +1,10 @@
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backtrace-unwarminder.c
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get_sp.S
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unwarm_arm.c
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unwarm.c
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unwarminder.c
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unwarmmem.c
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unwarm_thumb.c
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safe_read.S
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#if defined(CPU_ARM_CLASSIC)
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get_sp.S
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#endif
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@ -6,14 +6,18 @@
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*
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* On RaaA we are called in USER mode most probably and
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* cpsr mangling is restricted. We simply copy SP value
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* in this situation
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* in this situation.
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*
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* For Cortex-M, SP is banked to MSP/PSP based on the current
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* processor mode. Exception stack frames can be detected and
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* backtraced across, so we can just return SP like RaaA does.
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*/
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.section .text
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.type __get_sp,%function
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.global __get_sp
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__get_sp:
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#if (CONFIG_PLATFORM & PLATFORM_NATIVE)
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#if (CONFIG_PLATFORM & PLATFORM_NATIVE) && defined(CPU_ARM_CLASSIC)
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mrs r1, cpsr /* save current state */
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orr r0, r1, #0xc0
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msr cpsr_c, r0 /* disable IRQ and FIQ */
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@ -28,7 +32,7 @@ call_from_exception:
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get_sp:
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#endif
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mov r0, sp /* get SP */
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#if (CONFIG_PLATFORM & PLATFORM_NATIVE)
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#if (CONFIG_PLATFORM & PLATFORM_NATIVE) && defined(CPU_ARM_CLASSIC)
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msr cpsr_c, r1 /* restore mode */
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#endif
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bx lr
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