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arm: add ARMv7-M version of ARMv6 mixer code

GCC cannot compile the existing assembly here on ARMv7-M,
claiming impossible constraints. It is actually possible to
compile if the input arguments (addresses and sizes) are
first moved to a high register so as not to conflict with
the use of r0-r7 in ldm/stm -- this is exactly what GCC does
for ARMv6, but it won't do it on ARMv7-M for some reason.

We can get a result similar to the ARMv6 code by manually
moving the inputs into temporaries, but the generated code
is a actually a bit smaller on ARMv7-M if the r0-r7 block is
shifted up to r3-r10. This only works since ARMv7-M supports
the 32-bit Thumb encoding -- 16-bit Thumb can't represent an
ldm/stm instruction of this type.

It's worth #ifdef'ing the code because although the ARMv7-M
version works on ARMv6 too, it spills a lot of registers on
the stack even though register use is mostly similar.

Change-Id: I9bc8b5c76e198aecfd0a0e7a2158b1c00f82c4df
This commit is contained in:
Aidan MacDonald 2024-11-14 14:47:45 +00:00 committed by Solomon Peachy
parent a1bf19de36
commit c33aafcd5c

View file

@ -78,6 +78,27 @@ static FORCE_INLINE void write_samples(void *out,
if (LIKELY(amp == MIX_AMP_UNITY))
{
/* Channel is unity amplitude */
#if defined(CPU_ARM_MICRO) && ARCH_VERSION >= 7
asm volatile (
"ands r4, %2, #0x1f \n"
"beq 2f \n"
"1: \n"
"ldr r3, [%1], #4 \n"
"subs r4, r4, #4 \n"
"str r3, [%0], #4 \n"
"bne 1b \n"
"bics %2, %2, #0x1f \n"
"beq 3f \n"
"2: \n"
"ldmia %1!, { r3-r10 } \n"
"subs %2, %2, #32 \n"
"stmia %0!, { r3-r10 } \n"
"bhi 2b \n"
"3: \n"
: "+lr"(out), "+lr"(src), "+r"(size)
:
: "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10");
#else
asm volatile (
"ands r1, %2, #0x1f \n"
"beq 2f \n"
@ -97,6 +118,7 @@ static FORCE_INLINE void write_samples(void *out,
: "+r"(out), "+r"(src), "+r"(size)
:
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7");
#endif
}
else
{