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https://github.com/Rockbox/rockbox.git
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d14ddcafd5
To keep the code size small, this hardcodes the D-Cache line size and set/way information (which is defined by the target and should be fixed for a given CPU) and assumes there is only one level of cache. Change-Id: Ia6d0e6a87b5dbfc6c39bda83b58461ed8767edf6
112 lines
2.8 KiB
C
112 lines
2.8 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2025 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "cpucache-armv7m.h"
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#include "cortex-m/cache.h"
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/*
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* The target must define DCACHE_WAYS and DCACHE_SETS to the number
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* of sets/ways in the L1 data cache. DCACHE_LINESIZE should be set
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* to the writeback granule size.
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*
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* If you have multiple levels of caches (L2 or higher) then you'll
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* probably need to change things here to handle it properly.
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*/
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#define DCACHE_WAYSHIFT \
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(DCACHE_WAYS <= 1 ? 0 : __builtin_clzl(DCACHE_WAYS - 1))
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static inline void full_dcache_op(volatile uint32_t *cache_reg)
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{
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arm_dsb();
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for (uint32_t way = 0; way < DCACHE_WAYS; ++way)
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{
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uint32_t arg = way << DCACHE_WAYSHIFT;
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for (uint32_t set = 0; set < DCACHE_SETS; ++set)
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{
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*cache_reg = arg;
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arg += DCACHE_LINESIZE;
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}
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}
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arm_dsb();
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}
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static inline void range_dcache_op(const void *base, unsigned int size,
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volatile uint32_t *cache_reg)
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{
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arm_dsb();
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uint32_t addr = (uint32_t)base;
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uint32_t endaddr = addr + size;
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while (addr < endaddr)
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{
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*cache_reg = addr;
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addr += DCACHE_LINESIZE;
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}
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arm_dsb();
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}
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void commit_dcache(void)
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{
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full_dcache_op(®_CACHE_DCCSW);
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}
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void commit_discard_dcache(void)
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{
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full_dcache_op(®_CACHE_DCCISW);
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}
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void commit_discard_idcache(void)
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{
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full_dcache_op(®_CACHE_DCCISW);
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REG_CACHE_ICIALLU = 0;
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arm_isb();
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}
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void __discard_idcache(void)
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{
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full_dcache_op(®_CACHE_DCISW);
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REG_CACHE_ICIALLU = 0;
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arm_isb();
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}
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void commit_discard_dcache_range(const void *base, unsigned int size)
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{
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range_dcache_op(base, size, ®_CACHE_DCCIMVAC);
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}
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void commit_dcache_range(const void *base, unsigned int size)
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{
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range_dcache_op(base, size, ®_CACHE_DCCMVAC);
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}
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void discard_dcache_range(const void *base, unsigned int size)
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{
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range_dcache_op(base, size, ®_CACHE_DCIMVAC);
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}
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