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Author SHA1 Message Date
Aidan MacDonald
d14ddcafd5 arm: implement cache maintenance ops for ARMv7-M
To keep the code size small, this hardcodes the D-Cache line
size and set/way information (which is defined by the target
and should be fixed for a given CPU) and assumes there is only
one level of cache.

Change-Id: Ia6d0e6a87b5dbfc6c39bda83b58461ed8767edf6
2025-04-21 13:07:38 -04:00