Michael Giacomelli deaef503bb opus: ARMv5E SILK resampler interpolation ... On ARMv5E and later the fixed-phase FIR cycles at 8, 12 and 16 kHz load two samples a word and take two coefficients a word from a literal pool; smla<x><y> picks the halves, so an odd-aligned window costs nothing. Outputs are paired as two interleaved accumulator chains. The FIR buffer is now word aligned. Generated by silk/arm/gen_resampler_armv5e.py. Bit-exact; OPUS_ARM_NO_SILK_ASM disables it, and config.h sets that on M-profile cores. Measured on the Clip+, silk_5.opus (WB SILK): 20.93 -> 15.84 MHz, -24.3%. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Change-Id: Ibec71fd52542f768f22e2970c9f8c45118c708b9		2026-09-30 08:21:46 -04:00
..
codecs	opus: ARMv5E SILK resampler interpolation	2026-09-30 08:21:46 -04:00
dsp	dsp: Add missing .type <symbol>, %function to arm asm	2026-09-19 21:18:30 -04:00
metadata	Add "rbfs" prefix to native filesystem functions	2026-09-17 16:22:31 -04:00
test	warble: zero the mp3entry before reading metadata	2026-09-28 16:35:14 -04:00
platform.h	firmware: refactor CACHEALIGN_BITS/SIZE defines	2026-03-06 14:49:00 +00:00
rbcodec.make	rbcodec: Force use of -O2 for dsp code	2025-09-06 08:44:32 -04:00
rbcodecconfig-example.h	Enable setting of global output samplerate on certain targets.	2013-07-06 04:22:04 +02:00
rbcodecplatform-unix.h	Add "rbfs" prefix to native filesystem functions	2026-09-17 16:22:31 -04:00
SOURCES	rbcodec dsp: Move dsp_sample_io_configure() to its own file	2022-12-22 17:20:14 -05:00