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d8f099f937
flash_init() identifies a chip by looking its READ ID device code up in
device_code[] and taking the capacity from device_info[] at the same
index. device_code[] had seven entries and device_info[] eight: 0xd5
(16 Gbit) was dropped when the table was transcribed from the OF. Every
code after the gap picked up the capacity one row up, so a 0xd7
(32 Gbit, 4 GiB) part was sized at 2 GiB.
On a generic rk2705 that halved total_phy_sec to 4194304, and the FTL
looked for its tables in the wrong place and read erased flash. With the
entry restored it reports 8388608, matching the chip and the host-side
dump of the same unit.
The OF's own table, as it appears in its NAND bootloader:
76 79 f1 da dc d3 d5 d7 00 00 02 00 00 00 04 00 ...
A compile-time check now fails the build if the two tables differ in
length again. Also fixes two register addresses in the same loop that
were missing a digit (0x180E204/0x180E208 for 0x180E8204/0x180E8208);
they are stored for reference only and nothing reads them.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Change-Id: Ia70c249eea2e44ea34aef52d8ae20860b2b5db9d
507 lines
13 KiB
C
507 lines
13 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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*
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* Copyright (C) 2010 by Bertrik Sikken
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "system.h"
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#include "string.h"
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#include "nand-target.h"
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#include "rk27xx.h"
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/* Raw nand handling functions based on OF disassembly and partially inspired
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* by Rockchip patent.
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*
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* This was written as documentation while the FTL was still unknown and sat
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* under `#if 0` for years. The Scheme A FTL is now reconstructed
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* (ftl-scheme-a.c) and needs exactly what this provides: chip detection and
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* the geometry derived from it, plus chip select. Enabled.
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*/
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/* MAX_FLASH_NUM now in nand-target.h */
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#define CMD_READ_STATUS 0x70
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#define CMD_RESET 0xFF
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#define CMD_READ_ID 0x90
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#define READ_PAGE_CMD 0x30
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/* struct flashspec_t now lives in nand-target.h - the Scheme A FTL's flash
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* primitives (flash-rk27xx.c) need the geometry flash_init() derives here. */
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/* holds nand chips characteristics */
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struct flashspec_t flash_spec[MAX_FLASH_NUM];
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/* sum of all phy sectors in all chips */
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uint32_t total_phy_sec;
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enum vendor_t {
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SAMSUNG,
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TOSHIBA,
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HYNIX,
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INFINEON,
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MICRON,
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RENESAS,
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ST
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};
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/* taken from OF - one entry per device_info[] row. The OF's table is
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* 76 79 f1 da dc d3 d5 d7; 0xd5 was once missing here, which shifted every
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* later code onto the capacity one row up and sized a 4 GiB 0xd7 part as
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* 2 GiB. */
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const uint8_t device_code[] = {
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0x76,
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0x79,
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0xf1,
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0xda,
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0xdc,
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0xd3,
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0xd5,
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0xd7
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};
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const uint8_t manufacture_id_tbl[] =
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{
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0xec, /* SAMSUNG */
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0x98, /* TOSHIBA */
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0xad, /* HYNIX */
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0xc1, /* INFINEON */
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0x2c, /* MICRON */
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0x07, /* RENESAS */
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0x20 /* ST */
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};
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/* phisical sectors */
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const uint32_t device_info[] =
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{
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0x20000, /* 64M, small page */
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0x40000, /* 128M, small page */
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0x40000, /* 128M, large page */
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0x80000, /* 256M, large page */
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0x100000, /* 512M, large page */
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0x200000, /* 1G, large page */
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0x400000, /* 2G, large page */
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0x800000 /* 4G, large page */
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};
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/* device_code[j] is looked up and device_info[j] used - a length mismatch
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* silently mis-sizes every chip after the gap */
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extern char device_tables_match[(sizeof(device_code) ==
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sizeof(device_info) / sizeof(device_info[0])) ? 1 : -1];
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/* State the OF keeps across flash operations.
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*
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* These were referenced by flash_init() but never transcribed - the block was
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* under `#if 0`, so nothing caught it. They are defined here with the values
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* flash_init() assigns, which is all the current code needs:
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*
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* - mlc_refresh_row: row scheduled for refresh after a sector needed
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* BCH_REFRESH_THRESHOLD corrected bits; 0xffffffff means "none pending".
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* - flash_pend_cmd: the OF defers a program command so it can be merged with
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* the next one (cache programming). Nothing issues one yet.
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* - flash_read_status_cmd: READ STATUS opcode, which differs on some
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* multi-plane parts.
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*/
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uint32_t mlc_refresh_row;
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struct flash_pend_cmd_t
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{
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uint8_t valid;
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uint32_t row;
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};
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struct flash_pend_cmd_t flash_pend_cmd;
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uint8_t flash_read_status_cmd;
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static int flash_delay(int n)
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{
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volatile int cnt, i, j;
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for (j=0; j<n; j++)
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for (i=0; i<10000; i++)
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cnt++;
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return cnt;
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}
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static void flash_wait_busy(void)
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{
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unsigned int i;
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for (i=0; i<0x2000; i++)
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{
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if (FMCTL & FM_RDY)
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break;
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flash_delay(1);
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}
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}
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void flash_chip_deselect(void)
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{
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uint32_t tmp;
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tmp = FMCTL;
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tmp &= 0xf0;
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FMCTL = tmp;
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}
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void flash_chip_select(uint8_t chip)
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{
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uint32_t tmp;
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/* Maybe we should handle IOMUX here as well?
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* for chip == 0,1 it is not needed
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*/
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tmp = FMCTL;
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tmp &= 0xf0;
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tmp |= 1<<chip;
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FMCTL = tmp;
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}
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void flash_init(void)
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{
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uint8_t buff[5]; /* buff for CMD_READ_ID response */
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uint32_t i,j;
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mlc_refresh_row = 0xffffffff;
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total_phy_sec = 0;
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flash_pend_cmd.valid = 0;
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flash_read_status_cmd = CMD_READ_STATUS;
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FMWAIT = 0x1081;
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FLCTL = FL_RST;
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for (i=0; i< MAX_FLASH_NUM; i++)
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{
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/* Redundat - we will use special macros
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* just for reference what OF does
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*/
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flash_spec[i].cmd = 0x180E8200 + (i<<9);
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flash_spec[i].addr = 0x180E8204 + (i<<9);
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flash_spec[i].data = 0x180E8208 + (i<<9);
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flash_chip_select(i);
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FLASH_CMD(i) = CMD_RESET; /* write cmd to flash chip */
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flash_delay(2);
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flash_wait_busy();
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FLASH_CMD(i) = CMD_READ_ID; /* write cmd to flash chip */
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FLASH_ADDR(i) = 0x00;
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/* read 5 bytes of CMD_READ_ID response */
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for (j=0; j<5; j++)
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buff[j] = FLASH_DATA(i);
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flash_chip_deselect();
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/* Get the vendor of the chip */
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for (j=0; j<sizeof(manufacture_id_tbl); j++)
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{
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/* store Manufacturer index */
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if (manufacture_id_tbl[j] == buff[0])
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{
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flash_spec[i].vendor = j;
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}
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}
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for (j=0; j<sizeof(device_code); j++)
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{
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/* look for matching device code
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* and store total phys sectors
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*/
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if (device_code[j] == buff[1])
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{
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flash_spec[i].total_phy_sec = device_info[j];
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break;
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}
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}
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/* div zero is fatal for us (not for OF :P) */
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if (flash_spec[i].total_phy_sec == 0)
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continue;
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/* loc_7e8 */
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flash_spec[i].mlc = 0;
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flash_spec[i].large = 0;
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flash_spec[i].five = 1;
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flash_spec[i].mul_plane = 1;
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flash_spec[i].interleave = 0;
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flash_spec[i].cache_prog = buff[2] & 0x80;
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/* flash access time (ns) */
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switch (buff[3] & 0x88)
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{
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case 0:
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flash_spec[i].access_time = 50;
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break;
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case 0x80:
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flash_spec[i].access_time = 25;
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break;
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case 0x08:
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flash_spec[i].access_time = 20;
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break;
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default:
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flash_spec[i].access_time = 60;
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}
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/* set_large
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* j is index in device_code table
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*/
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if (j < 2)
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{
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/* small block */
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flash_spec[i].large = 0;
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flash_spec[i].sec_per_page_raw = 1;
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flash_spec[i].sec_per_block_raw = 32;
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}
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else
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{
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flash_spec[i].large = 1;
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if (j == 2)
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flash_spec[i].five = 0;
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/* cell type */
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flash_spec[i].mlc = (buff[2] >> 2) & 0x03;
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flash_spec[i].sec_per_page_raw = 2; /* 1KB~8KB */
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/* set_sec_per_page_raw */
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flash_spec[i].sec_per_page_raw <<= (buff[3] & 3);
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flash_spec[i].sec_per_block_raw = 128; /* 64KB~512KB */
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/* set_sec_per_block_raw */
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flash_spec[i].sec_per_block_raw <<= ((buff[3]>>4) & 3);
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/* simult_prog */
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if (buff[2] & 0x30)
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{
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/* buff4_mulplane */
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flash_spec[i].mul_plane <<= ((buff[4]>>2) & 3);
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}
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/* set_interleave */
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if (flash_spec[i].vendor == TOSHIBA)
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{
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flash_spec[i].mul_plane = 2;
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if (buff[2] & 3)
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flash_spec[i].interleave = 1;
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}
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} /* large block */
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if (flash_spec[i].mul_plane > 2)
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{
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flash_spec[i].mul_plane = 2;
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flash_spec[i].interleave = 1;
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}
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flash_spec[i].page_per_block_raw = flash_spec[i].sec_per_block_raw/flash_spec[i].sec_per_page_raw;
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flash_spec[i].page_per_block = flash_spec[i].page_per_block_raw * flash_spec[i].mul_plane;
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flash_spec[i].sec_per_block = flash_spec[i].sec_per_block_raw * flash_spec[i].mul_plane;
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flash_spec[i].sec_per_page = flash_spec[i].sec_per_page_raw * flash_spec[i].mul_plane;
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flash_spec[i].total_bloks = flash_spec[i].total_phy_sec / flash_spec[i].sec_per_block;
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total_phy_sec += flash_spec[i].total_phy_sec;
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}
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/* read ID block and propagate SysDiskCapacity and SysResBlocks */
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}
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/* read single page in unbuffered mode */
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void flash_read_page_raw(int page, unsigned char *pgbuff)
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{
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unsigned int i;
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flash_chip_select(0);
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flash_delay(2);
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flash_wait_busy();
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/* setup transfer */
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FLASH_CMD(0) = 0x00;
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FLASH_ADDR(0) = 0x00; /* column */
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FLASH_ADDR(0) = 0x00; /* column */
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FLASH_ADDR(0) = page & 0xff; /* row */
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FLASH_ADDR(0) = (page >> 8) & 0xff; /* row */
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FLASH_ADDR(0) = (page >> 16) & 0xff; /* row */
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FLASH_CMD(0) = READ_PAGE_CMD;
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/* wait for operation complete */
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flash_wait_busy();
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/* copy data from page register
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* WARNING flash page size can be different
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* for different chips. This value should be set
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* based on initialization.
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*/
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for (i=0; i<(4096+218); i++)
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pgbuff[i] = FLASH_DATA(0);
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flash_chip_deselect();
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}
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void flash_read_sector(int page, unsigned char *secbuf, int nsec)
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{
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int i = 0;
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int j = 0;
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/* WARNING this code assumes only one nand chip
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* it does not handle data split across different nand chips
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*/
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flash_chip_select(0);
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flash_delay(2);
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flash_wait_busy();
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FLASH_CMD(0) = 0x00;
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FLASH_ADDR(0) = 0x00;
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FLASH_ADDR(0) = 0x00;
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FLASH_ADDR(0) = page & 0xff;
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FLASH_ADDR(0) = (page >> 8) & 0xff;
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FLASH_ADDR(0) = (page >> 16) & 0xff;
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FLASH_CMD(0) = READ_PAGE_CMD;
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flash_delay(1);
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/* wait for operation to complete */
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flash_wait_busy();
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/* enables hw checksum control most probably */
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BCHCTL = 1;
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/* This initializes the transfer from the nand to the buffer
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* There are 4 consecutive hw buffers 512 bytes long for data (PAGE_BUF)
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* and 4 16 bytes long for metadata (BCH code checksum) (SPARE_BUF)
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*/
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FLCTL = 0xA24;
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/* This scheme utilizes some overlap in data transfers -
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* data are copied from buffer to the mem and from nand to the buf
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* at the same time.
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*/
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while (++j < nsec)
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{
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/* wait for transfer to complete */
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while(! (FLCTL & FL_RDY));
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/* initialize next transfer to the next buffer */
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FLCTL = 0xA24 | (j&3)<<3;
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/* copy data chunk */
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memcpy(secbuf, (((unsigned char *)&PAGE_BUF)+((i&3)<<9)), 0x200);
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secbuf += 0x200;
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/* copy metadata chunk (BCH)
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* in real application this can be discarded
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*/
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memcpy(secbuf, (((unsigned char *)&SPARE_BUF)+((i&3)<<4)), 0x10);
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secbuf += 0x10;
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i++;
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}
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/* wait for transfer to complete */
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while(! (FLCTL & FL_RDY));
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/* copy data chunk */
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memcpy(secbuf, (((unsigned char *)&PAGE_BUF)+((i&3)<<9)), 0x200);
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secbuf += 0x200;
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/* copy metadata chunk (BCH)
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* in real application this can be discarded
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*/
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memcpy(secbuf, (((unsigned char *)&SPARE_BUF)+((i&3)<<4)), 0x10);
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secbuf += 0x10;
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flash_chip_deselect();
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}
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const struct nand_device_info_type* nand_get_device_type(uint32_t bank);
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uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
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void* sparebuffer, uint32_t doecc,
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uint32_t checkempty)
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{
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/* TODO implement */
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(void)bank;
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(void)page;
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(void)databuffer;
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(void)sparebuffer;
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(void)doecc;
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(void)checkempty;
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return 0;
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}
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uint32_t nand_write_page(uint32_t bank, uint32_t page, void* databuffer,
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void* sparebuffer, uint32_t doecc)
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{
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/* TODO implement */
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(void)bank;
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(void)page;
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(void)databuffer;
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(void)sparebuffer;
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(void)doecc;
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return 0;
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}
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uint32_t nand_block_erase(uint32_t bank, uint32_t page)
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{
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/* TODO implement */
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(void)bank;
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(void)page;
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return 0;
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}
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uint32_t nand_reset(uint32_t bank)
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{
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/* TODO implement */
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(void)bank;
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return 0;
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}
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uint32_t nand_device_init(void)
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{
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/* TODO implement */
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return 0;
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}
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void nand_power_up(void)
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{
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/* TODO implement */
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}
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void nand_power_down(void)
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{
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/* TODO implement */
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}
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void nand_set_active(void)
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{
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/* TODO implement */
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}
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long nand_last_activity(void)
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{
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/* TODO implement */
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return 0;
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}
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int nand_spinup_time(void)
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{
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return 0;
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}
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