mirror of
https://github.com/Rockbox/rockbox.git
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190 lines
8.9 KiB
C
190 lines
8.9 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* stm32h743 version: 1.0
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* stm32h743 authors: Aidan MacDonald
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_PWR_H__
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#define __HEADERGEN_PWR_H__
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#include "macro.h"
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#define STA_PWR (0x58024800)
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#define REG_PWR_CR1 st_reg(PWR_CR1)
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#define STA_PWR_CR1 (0x58024800 + 0x0)
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#define STO_PWR_CR1 (0x0)
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#define STT_PWR_CR1 STIO_32_RW
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#define STN_PWR_CR1 PWR_CR1
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#define BP_PWR_CR1_ALS 17
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#define BM_PWR_CR1_ALS 0x60000
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#define BF_PWR_CR1_ALS(v) (((v) & 0x3) << 17)
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#define BFM_PWR_CR1_ALS(v) BM_PWR_CR1_ALS
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#define BF_PWR_CR1_ALS_V(e) BF_PWR_CR1_ALS(BV_PWR_CR1_ALS__##e)
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#define BFM_PWR_CR1_ALS_V(v) BM_PWR_CR1_ALS
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#define BP_PWR_CR1_SVOS 14
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#define BM_PWR_CR1_SVOS 0xc000
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#define BF_PWR_CR1_SVOS(v) (((v) & 0x3) << 14)
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#define BFM_PWR_CR1_SVOS(v) BM_PWR_CR1_SVOS
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#define BF_PWR_CR1_SVOS_V(e) BF_PWR_CR1_SVOS(BV_PWR_CR1_SVOS__##e)
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#define BFM_PWR_CR1_SVOS_V(v) BM_PWR_CR1_SVOS
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#define BP_PWR_CR1_PLS 5
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#define BM_PWR_CR1_PLS 0xe0
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#define BF_PWR_CR1_PLS(v) (((v) & 0x7) << 5)
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#define BFM_PWR_CR1_PLS(v) BM_PWR_CR1_PLS
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#define BF_PWR_CR1_PLS_V(e) BF_PWR_CR1_PLS(BV_PWR_CR1_PLS__##e)
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#define BFM_PWR_CR1_PLS_V(v) BM_PWR_CR1_PLS
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#define BP_PWR_CR1_AVDEN 16
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#define BM_PWR_CR1_AVDEN 0x10000
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#define BF_PWR_CR1_AVDEN(v) (((v) & 0x1) << 16)
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#define BFM_PWR_CR1_AVDEN(v) BM_PWR_CR1_AVDEN
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#define BF_PWR_CR1_AVDEN_V(e) BF_PWR_CR1_AVDEN(BV_PWR_CR1_AVDEN__##e)
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#define BFM_PWR_CR1_AVDEN_V(v) BM_PWR_CR1_AVDEN
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#define BP_PWR_CR1_FLPS 9
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#define BM_PWR_CR1_FLPS 0x200
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#define BF_PWR_CR1_FLPS(v) (((v) & 0x1) << 9)
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#define BFM_PWR_CR1_FLPS(v) BM_PWR_CR1_FLPS
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#define BF_PWR_CR1_FLPS_V(e) BF_PWR_CR1_FLPS(BV_PWR_CR1_FLPS__##e)
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#define BFM_PWR_CR1_FLPS_V(v) BM_PWR_CR1_FLPS
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#define BP_PWR_CR1_DBP 8
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#define BM_PWR_CR1_DBP 0x100
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#define BF_PWR_CR1_DBP(v) (((v) & 0x1) << 8)
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#define BFM_PWR_CR1_DBP(v) BM_PWR_CR1_DBP
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#define BF_PWR_CR1_DBP_V(e) BF_PWR_CR1_DBP(BV_PWR_CR1_DBP__##e)
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#define BFM_PWR_CR1_DBP_V(v) BM_PWR_CR1_DBP
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#define BP_PWR_CR1_PVDE 4
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#define BM_PWR_CR1_PVDE 0x10
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#define BF_PWR_CR1_PVDE(v) (((v) & 0x1) << 4)
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#define BFM_PWR_CR1_PVDE(v) BM_PWR_CR1_PVDE
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#define BF_PWR_CR1_PVDE_V(e) BF_PWR_CR1_PVDE(BV_PWR_CR1_PVDE__##e)
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#define BFM_PWR_CR1_PVDE_V(v) BM_PWR_CR1_PVDE
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#define BP_PWR_CR1_LPDS 0
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#define BM_PWR_CR1_LPDS 0x1
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#define BF_PWR_CR1_LPDS(v) (((v) & 0x1) << 0)
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#define BFM_PWR_CR1_LPDS(v) BM_PWR_CR1_LPDS
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#define BF_PWR_CR1_LPDS_V(e) BF_PWR_CR1_LPDS(BV_PWR_CR1_LPDS__##e)
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#define BFM_PWR_CR1_LPDS_V(v) BM_PWR_CR1_LPDS
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#define REG_PWR_CSR1 st_reg(PWR_CSR1)
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#define STA_PWR_CSR1 (0x58024800 + 0x4)
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#define STO_PWR_CSR1 (0x4)
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#define STT_PWR_CSR1 STIO_32_RW
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#define STN_PWR_CSR1 PWR_CSR1
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#define BP_PWR_CSR1_ACTVOS 14
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#define BM_PWR_CSR1_ACTVOS 0xc000
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#define BF_PWR_CSR1_ACTVOS(v) (((v) & 0x3) << 14)
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#define BFM_PWR_CSR1_ACTVOS(v) BM_PWR_CSR1_ACTVOS
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#define BF_PWR_CSR1_ACTVOS_V(e) BF_PWR_CSR1_ACTVOS(BV_PWR_CSR1_ACTVOS__##e)
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#define BFM_PWR_CSR1_ACTVOS_V(v) BM_PWR_CSR1_ACTVOS
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#define BP_PWR_CSR1_AVDO 16
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#define BM_PWR_CSR1_AVDO 0x10000
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#define BF_PWR_CSR1_AVDO(v) (((v) & 0x1) << 16)
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#define BFM_PWR_CSR1_AVDO(v) BM_PWR_CSR1_AVDO
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#define BF_PWR_CSR1_AVDO_V(e) BF_PWR_CSR1_AVDO(BV_PWR_CSR1_AVDO__##e)
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#define BFM_PWR_CSR1_AVDO_V(v) BM_PWR_CSR1_AVDO
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#define BP_PWR_CSR1_ACTVOSRDY 13
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#define BM_PWR_CSR1_ACTVOSRDY 0x2000
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#define BF_PWR_CSR1_ACTVOSRDY(v) (((v) & 0x1) << 13)
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#define BFM_PWR_CSR1_ACTVOSRDY(v) BM_PWR_CSR1_ACTVOSRDY
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#define BF_PWR_CSR1_ACTVOSRDY_V(e) BF_PWR_CSR1_ACTVOSRDY(BV_PWR_CSR1_ACTVOSRDY__##e)
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#define BFM_PWR_CSR1_ACTVOSRDY_V(v) BM_PWR_CSR1_ACTVOSRDY
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#define BP_PWR_CSR1_PVDO 4
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#define BM_PWR_CSR1_PVDO 0x10
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#define BF_PWR_CSR1_PVDO(v) (((v) & 0x1) << 4)
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#define BFM_PWR_CSR1_PVDO(v) BM_PWR_CSR1_PVDO
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#define BF_PWR_CSR1_PVDO_V(e) BF_PWR_CSR1_PVDO(BV_PWR_CSR1_PVDO__##e)
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#define BFM_PWR_CSR1_PVDO_V(v) BM_PWR_CSR1_PVDO
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#define REG_PWR_CR3 st_reg(PWR_CR3)
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#define STA_PWR_CR3 (0x58024800 + 0xc)
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#define STO_PWR_CR3 (0xc)
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#define STT_PWR_CR3 STIO_32_RW
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#define STN_PWR_CR3 PWR_CR3
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#define BP_PWR_CR3_USB33RDY 26
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#define BM_PWR_CR3_USB33RDY 0x4000000
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#define BF_PWR_CR3_USB33RDY(v) (((v) & 0x1) << 26)
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#define BFM_PWR_CR3_USB33RDY(v) BM_PWR_CR3_USB33RDY
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#define BF_PWR_CR3_USB33RDY_V(e) BF_PWR_CR3_USB33RDY(BV_PWR_CR3_USB33RDY__##e)
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#define BFM_PWR_CR3_USB33RDY_V(v) BM_PWR_CR3_USB33RDY
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#define BP_PWR_CR3_USBREGEN 25
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#define BM_PWR_CR3_USBREGEN 0x2000000
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#define BF_PWR_CR3_USBREGEN(v) (((v) & 0x1) << 25)
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#define BFM_PWR_CR3_USBREGEN(v) BM_PWR_CR3_USBREGEN
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#define BF_PWR_CR3_USBREGEN_V(e) BF_PWR_CR3_USBREGEN(BV_PWR_CR3_USBREGEN__##e)
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#define BFM_PWR_CR3_USBREGEN_V(v) BM_PWR_CR3_USBREGEN
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#define BP_PWR_CR3_USB33DEN 24
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#define BM_PWR_CR3_USB33DEN 0x1000000
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#define BF_PWR_CR3_USB33DEN(v) (((v) & 0x1) << 24)
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#define BFM_PWR_CR3_USB33DEN(v) BM_PWR_CR3_USB33DEN
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#define BF_PWR_CR3_USB33DEN_V(e) BF_PWR_CR3_USB33DEN(BV_PWR_CR3_USB33DEN__##e)
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#define BFM_PWR_CR3_USB33DEN_V(v) BM_PWR_CR3_USB33DEN
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#define BP_PWR_CR3_VBRS 9
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#define BM_PWR_CR3_VBRS 0x200
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#define BF_PWR_CR3_VBRS(v) (((v) & 0x1) << 9)
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#define BFM_PWR_CR3_VBRS(v) BM_PWR_CR3_VBRS
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#define BF_PWR_CR3_VBRS_V(e) BF_PWR_CR3_VBRS(BV_PWR_CR3_VBRS__##e)
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#define BFM_PWR_CR3_VBRS_V(v) BM_PWR_CR3_VBRS
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#define BP_PWR_CR3_VBE 8
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#define BM_PWR_CR3_VBE 0x100
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#define BF_PWR_CR3_VBE(v) (((v) & 0x1) << 8)
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#define BFM_PWR_CR3_VBE(v) BM_PWR_CR3_VBE
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#define BF_PWR_CR3_VBE_V(e) BF_PWR_CR3_VBE(BV_PWR_CR3_VBE__##e)
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#define BFM_PWR_CR3_VBE_V(v) BM_PWR_CR3_VBE
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#define BP_PWR_CR3_SCUEN 2
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#define BM_PWR_CR3_SCUEN 0x4
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#define BF_PWR_CR3_SCUEN(v) (((v) & 0x1) << 2)
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#define BFM_PWR_CR3_SCUEN(v) BM_PWR_CR3_SCUEN
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#define BF_PWR_CR3_SCUEN_V(e) BF_PWR_CR3_SCUEN(BV_PWR_CR3_SCUEN__##e)
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#define BFM_PWR_CR3_SCUEN_V(v) BM_PWR_CR3_SCUEN
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#define BP_PWR_CR3_LDOEN 1
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#define BM_PWR_CR3_LDOEN 0x2
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#define BF_PWR_CR3_LDOEN(v) (((v) & 0x1) << 1)
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#define BFM_PWR_CR3_LDOEN(v) BM_PWR_CR3_LDOEN
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#define BF_PWR_CR3_LDOEN_V(e) BF_PWR_CR3_LDOEN(BV_PWR_CR3_LDOEN__##e)
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#define BFM_PWR_CR3_LDOEN_V(v) BM_PWR_CR3_LDOEN
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#define BP_PWR_CR3_BYPASS 0
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#define BM_PWR_CR3_BYPASS 0x1
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#define BF_PWR_CR3_BYPASS(v) (((v) & 0x1) << 0)
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#define BFM_PWR_CR3_BYPASS(v) BM_PWR_CR3_BYPASS
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#define BF_PWR_CR3_BYPASS_V(e) BF_PWR_CR3_BYPASS(BV_PWR_CR3_BYPASS__##e)
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#define BFM_PWR_CR3_BYPASS_V(v) BM_PWR_CR3_BYPASS
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#define REG_PWR_D3CR st_reg(PWR_D3CR)
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#define STA_PWR_D3CR (0x58024800 + 0x18)
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#define STO_PWR_D3CR (0x18)
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#define STT_PWR_D3CR STIO_32_RW
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#define STN_PWR_D3CR PWR_D3CR
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#define BP_PWR_D3CR_VOS 14
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#define BM_PWR_D3CR_VOS 0xc000
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#define BV_PWR_D3CR_VOS__VOS3 0x1
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#define BV_PWR_D3CR_VOS__VOS2 0x2
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#define BV_PWR_D3CR_VOS__VOS1 0x3
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#define BF_PWR_D3CR_VOS(v) (((v) & 0x3) << 14)
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#define BFM_PWR_D3CR_VOS(v) BM_PWR_D3CR_VOS
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#define BF_PWR_D3CR_VOS_V(e) BF_PWR_D3CR_VOS(BV_PWR_D3CR_VOS__##e)
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#define BFM_PWR_D3CR_VOS_V(v) BM_PWR_D3CR_VOS
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#define BP_PWR_D3CR_VOSRDY 13
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#define BM_PWR_D3CR_VOSRDY 0x2000
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#define BF_PWR_D3CR_VOSRDY(v) (((v) & 0x1) << 13)
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#define BFM_PWR_D3CR_VOSRDY(v) BM_PWR_D3CR_VOSRDY
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#define BF_PWR_D3CR_VOSRDY_V(e) BF_PWR_D3CR_VOSRDY(BV_PWR_D3CR_VOSRDY__##e)
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#define BFM_PWR_D3CR_VOSRDY_V(v) BM_PWR_D3CR_VOSRDY
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#endif /* __HEADERGEN_PWR_H__*/
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