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stm32h743: add intitial register definitions

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Change-Id: I0c9f94103eedb333b2167a8ef49568c8e50c2218
This commit is contained in:
Aidan MacDonald 2025-02-17 02:21:27 +00:00 • committed by Solomon Peachy
parent d68efd3363
commit bf689e9b5d
10 changed files with 5091 additions and 0 deletions
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49
firmware/target/arm/stm32/stm32h7/flash.h Normal file
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stm32h743 version: 1.0
* stm32h743 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_FLASH_H__
#define __HEADERGEN_FLASH_H__
#include "macro.h"
#define STA_FLASH (0x52002000)
#define REG_FLASH_ACR st_reg(FLASH_ACR)
#define STA_FLASH_ACR (0x52002000 + 0x0)
#define STO_FLASH_ACR (0x0)
#define STT_FLASH_ACR STIO_32_RW
#define STN_FLASH_ACR FLASH_ACR
#define BP_FLASH_ACR_WRHIGHFREQ 3
#define BM_FLASH_ACR_WRHIGHFREQ 0x38
#define BF_FLASH_ACR_WRHIGHFREQ(v) (((v) & 0x7) << 3)
#define BFM_FLASH_ACR_WRHIGHFREQ(v) BM_FLASH_ACR_WRHIGHFREQ
#define BF_FLASH_ACR_WRHIGHFREQ_V(e) BF_FLASH_ACR_WRHIGHFREQ(BV_FLASH_ACR_WRHIGHFREQ__##e)
#define BFM_FLASH_ACR_WRHIGHFREQ_V(v) BM_FLASH_ACR_WRHIGHFREQ
#define BP_FLASH_ACR_LATENCY 0
#define BM_FLASH_ACR_LATENCY 0xf
#define BF_FLASH_ACR_LATENCY(v) (((v) & 0xf) << 0)
#define BFM_FLASH_ACR_LATENCY(v) BM_FLASH_ACR_LATENCY
#define BF_FLASH_ACR_LATENCY_V(e) BF_FLASH_ACR_LATENCY(BV_FLASH_ACR_LATENCY__##e)
#define BFM_FLASH_ACR_LATENCY_V(v) BM_FLASH_ACR_LATENCY
#endif /* __HEADERGEN_FLASH_H__*/

247
firmware/target/arm/stm32/stm32h7/fmc.h Normal file
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stm32h743 version: 1.0
* stm32h743 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_FMC_H__
#define __HEADERGEN_FMC_H__
#include "macro.h"
#define STA_FMC (0x52004000)
#define REG_FMC_BCR(_n1) st_reg(FMC_BCR(_n1))
#define STA_FMC_BCR(_n1) (0x52004000 + 0x0 + (_n1) * 0x8)
#define STO_FMC_BCR(_n1) (0x0 + (_n1) * 0x8)
#define STT_FMC_BCR(_n1) STIO_32_RW
#define STN_FMC_BCR(_n1) FMC_BCR
#define BP_FMC_BCR_BMAP 24
#define BM_FMC_BCR_BMAP 0x3000000
#define BF_FMC_BCR_BMAP(v) (((v) & 0x3) << 24)
#define BFM_FMC_BCR_BMAP(v) BM_FMC_BCR_BMAP
#define BF_FMC_BCR_BMAP_V(e) BF_FMC_BCR_BMAP(BV_FMC_BCR_BMAP__##e)
#define BFM_FMC_BCR_BMAP_V(v) BM_FMC_BCR_BMAP
#define BP_FMC_BCR_FMCEN 31
#define BM_FMC_BCR_FMCEN 0x80000000
#define BF_FMC_BCR_FMCEN(v) (((v) & 0x1) << 31)
#define BFM_FMC_BCR_FMCEN(v) BM_FMC_BCR_FMCEN
#define BF_FMC_BCR_FMCEN_V(e) BF_FMC_BCR_FMCEN(BV_FMC_BCR_FMCEN__##e)
#define BFM_FMC_BCR_FMCEN_V(v) BM_FMC_BCR_FMCEN
#define BP_FMC_BCR_WFDIS 21
#define BM_FMC_BCR_WFDIS 0x200000
#define BF_FMC_BCR_WFDIS(v) (((v) & 0x1) << 21)
#define BFM_FMC_BCR_WFDIS(v) BM_FMC_BCR_WFDIS
#define BF_FMC_BCR_WFDIS_V(e) BF_FMC_BCR_WFDIS(BV_FMC_BCR_WFDIS__##e)
#define BFM_FMC_BCR_WFDIS_V(v) BM_FMC_BCR_WFDIS
#define REG_FMC_SDCR(_n1) st_reg(FMC_SDCR(_n1))
#define STA_FMC_SDCR(_n1) (0x52004000 + 0x140 + (_n1) * 0x4)
#define STO_FMC_SDCR(_n1) (0x140 + (_n1) * 0x4)
#define STT_FMC_SDCR(_n1) STIO_32_RW
#define STN_FMC_SDCR(_n1) FMC_SDCR
#define BP_FMC_SDCR_RPIPE 13
#define BM_FMC_SDCR_RPIPE 0x6000
#define BF_FMC_SDCR_RPIPE(v) (((v) & 0x3) << 13)
#define BFM_FMC_SDCR_RPIPE(v) BM_FMC_SDCR_RPIPE
#define BF_FMC_SDCR_RPIPE_V(e) BF_FMC_SDCR_RPIPE(BV_FMC_SDCR_RPIPE__##e)
#define BFM_FMC_SDCR_RPIPE_V(v) BM_FMC_SDCR_RPIPE
#define BP_FMC_SDCR_SDCLK 10
#define BM_FMC_SDCR_SDCLK 0xc00
#define BF_FMC_SDCR_SDCLK(v) (((v) & 0x3) << 10)
#define BFM_FMC_SDCR_SDCLK(v) BM_FMC_SDCR_SDCLK
#define BF_FMC_SDCR_SDCLK_V(e) BF_FMC_SDCR_SDCLK(BV_FMC_SDCR_SDCLK__##e)
#define BFM_FMC_SDCR_SDCLK_V(v) BM_FMC_SDCR_SDCLK
#define BP_FMC_SDCR_CAS 7
#define BM_FMC_SDCR_CAS 0x180
#define BF_FMC_SDCR_CAS(v) (((v) & 0x3) << 7)
#define BFM_FMC_SDCR_CAS(v) BM_FMC_SDCR_CAS
#define BF_FMC_SDCR_CAS_V(e) BF_FMC_SDCR_CAS(BV_FMC_SDCR_CAS__##e)
#define BFM_FMC_SDCR_CAS_V(v) BM_FMC_SDCR_CAS
#define BP_FMC_SDCR_MWID 4
#define BM_FMC_SDCR_MWID 0x30
#define BF_FMC_SDCR_MWID(v) (((v) & 0x3) << 4)
#define BFM_FMC_SDCR_MWID(v) BM_FMC_SDCR_MWID
#define BF_FMC_SDCR_MWID_V(e) BF_FMC_SDCR_MWID(BV_FMC_SDCR_MWID__##e)
#define BFM_FMC_SDCR_MWID_V(v) BM_FMC_SDCR_MWID
#define BP_FMC_SDCR_NR 2
#define BM_FMC_SDCR_NR 0xc
#define BF_FMC_SDCR_NR(v) (((v) & 0x3) << 2)
#define BFM_FMC_SDCR_NR(v) BM_FMC_SDCR_NR
#define BF_FMC_SDCR_NR_V(e) BF_FMC_SDCR_NR(BV_FMC_SDCR_NR__##e)
#define BFM_FMC_SDCR_NR_V(v) BM_FMC_SDCR_NR
#define BP_FMC_SDCR_NC 0
#define BM_FMC_SDCR_NC 0x3
#define BF_FMC_SDCR_NC(v) (((v) & 0x3) << 0)
#define BFM_FMC_SDCR_NC(v) BM_FMC_SDCR_NC
#define BF_FMC_SDCR_NC_V(e) BF_FMC_SDCR_NC(BV_FMC_SDCR_NC__##e)
#define BFM_FMC_SDCR_NC_V(v) BM_FMC_SDCR_NC
#define BP_FMC_SDCR_RBURST 12
#define BM_FMC_SDCR_RBURST 0x1000
#define BF_FMC_SDCR_RBURST(v) (((v) & 0x1) << 12)
#define BFM_FMC_SDCR_RBURST(v) BM_FMC_SDCR_RBURST
#define BF_FMC_SDCR_RBURST_V(e) BF_FMC_SDCR_RBURST(BV_FMC_SDCR_RBURST__##e)
#define BFM_FMC_SDCR_RBURST_V(v) BM_FMC_SDCR_RBURST
#define BP_FMC_SDCR_WP 9
#define BM_FMC_SDCR_WP 0x200
#define BF_FMC_SDCR_WP(v) (((v) & 0x1) << 9)
#define BFM_FMC_SDCR_WP(v) BM_FMC_SDCR_WP
#define BF_FMC_SDCR_WP_V(e) BF_FMC_SDCR_WP(BV_FMC_SDCR_WP__##e)
#define BFM_FMC_SDCR_WP_V(v) BM_FMC_SDCR_WP
#define BP_FMC_SDCR_NB 6
#define BM_FMC_SDCR_NB 0x40
#define BF_FMC_SDCR_NB(v) (((v) & 0x1) << 6)
#define BFM_FMC_SDCR_NB(v) BM_FMC_SDCR_NB
#define BF_FMC_SDCR_NB_V(e) BF_FMC_SDCR_NB(BV_FMC_SDCR_NB__##e)
#define BFM_FMC_SDCR_NB_V(v) BM_FMC_SDCR_NB
#define REG_FMC_SDTR(_n1) st_reg(FMC_SDTR(_n1))
#define STA_FMC_SDTR(_n1) (0x52004000 + 0x148 + (_n1) * 0x4)
#define STO_FMC_SDTR(_n1) (0x148 + (_n1) * 0x4)
#define STT_FMC_SDTR(_n1) STIO_32_RW
#define STN_FMC_SDTR(_n1) FMC_SDTR
#define BP_FMC_SDTR_TRCD 24
#define BM_FMC_SDTR_TRCD 0xf000000
#define BF_FMC_SDTR_TRCD(v) (((v) & 0xf) << 24)
#define BFM_FMC_SDTR_TRCD(v) BM_FMC_SDTR_TRCD
#define BF_FMC_SDTR_TRCD_V(e) BF_FMC_SDTR_TRCD(BV_FMC_SDTR_TRCD__##e)
#define BFM_FMC_SDTR_TRCD_V(v) BM_FMC_SDTR_TRCD
#define BP_FMC_SDTR_TRP 20
#define BM_FMC_SDTR_TRP 0xf00000
#define BF_FMC_SDTR_TRP(v) (((v) & 0xf) << 20)
#define BFM_FMC_SDTR_TRP(v) BM_FMC_SDTR_TRP
#define BF_FMC_SDTR_TRP_V(e) BF_FMC_SDTR_TRP(BV_FMC_SDTR_TRP__##e)
#define BFM_FMC_SDTR_TRP_V(v) BM_FMC_SDTR_TRP
#define BP_FMC_SDTR_TWR 16
#define BM_FMC_SDTR_TWR 0xf0000
#define BF_FMC_SDTR_TWR(v) (((v) & 0xf) << 16)
#define BFM_FMC_SDTR_TWR(v) BM_FMC_SDTR_TWR
#define BF_FMC_SDTR_TWR_V(e) BF_FMC_SDTR_TWR(BV_FMC_SDTR_TWR__##e)
#define BFM_FMC_SDTR_TWR_V(v) BM_FMC_SDTR_TWR
#define BP_FMC_SDTR_TRC 12
#define BM_FMC_SDTR_TRC 0xf000
#define BF_FMC_SDTR_TRC(v) (((v) & 0xf) << 12)
#define BFM_FMC_SDTR_TRC(v) BM_FMC_SDTR_TRC
#define BF_FMC_SDTR_TRC_V(e) BF_FMC_SDTR_TRC(BV_FMC_SDTR_TRC__##e)
#define BFM_FMC_SDTR_TRC_V(v) BM_FMC_SDTR_TRC
#define BP_FMC_SDTR_TRAS 8
#define BM_FMC_SDTR_TRAS 0xf00
#define BF_FMC_SDTR_TRAS(v) (((v) & 0xf) << 8)
#define BFM_FMC_SDTR_TRAS(v) BM_FMC_SDTR_TRAS
#define BF_FMC_SDTR_TRAS_V(e) BF_FMC_SDTR_TRAS(BV_FMC_SDTR_TRAS__##e)
#define BFM_FMC_SDTR_TRAS_V(v) BM_FMC_SDTR_TRAS
#define BP_FMC_SDTR_TXSR 4
#define BM_FMC_SDTR_TXSR 0xf0
#define BF_FMC_SDTR_TXSR(v) (((v) & 0xf) << 4)
#define BFM_FMC_SDTR_TXSR(v) BM_FMC_SDTR_TXSR
#define BF_FMC_SDTR_TXSR_V(e) BF_FMC_SDTR_TXSR(BV_FMC_SDTR_TXSR__##e)
#define BFM_FMC_SDTR_TXSR_V(v) BM_FMC_SDTR_TXSR
#define BP_FMC_SDTR_TMRD 0
#define BM_FMC_SDTR_TMRD 0xf
#define BF_FMC_SDTR_TMRD(v) (((v) & 0xf) << 0)
#define BFM_FMC_SDTR_TMRD(v) BM_FMC_SDTR_TMRD
#define BF_FMC_SDTR_TMRD_V(e) BF_FMC_SDTR_TMRD(BV_FMC_SDTR_TMRD__##e)
#define BFM_FMC_SDTR_TMRD_V(v) BM_FMC_SDTR_TMRD
#define REG_FMC_SDCMR st_reg(FMC_SDCMR)
#define STA_FMC_SDCMR (0x52004000 + 0x150)
#define STO_FMC_SDCMR (0x150)
#define STT_FMC_SDCMR STIO_32_RW
#define STN_FMC_SDCMR FMC_SDCMR
#define BP_FMC_SDCMR_MRD 9
#define BM_FMC_SDCMR_MRD 0x7ffe00
#define BF_FMC_SDCMR_MRD(v) (((v) & 0x3fff) << 9)
#define BFM_FMC_SDCMR_MRD(v) BM_FMC_SDCMR_MRD
#define BF_FMC_SDCMR_MRD_V(e) BF_FMC_SDCMR_MRD(BV_FMC_SDCMR_MRD__##e)
#define BFM_FMC_SDCMR_MRD_V(v) BM_FMC_SDCMR_MRD
#define BP_FMC_SDCMR_NRFS 5
#define BM_FMC_SDCMR_NRFS 0x1e0
#define BF_FMC_SDCMR_NRFS(v) (((v) & 0xf) << 5)
#define BFM_FMC_SDCMR_NRFS(v) BM_FMC_SDCMR_NRFS
#define BF_FMC_SDCMR_NRFS_V(e) BF_FMC_SDCMR_NRFS(BV_FMC_SDCMR_NRFS__##e)
#define BFM_FMC_SDCMR_NRFS_V(v) BM_FMC_SDCMR_NRFS
#define BP_FMC_SDCMR_MODE 0
#define BM_FMC_SDCMR_MODE 0x7
#define BF_FMC_SDCMR_MODE(v) (((v) & 0x7) << 0)
#define BFM_FMC_SDCMR_MODE(v) BM_FMC_SDCMR_MODE
#define BF_FMC_SDCMR_MODE_V(e) BF_FMC_SDCMR_MODE(BV_FMC_SDCMR_MODE__##e)
#define BFM_FMC_SDCMR_MODE_V(v) BM_FMC_SDCMR_MODE
#define BP_FMC_SDCMR_CTB1 4
#define BM_FMC_SDCMR_CTB1 0x10
#define BF_FMC_SDCMR_CTB1(v) (((v) & 0x1) << 4)
#define BFM_FMC_SDCMR_CTB1(v) BM_FMC_SDCMR_CTB1
#define BF_FMC_SDCMR_CTB1_V(e) BF_FMC_SDCMR_CTB1(BV_FMC_SDCMR_CTB1__##e)
#define BFM_FMC_SDCMR_CTB1_V(v) BM_FMC_SDCMR_CTB1
#define BP_FMC_SDCMR_CTB2 3
#define BM_FMC_SDCMR_CTB2 0x8
#define BF_FMC_SDCMR_CTB2(v) (((v) & 0x1) << 3)
#define BFM_FMC_SDCMR_CTB2(v) BM_FMC_SDCMR_CTB2
#define BF_FMC_SDCMR_CTB2_V(e) BF_FMC_SDCMR_CTB2(BV_FMC_SDCMR_CTB2__##e)
#define BFM_FMC_SDCMR_CTB2_V(v) BM_FMC_SDCMR_CTB2
#define REG_FMC_SDRTR st_reg(FMC_SDRTR)
#define STA_FMC_SDRTR (0x52004000 + 0x154)
#define STO_FMC_SDRTR (0x154)
#define STT_FMC_SDRTR STIO_32_RW
#define STN_FMC_SDRTR FMC_SDRTR
#define BP_FMC_SDRTR_COUNT 1
#define BM_FMC_SDRTR_COUNT 0x3ffe
#define BF_FMC_SDRTR_COUNT(v) (((v) & 0x1fff) << 1)
#define BFM_FMC_SDRTR_COUNT(v) BM_FMC_SDRTR_COUNT
#define BF_FMC_SDRTR_COUNT_V(e) BF_FMC_SDRTR_COUNT(BV_FMC_SDRTR_COUNT__##e)
#define BFM_FMC_SDRTR_COUNT_V(v) BM_FMC_SDRTR_COUNT
#define BP_FMC_SDRTR_REIE 14
#define BM_FMC_SDRTR_REIE 0x4000
#define BF_FMC_SDRTR_REIE(v) (((v) & 0x1) << 14)
#define BFM_FMC_SDRTR_REIE(v) BM_FMC_SDRTR_REIE
#define BF_FMC_SDRTR_REIE_V(e) BF_FMC_SDRTR_REIE(BV_FMC_SDRTR_REIE__##e)
#define BFM_FMC_SDRTR_REIE_V(v) BM_FMC_SDRTR_REIE
#define BP_FMC_SDRTR_CRE 0
#define BM_FMC_SDRTR_CRE 0x1
#define BF_FMC_SDRTR_CRE(v) (((v) & 0x1) << 0)
#define BFM_FMC_SDRTR_CRE(v) BM_FMC_SDRTR_CRE
#define BF_FMC_SDRTR_CRE_V(e) BF_FMC_SDRTR_CRE(BV_FMC_SDRTR_CRE__##e)
#define BFM_FMC_SDRTR_CRE_V(v) BM_FMC_SDRTR_CRE
#define REG_FMC_SDSR st_reg(FMC_SDSR)
#define STA_FMC_SDSR (0x52004000 + 0x158)
#define STO_FMC_SDSR (0x158)
#define STT_FMC_SDSR STIO_32_RW
#define STN_FMC_SDSR FMC_SDSR
#define BP_FMC_SDSR_MODES2 3
#define BM_FMC_SDSR_MODES2 0x18
#define BF_FMC_SDSR_MODES2(v) (((v) & 0x3) << 3)
#define BFM_FMC_SDSR_MODES2(v) BM_FMC_SDSR_MODES2
#define BF_FMC_SDSR_MODES2_V(e) BF_FMC_SDSR_MODES2(BV_FMC_SDSR_MODES2__##e)
#define BFM_FMC_SDSR_MODES2_V(v) BM_FMC_SDSR_MODES2
#define BP_FMC_SDSR_MODES1 1
#define BM_FMC_SDSR_MODES1 0x6
#define BF_FMC_SDSR_MODES1(v) (((v) & 0x3) << 1)
#define BFM_FMC_SDSR_MODES1(v) BM_FMC_SDSR_MODES1
#define BF_FMC_SDSR_MODES1_V(e) BF_FMC_SDSR_MODES1(BV_FMC_SDSR_MODES1__##e)
#define BFM_FMC_SDSR_MODES1_V(v) BM_FMC_SDSR_MODES1
#define BP_FMC_SDSR_RE 0
#define BM_FMC_SDSR_RE 0x1
#define BF_FMC_SDSR_RE(v) (((v) & 0x1) << 0)
#define BFM_FMC_SDSR_RE(v) BM_FMC_SDSR_RE
#define BF_FMC_SDSR_RE_V(e) BF_FMC_SDSR_RE(BV_FMC_SDSR_RE__##e)
#define BFM_FMC_SDSR_RE_V(v) BM_FMC_SDSR_RE
#endif /* __HEADERGEN_FMC_H__*/

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firmware/target/arm/stm32/stm32h7/gpio.h Normal file
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stm32h743 version: 1.0
* stm32h743 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_GPIO_H__
#define __HEADERGEN_GPIO_H__
#include "macro.h"
#define STA_GPIO(_n1) (0x58020000 + (_n1) * 0x400)
#define REG_GPIO_MODER(_n1) st_reg(GPIO_MODER(_n1))
#define STA_GPIO_MODER(_n1) (0x58020000 + (_n1) * 0x400 + 0x0)
#define STO_GPIO_MODER (0x0)
#define STT_GPIO_MODER(_n1) STIO_32_RW
#define STN_GPIO_MODER(_n1) GPIO_MODER
#define REG_GPIO_OTYPER(_n1) st_reg(GPIO_OTYPER(_n1))
#define STA_GPIO_OTYPER(_n1) (0x58020000 + (_n1) * 0x400 + 0x4)
#define STO_GPIO_OTYPER (0x4)
#define STT_GPIO_OTYPER(_n1) STIO_32_RW
#define STN_GPIO_OTYPER(_n1) GPIO_OTYPER
#define REG_GPIO_OSPEEDR(_n1) st_reg(GPIO_OSPEEDR(_n1))
#define STA_GPIO_OSPEEDR(_n1) (0x58020000 + (_n1) * 0x400 + 0x8)
#define STO_GPIO_OSPEEDR (0x8)
#define STT_GPIO_OSPEEDR(_n1) STIO_32_RW
#define STN_GPIO_OSPEEDR(_n1) GPIO_OSPEEDR
#define REG_GPIO_PUPDR(_n1) st_reg(GPIO_PUPDR(_n1))
#define STA_GPIO_PUPDR(_n1) (0x58020000 + (_n1) * 0x400 + 0xc)
#define STO_GPIO_PUPDR (0xc)
#define STT_GPIO_PUPDR(_n1) STIO_32_RW
#define STN_GPIO_PUPDR(_n1) GPIO_PUPDR
#define REG_GPIO_IDR(_n1) st_reg(GPIO_IDR(_n1))
#define STA_GPIO_IDR(_n1) (0x58020000 + (_n1) * 0x400 + 0x10)
#define STO_GPIO_IDR (0x10)
#define STT_GPIO_IDR(_n1) STIO_32_RW
#define STN_GPIO_IDR(_n1) GPIO_IDR
#define REG_GPIO_ODR(_n1) st_reg(GPIO_ODR(_n1))
#define STA_GPIO_ODR(_n1) (0x58020000 + (_n1) * 0x400 + 0x14)
#define STO_GPIO_ODR (0x14)
#define STT_GPIO_ODR(_n1) STIO_32_RW
#define STN_GPIO_ODR(_n1) GPIO_ODR
#define REG_GPIO_BSRR(_n1) st_reg(GPIO_BSRR(_n1))
#define STA_GPIO_BSRR(_n1) (0x58020000 + (_n1) * 0x400 + 0x18)
#define STO_GPIO_BSRR (0x18)
#define STT_GPIO_BSRR(_n1) STIO_32_RW
#define STN_GPIO_BSRR(_n1) GPIO_BSRR
#define REG_GPIO_LCKR(_n1) st_reg(GPIO_LCKR(_n1))
#define STA_GPIO_LCKR(_n1) (0x58020000 + (_n1) * 0x400 + 0x1c)
#define STO_GPIO_LCKR (0x1c)
#define STT_GPIO_LCKR(_n1) STIO_32_RW
#define STN_GPIO_LCKR(_n1) GPIO_LCKR
#define REG_GPIO_AFRL(_n1) st_reg(GPIO_AFRL(_n1))
#define STA_GPIO_AFRL(_n1) (0x58020000 + (_n1) * 0x400 + 0x20)
#define STO_GPIO_AFRL (0x20)
#define STT_GPIO_AFRL(_n1) STIO_32_RW
#define STN_GPIO_AFRL(_n1) GPIO_AFRL
#define REG_GPIO_AFRH(_n1) st_reg(GPIO_AFRH(_n1))
#define STA_GPIO_AFRH(_n1) (0x58020000 + (_n1) * 0x400 + 0x24)
#define STO_GPIO_AFRH (0x24)
#define STT_GPIO_AFRH(_n1) STIO_32_RW
#define STN_GPIO_AFRH(_n1) GPIO_AFRH
#endif /* __HEADERGEN_GPIO_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_MACRO_H__
#define __HEADERGEN_MACRO_H__
#include <stdint.h>
#define __VAR_OR1(prefix, suffix) \
(prefix##suffix)
#define __VAR_OR2(pre, s1, s2) \
(__VAR_OR1(pre, s1) | __VAR_OR1(pre, s2))
#define __VAR_OR3(pre, s1, s2, s3) \
(__VAR_OR1(pre, s1) | __VAR_OR2(pre, s2, s3))
#define __VAR_OR4(pre, s1, s2, s3, s4) \
(__VAR_OR2(pre, s1, s2) | __VAR_OR2(pre, s3, s4))
#define __VAR_OR5(pre, s1, s2, s3, s4, s5) \
(__VAR_OR2(pre, s1, s2) | __VAR_OR3(pre, s3, s4, s5))
#define __VAR_OR6(pre, s1, s2, s3, s4, s5, s6) \
(__VAR_OR3(pre, s1, s2, s3) | __VAR_OR3(pre, s4, s5, s6))
#define __VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) \
(__VAR_OR3(pre, s1, s2, s3) | __VAR_OR4(pre, s4, s5, s6, s7))
#define __VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) \
(__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR4(pre, s5, s6, s7, s8))
#define __VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) \
(__VAR_OR4(pre, s1, s2, s3, s4) | __VAR_OR5(pre, s5, s6, s7, s8, s9))
#define __VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) \
(__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR5(pre, s6, s7, s8, s9, s10))
#define __VAR_OR11(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11) \
(__VAR_OR5(pre, s1, s2, s3, s4, s5) | __VAR_OR6(pre, s6, s7, s8, s9, s10, s11))
#define __VAR_OR12(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12) \
(__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR6(pre, s7, s8, s9, s10, s11, s12))
#define __VAR_OR13(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13) \
(__VAR_OR6(pre, s1, s2, s3, s4, s5, s6) | __VAR_OR7(pre, s7, s8, s9, s10, s11, s12, s13))
#define __VAR_OR14(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14) \
(__VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) | __VAR_OR7(pre, s8, s9, s10, s11, s12, s13, s14))
#define __VAR_OR15(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15) \
(__VAR_OR7(pre, s1, s2, s3, s4, s5, s6, s7) | __VAR_OR8(pre, s8, s9, s10, s11, s12, s13, s14, s15))
#define __VAR_OR16(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16) \
(__VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) | __VAR_OR8(pre, s9, s10, s11, s12, s13, s14, s15, s16))
#define __VAR_OR17(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17) \
(__VAR_OR8(pre, s1, s2, s3, s4, s5, s6, s7, s8) | __VAR_OR9(pre, s9, s10, s11, s12, s13, s14, s15, s16, s17))
#define __VAR_OR18(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18) \
(__VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) | __VAR_OR9(pre, s10, s11, s12, s13, s14, s15, s16, s17, s18))
#define __VAR_OR19(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19) \
(__VAR_OR9(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9) | __VAR_OR10(pre, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19))
#define __VAR_OR20(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20) \
(__VAR_OR10(pre, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10) | __VAR_OR10(pre, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20))
#define __VAR_NARGS(...) __VAR_NARGS_(__VA_ARGS__, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)
#define __VAR_NARGS_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, N, ...) N
#define __VAR_EXPAND(macro, prefix, ...) __VAR_EXPAND_(macro, __VAR_NARGS(__VA_ARGS__), prefix, __VA_ARGS__)
#define __VAR_EXPAND_(macro, cnt, prefix, ...) __VAR_EXPAND__(macro, cnt, prefix, __VA_ARGS__)
#define __VAR_EXPAND__(macro, cnt, prefix, ...) __VAR_EXPAND___(macro##cnt, prefix, __VA_ARGS__)
#define __VAR_EXPAND___(macro, prefix, ...) macro(prefix, __VA_ARGS__)
#define STIO_8_RO(op, name, ...) STIO_8_RO_##op(name, __VA_ARGS__)
#define STIO_8_RO_RD(name, ...) (*(const volatile uint8_t *)(STA_##name))
#define STIO_8_RO_WR(name, val) _Static_assert(0, #name " is read-only")
#define STIO_8_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
#define STIO_8_RO_VAR(name, ...) (*(const volatile uint8_t *)(STA_##name))
#define STIO_8_RO_RDREL(name, base, ...) (*(const volatile uint8_t *)((base) + STO_##name))
#define STIO_8_RO_WRREL(name, base, val) _Static_assert(0, #name " is read-only")
#define STIO_8_RO_RMWREL(name, base, vand, vor) _Static_assert(0, #name " is read-only")
#define STIO_8_RO_VARREL(name, base, ...) (*(const volatile uint8_t *)((base) + STO_##name))
#define STIO_16_RO(op, name, ...) STIO_16_RO_##op(name, __VA_ARGS__)
#define STIO_16_RO_RD(name, ...) (*(const volatile uint16_t *)(STA_##name))
#define STIO_16_RO_WR(name, val) _Static_assert(0, #name " is read-only")
#define STIO_16_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
#define STIO_16_RO_VAR(name, ...) (*(const volatile uint16_t *)(STA_##name))
#define STIO_16_RO_RDREL(name, base, ...) (*(const volatile uint16_t *)((base) + STO_##name))
#define STIO_16_RO_WRREL(name, base, val) _Static_assert(0, #name " is read-only")
#define STIO_16_RO_RMWREL(name, base, vand, vor) _Static_assert(0, #name " is read-only")
#define STIO_16_RO_VARREL(name, base, ...) (*(const volatile uint16_t *)((base) + STO_##name))
#define STIO_32_RO(op, name, ...) STIO_32_RO_##op(name, __VA_ARGS__)
#define STIO_32_RO_RD(name, ...) (*(const volatile uint32_t *)(STA_##name))
#define STIO_32_RO_WR(name, val) _Static_assert(0, #name " is read-only")
#define STIO_32_RO_RMW(name, vand, vor) _Static_assert(0, #name " is read-only")
#define STIO_32_RO_VAR(name, ...) (*(const volatile uint32_t *)(STA_##name))
#define STIO_32_RO_RDREL(name, base, ...) (*(const volatile uint32_t *)((base) + STO_##name))
#define STIO_32_RO_WRREL(name, base, val) _Static_assert(0, #name " is read-only")
#define STIO_32_RO_RMWREL(name, base, vand, vor) _Static_assert(0, #name " is read-only")
#define STIO_32_RO_VARREL(name, base, ...) (*(const volatile uint32_t *)((base) + STO_##name))
#define STIO_8_RW(op, name, ...) STIO_8_RW_##op(name, __VA_ARGS__)
#define STIO_8_RW_RD(name, ...) (*(volatile uint8_t *)(STA_##name))
#define STIO_8_RW_WR(name, val) (*(volatile uint8_t *)(STA_##name)) = (val)
#define STIO_8_RW_RMW(name, vand, vor) STIO_8_RW_WR(name, (STIO_8_RW_RD(name) & (vand)) | (vor))
#define STIO_8_RW_VAR(name, ...) (*(volatile uint8_t *)(STA_##name))
#define STIO_8_RW_RDREL(name, base, ...) (*(volatile uint8_t *)((base) + STO_##name))
#define STIO_8_RW_WRREL(name, base, val) (*(volatile uint8_t *)((base) + STO_##name)) = (val)
#define STIO_8_RW_RMWREL(name, base, vand, vor) STIO_8_RW_WRREL(name, base, (STIO_8_RW_RDREL(name, base) & (vand)) | (vor))
#define STIO_8_RW_VARREL(name, base, ...) (*(volatile uint8_t *)((base) + STO_##name))
#define STIO_16_RW(op, name, ...) STIO_16_RW_##op(name, __VA_ARGS__)
#define STIO_16_RW_RD(name, ...) (*(volatile uint16_t *)(STA_##name))
#define STIO_16_RW_WR(name, val) (*(volatile uint16_t *)(STA_##name)) = (val)
#define STIO_16_RW_RMW(name, vand, vor) STIO_16_RW_WR(name, (STIO_16_RW_RD(name) & (vand)) | (vor))
#define STIO_16_RW_VAR(name, ...) (*(volatile uint16_t *)(STA_##name))
#define STIO_16_RW_RDREL(name, base, ...) (*(volatile uint16_t *)((base) + STO_##name))
#define STIO_16_RW_WRREL(name, base, val) (*(volatile uint16_t *)((base) + STO_##name)) = (val)
#define STIO_16_RW_RMWREL(name, base, vand, vor) STIO_16_RW_WRREL(name, base, (STIO_16_RW_RDREL(name, base) & (vand)) | (vor))
#define STIO_16_RW_VARREL(name, base, ...) (*(volatile uint16_t *)((base) + STO_##name))
#define STIO_32_RW(op, name, ...) STIO_32_RW_##op(name, __VA_ARGS__)
#define STIO_32_RW_RD(name, ...) (*(volatile uint32_t *)(STA_##name))
#define STIO_32_RW_WR(name, val) (*(volatile uint32_t *)(STA_##name)) = (val)
#define STIO_32_RW_RMW(name, vand, vor) STIO_32_RW_WR(name, (STIO_32_RW_RD(name) & (vand)) | (vor))
#define STIO_32_RW_VAR(name, ...) (*(volatile uint32_t *)(STA_##name))
#define STIO_32_RW_RDREL(name, base, ...) (*(volatile uint32_t *)((base) + STO_##name))
#define STIO_32_RW_WRREL(name, base, val) (*(volatile uint32_t *)((base) + STO_##name)) = (val)
#define STIO_32_RW_RMWREL(name, base, vand, vor) STIO_32_RW_WRREL(name, base, (STIO_32_RW_RDREL(name, base) & (vand)) | (vor))
#define STIO_32_RW_VARREL(name, base, ...) (*(volatile uint32_t *)((base) + STO_##name))
#define STIO_8_WO(op, name, ...) STIO_8_WO_##op(name, __VA_ARGS__)
#define STIO_8_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
#define STIO_8_WO_WR(name, val) (*(volatile uint8_t *)(STA_##name)) = (val)
#define STIO_8_WO_RMW(name, vand, vor) STIO_8_WO_WR(name, vor)
#define STIO_8_WO_VAR(name, ...) (*(volatile uint8_t *)(STA_##name))
#define STIO_8_WO_RDREL(name, base, ...) ({_Static_assert(0, #name " is write-only"); 0;})
#define STIO_8_WO_WRREL(name, base, val) (*(volatile uint8_t *)((base) + STO_##name)) = (val)
#define STIO_8_WO_RMWREL(name, base, vand, vor) STIO_8_WO_WRREL(name, base, vor)
#define STIO_8_WO_VARREL(name, base, ...) (*(volatile uint8_t *)((base) + STO_##name))
#define STIO_16_WO(op, name, ...) STIO_16_WO_##op(name, __VA_ARGS__)
#define STIO_16_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
#define STIO_16_WO_WR(name, val) (*(volatile uint16_t *)(STA_##name)) = (val)
#define STIO_16_WO_RMW(name, vand, vor) STIO_16_WO_WR(name, vor)
#define STIO_16_WO_VAR(name, ...) (*(volatile uint16_t *)(STA_##name))
#define STIO_16_WO_RDREL(name, base, ...) ({_Static_assert(0, #name " is write-only"); 0;})
#define STIO_16_WO_WRREL(name, base, val) (*(volatile uint16_t *)((base) + STO_##name)) = (val)
#define STIO_16_WO_RMWREL(name, base, vand, vor) STIO_16_WO_WRREL(name, base, vor)
#define STIO_16_WO_VARREL(name, base, ...) (*(volatile uint16_t *)((base) + STO_##name))
#define STIO_32_WO(op, name, ...) STIO_32_WO_##op(name, __VA_ARGS__)
#define STIO_32_WO_RD(name, ...) ({_Static_assert(0, #name " is write-only"); 0;})
#define STIO_32_WO_WR(name, val) (*(volatile uint32_t *)(STA_##name)) = (val)
#define STIO_32_WO_RMW(name, vand, vor) STIO_32_WO_WR(name, vor)
#define STIO_32_WO_VAR(name, ...) (*(volatile uint32_t *)(STA_##name))
#define STIO_32_WO_RDREL(name, base, ...) ({_Static_assert(0, #name " is write-only"); 0;})
#define STIO_32_WO_WRREL(name, base, val) (*(volatile uint32_t *)((base) + STO_##name)) = (val)
#define STIO_32_WO_RMWREL(name, base, vand, vor) STIO_32_WO_WRREL(name, base, vor)
#define STIO_32_WO_VARREL(name, base, ...) (*(volatile uint32_t *)((base) + STO_##name))
/** st_orf
*
* usage: st_orf(register, f1(v1), f2(v2), ...)
*
* effect: expands to the register value where each field fi has value vi.
* Informally: reg_f1(v1) | reg_f2(v2) | ...
* note: enumerated values for fields can be obtained by using the syntax:
* f1_V(name)
*
* example: st_orf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
*/
#define st_orf(reg, ...) __VAR_EXPAND(__VAR_OR, BF_##reg##_, __VA_ARGS__)
/** __st_orfm
*
* usage: __st_orfm(register, f1(v1), f2(v2), ...)
*
* effect: expands to the register value where each field fi has maximum value (vi is ignored).
* note: internal usage
*
* example: __st_orfm(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
*/
#define __st_orfm(reg, ...) __VAR_EXPAND(__VAR_OR, BFM_##reg##_, __VA_ARGS__)
/** st_orm
*
* usage: st_orm(register, f1, f2, ...)
*
* effect: expands to the register value where each field fi is set to its maximum value.
* Informally: reg_f1_mask | reg_f2_mask | ...
*
* example: st_orm(ICOLL_CTRL, SFTRST, CLKGATE)
*/
#define st_orm(reg, ...) __VAR_EXPAND(__VAR_OR, BM_##reg##_, __VA_ARGS__)
/** st_vreadf
*
* usage: st_vreadf(value, register, field)
*
* effect: given a register value, return the value of a particular field
* note: this macro does NOT read any register
*
* example: st_vreadf(0xc0000000, ICOLL_CTRL, SFTRST)
* st_vreadf(0x46ff, ICOLL_ENABLE, CPU0_PRIO)
*/
#define st_vreadf(val, name, field) (((val) & BM_##name##_##field) >> BP_##name##_##field)
/** st_vwritef
*
* usage: st_vwritef(var, register, f1(v1), f2(v2), ...)
*
* effect: change the variable value so that field fi has value vi
* note: this macro will perform a read-modify-write
*
* example: st_vwritef(var, ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
* st_vwritef(var, ICOLL_ENABLE, CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
*/
#define st_vwritef(var, name, ...) (var) = st_orf(name, __VA_ARGS__) | (~__st_orfm(name, __VA_ARGS__) & (var))
/** st_read
*
* usage: st_read(register)
*
* effect: read the register and return its value
* note: register must be fully qualified if indexed
*
* example: st_read(ICOLL_STATUS)
* st_read(ICOLL_ENABLE(42))
*/
#define st_read(name) STT_##name(RD, name)
/** st_readf
*
* usage: st_readf(register, field)
*
* effect: read a register and return the value of a particular field
* note: register must be fully qualified if indexed
*
* example: st_readf(ICOLL_CTRL, SFTRST)
* st_readf(ICOLL_ENABLE(3), CPU0_PRIO)
*/
#define st_readf(name, field) st_readf_(st_read(name), STN_##name, field)
#define st_readf_(...) st_vreadf(__VA_ARGS__)
/** st_write
*
* usage: st_write(register, value)
*
* effect: write a register
* note: register must be fully qualified if indexed
*
* example: st_write(ICOLL_CTRL, 0x42)
* st_write(ICOLL_ENABLE_SET(3), 0x37)
*/
#define st_write(name, val) STT_##name(WR, name, val)
/** st_writef
*
* usage: st_writef(register, f1(v1), f2(v2), ...)
*
* effect: change the register value so that field fi has value vi
* note: register must be fully qualified if indexed
* note: this macro may perform a read-modify-write
*
* example: st_writef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
* st_writef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
*/
#define st_writef(name, ...) st_writef_(name, STN_##name, __VA_ARGS__)
#define st_writef_(name, name2, ...) STT_##name(RMW, name, ~__st_orfm(name2, __VA_ARGS__), st_orf(name2, __VA_ARGS__))
/** st_overwritef
*
* usage: st_overwritef(register, f1(v1), f2(v2), ...)
*
* effect: change the register value so that field fi has value vi and other fields have value zero
* thus this macro is equivalent to:
* st_write(register, st_orf(register, f1(v1), ...))
* note: register must be fully qualified if indexed
* note: this macro will overwrite the register (it is NOT a read-modify-write)
*
* example: st_overwritef(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
* st_overwritef(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
*/
#define st_overwritef(name, ...) st_overwritef_(name, STN_##name, __VA_ARGS__)
#define st_overwritef_(name, name2, ...) STT_##name(WR, name, st_orf(name2, __VA_ARGS__))
/** st_setf
*
* usage: st_setf(register, f1, f2, ...)
*
* effect: change the register value so that field fi has maximum value
* note: this macro will perform a read-modify-write
* note: register must be fully qualified if indexed
*
* example: st_setf(ICOLL_CTRL, SFTRST, CLKGATE)
* st_setf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
*/
#define st_setf(name, ...) st_setf_(name, STN_##name, __VA_ARGS__)
#define st_setf_(name, name2, ...) STT_##name(RMW, name, ~0,st_orm(name2, __VA_ARGS__))
/** st_clrf
*
* usage: st_clrf(register, f1, f2, ...)
*
* effect: change the register value so that field fi has value zero
* note: this macro will perform a read-modify-write
* note: register must be fully qualified if indexed
*
* example: st_clrf(ICOLL_CTRL, SFTRST, CLKGATE)
* st_clrf(ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
*/
#define st_clrf(name, ...) st_clrf_(name, STN_##name, __VA_ARGS__)
#define st_clrf_(name, name2, ...) STT_##name(RMW, name, ~st_orm(name2, __VA_ARGS__), 0)
/** st_reg
*
* usage: st_reg(register)
*
* effect: return a variable-like expression that can be read/written
* note: register must be fully qualified if indexed
* note: read-only registers will yield a constant expression
*
* example: unsigned x = st_reg(ICOLL_STATUS)
* unsigned x = st_reg(ICOLL_ENABLE(42))
* st_reg(ICOLL_ENABLE(42)) = 64
*/
#define st_reg(name) STT_##name(VAR, name)
/** st_readl
*
* usage: st_readl(base, register)
*
* effect: read the register and return its value
* register address is calculated by offsetting from the base address
* note: register must be fully qualified if indexed
*
* example: st_readl(base, ICOLL_STATUS)
* st_readl(base, ICOLL_ENABLE(42))
*/
#define st_readl(base, name) STT_##name(RDREL, name, base)
/** st_readlf
*
* usage: st_readlf(base, register, field)
*
* effect: read a register and return the value of a particular field
* register address is calculated by offsetting from the base address
* note: register must be fully qualified if indexed
*
* example: st_readlf(base, ICOLL_CTRL, SFTRST)
* st_readlf(base, ICOLL_ENABLE(3), CPU0_PRIO)
*/
#define st_readlf(base, name, field) st_readlf_(st_readl(base, name), STN_##name, field)
#define st_readlf_(...) st_vreadf(__VA_ARGS__)
/** st_writel
*
* usage: st_writel(base, register, value)
*
* effect: write a register
* register address is calculated by offsetting from the base address
* note: register must be fully qualified if indexed
*
* example: st_writel(base, ICOLL_CTRL, 0x42)
* st_writel(base, ICOLL_ENABLE_SET(3), 0x37)
*/
#define st_writel(base, name, val) STT_##name(WRREL, name, base, val)
/** st_writelf
*
* usage: st_writelf(base, register, f1(v1), f2(v2), ...)
*
* effect: change the register value so that field fi has value vi
* register address is calculated by offsetting from the base address
* note: register must be fully qualified if indexed
* note: this macro may perform a read-modify-write
*
* example: st_writelf(base, ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
* st_writelf(base, ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
*/
#define st_writelf(base, name, ...) st_writelf_(base, name, STN_##name, __VA_ARGS__)
#define st_writelf_(base, name, name2, ...) STT_##name(RMWREL, name, base, ~__st_orfm(name2, __VA_ARGS__), st_orf(name2, __VA_ARGS__))
/** st_overwritelf
*
* usage: st_overwritelf(base, register, f1(v1), f2(v2), ...)
*
* effect: change the register value so that field fi has value vi and other fields have value zero
* register address is calculated by offsetting from the base address
* thus this macro is equivalent to:
* st_writel(base, register, st_orf(register, f1(v1), ...))
* note: register must be fully qualified if indexed
* note: this macro will overwrite the register (it is NOT a read-modify-write)
*
* example: st_overwritelf(ICOLL_CTRL, SFTRST(1), CLKGATE(0), TZ_LOCK_V(UNLOCKED))
* st_overwritelf(ICOLL_ENABLE(3), CPU0_PRIO(1), CPU0_TYPE_V(FIQ))
*/
#define st_overwritelf(base, name, ...) st_overwritelf_(base, name, STN_##name, __VA_ARGS__)
#define st_overwritelf_(base, name, name2, ...) STT_##name(WRREL, name, base, st_orf(name2, __VA_ARGS__))
/** st_setlf
*
* usage: st_setlf(base, register, f1, f2, ...)
*
* effect: change the register value so that field fi has maximum value
* register address is calculated by offsetting from the base address
* note: this macro will perform a read-modify-write
* note: register must be fully qualified if indexed
*
* example: st_setlf(base, ICOLL_CTRL, SFTRST, CLKGATE)
* st_setlf(base, ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
*/
#define st_setlf(base, name, ...) st_setlf_(base, name, STN_##name, __VA_ARGS__)
#define st_setlf_(base, name, name2, ...) STT_##name(RMWREL, name, base, ~0,st_orm(name2, __VA_ARGS__))
/** st_clrlf
*
* usage: st_clrlf(base, register, f1, f2, ...)
*
* effect: change the register value so that field fi has value zero
* register address is calculated by offsetting from the base address
* note: this macro will perform a read-modify-write
* note: register must be fully qualified if indexed
*
* example: st_clrlf(base, ICOLL_CTRL, SFTRST, CLKGATE)
* st_clrlf(base, ICOLL_ENABLE(3), CPU0_PRIO, CPU0_TYPE)
*/
#define st_clrlf(base, name, ...) st_clrlf_(base, name, STN_##name, __VA_ARGS__)
#define st_clrlf_(base, name, name2, ...) STT_##name(RMWREL, name, base, ~st_orm(name2, __VA_ARGS__), 0)
/** st_regl
*
* usage: st_regl(base, register)
*
* effect: return a variable-like expression that can be read/written
* register address is calculated by offsetting from the base address
* note: register must be fully qualified if indexed
* note: read-only registers will yield a constant expression
*
* example: unsigned x = st_regl(base, ICOLL_STATUS)
* unsigned x = st_regl(base, ICOLL_ENABLE(42))
* st_regl(base, ICOLL_ENABLE(42)) = 64
*/
#define st_regl(base, name) STT_##name(VARREL, base, name)
#endif /* __HEADERGEN_MACRO_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stm32h743 version: 1.0
* stm32h743 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_PWR_H__
#define __HEADERGEN_PWR_H__
#include "macro.h"
#define STA_PWR (0x58024800)
#define REG_PWR_CR1 st_reg(PWR_CR1)
#define STA_PWR_CR1 (0x58024800 + 0x0)
#define STO_PWR_CR1 (0x0)
#define STT_PWR_CR1 STIO_32_RW
#define STN_PWR_CR1 PWR_CR1
#define BP_PWR_CR1_ALS 17
#define BM_PWR_CR1_ALS 0x60000
#define BF_PWR_CR1_ALS(v) (((v) & 0x3) << 17)
#define BFM_PWR_CR1_ALS(v) BM_PWR_CR1_ALS
#define BF_PWR_CR1_ALS_V(e) BF_PWR_CR1_ALS(BV_PWR_CR1_ALS__##e)
#define BFM_PWR_CR1_ALS_V(v) BM_PWR_CR1_ALS
#define BP_PWR_CR1_SVOS 14
#define BM_PWR_CR1_SVOS 0xc000
#define BF_PWR_CR1_SVOS(v) (((v) & 0x3) << 14)
#define BFM_PWR_CR1_SVOS(v) BM_PWR_CR1_SVOS
#define BF_PWR_CR1_SVOS_V(e) BF_PWR_CR1_SVOS(BV_PWR_CR1_SVOS__##e)
#define BFM_PWR_CR1_SVOS_V(v) BM_PWR_CR1_SVOS
#define BP_PWR_CR1_PLS 5
#define BM_PWR_CR1_PLS 0xe0
#define BF_PWR_CR1_PLS(v) (((v) & 0x7) << 5)
#define BFM_PWR_CR1_PLS(v) BM_PWR_CR1_PLS
#define BF_PWR_CR1_PLS_V(e) BF_PWR_CR1_PLS(BV_PWR_CR1_PLS__##e)
#define BFM_PWR_CR1_PLS_V(v) BM_PWR_CR1_PLS
#define BP_PWR_CR1_AVDEN 16
#define BM_PWR_CR1_AVDEN 0x10000
#define BF_PWR_CR1_AVDEN(v) (((v) & 0x1) << 16)
#define BFM_PWR_CR1_AVDEN(v) BM_PWR_CR1_AVDEN
#define BF_PWR_CR1_AVDEN_V(e) BF_PWR_CR1_AVDEN(BV_PWR_CR1_AVDEN__##e)
#define BFM_PWR_CR1_AVDEN_V(v) BM_PWR_CR1_AVDEN
#define BP_PWR_CR1_FLPS 9
#define BM_PWR_CR1_FLPS 0x200
#define BF_PWR_CR1_FLPS(v) (((v) & 0x1) << 9)
#define BFM_PWR_CR1_FLPS(v) BM_PWR_CR1_FLPS
#define BF_PWR_CR1_FLPS_V(e) BF_PWR_CR1_FLPS(BV_PWR_CR1_FLPS__##e)
#define BFM_PWR_CR1_FLPS_V(v) BM_PWR_CR1_FLPS
#define BP_PWR_CR1_DBP 8
#define BM_PWR_CR1_DBP 0x100
#define BF_PWR_CR1_DBP(v) (((v) & 0x1) << 8)
#define BFM_PWR_CR1_DBP(v) BM_PWR_CR1_DBP
#define BF_PWR_CR1_DBP_V(e) BF_PWR_CR1_DBP(BV_PWR_CR1_DBP__##e)
#define BFM_PWR_CR1_DBP_V(v) BM_PWR_CR1_DBP
#define BP_PWR_CR1_PVDE 4
#define BM_PWR_CR1_PVDE 0x10
#define BF_PWR_CR1_PVDE(v) (((v) & 0x1) << 4)
#define BFM_PWR_CR1_PVDE(v) BM_PWR_CR1_PVDE
#define BF_PWR_CR1_PVDE_V(e) BF_PWR_CR1_PVDE(BV_PWR_CR1_PVDE__##e)
#define BFM_PWR_CR1_PVDE_V(v) BM_PWR_CR1_PVDE
#define BP_PWR_CR1_LPDS 0
#define BM_PWR_CR1_LPDS 0x1
#define BF_PWR_CR1_LPDS(v) (((v) & 0x1) << 0)
#define BFM_PWR_CR1_LPDS(v) BM_PWR_CR1_LPDS
#define BF_PWR_CR1_LPDS_V(e) BF_PWR_CR1_LPDS(BV_PWR_CR1_LPDS__##e)
#define BFM_PWR_CR1_LPDS_V(v) BM_PWR_CR1_LPDS
#define REG_PWR_CSR1 st_reg(PWR_CSR1)
#define STA_PWR_CSR1 (0x58024800 + 0x4)
#define STO_PWR_CSR1 (0x4)
#define STT_PWR_CSR1 STIO_32_RW
#define STN_PWR_CSR1 PWR_CSR1
#define BP_PWR_CSR1_ACTVOS 14
#define BM_PWR_CSR1_ACTVOS 0xc000
#define BF_PWR_CSR1_ACTVOS(v) (((v) & 0x3) << 14)
#define BFM_PWR_CSR1_ACTVOS(v) BM_PWR_CSR1_ACTVOS
#define BF_PWR_CSR1_ACTVOS_V(e) BF_PWR_CSR1_ACTVOS(BV_PWR_CSR1_ACTVOS__##e)
#define BFM_PWR_CSR1_ACTVOS_V(v) BM_PWR_CSR1_ACTVOS
#define BP_PWR_CSR1_AVDO 16
#define BM_PWR_CSR1_AVDO 0x10000
#define BF_PWR_CSR1_AVDO(v) (((v) & 0x1) << 16)
#define BFM_PWR_CSR1_AVDO(v) BM_PWR_CSR1_AVDO
#define BF_PWR_CSR1_AVDO_V(e) BF_PWR_CSR1_AVDO(BV_PWR_CSR1_AVDO__##e)
#define BFM_PWR_CSR1_AVDO_V(v) BM_PWR_CSR1_AVDO
#define BP_PWR_CSR1_ACTVOSRDY 13
#define BM_PWR_CSR1_ACTVOSRDY 0x2000
#define BF_PWR_CSR1_ACTVOSRDY(v) (((v) & 0x1) << 13)
#define BFM_PWR_CSR1_ACTVOSRDY(v) BM_PWR_CSR1_ACTVOSRDY
#define BF_PWR_CSR1_ACTVOSRDY_V(e) BF_PWR_CSR1_ACTVOSRDY(BV_PWR_CSR1_ACTVOSRDY__##e)
#define BFM_PWR_CSR1_ACTVOSRDY_V(v) BM_PWR_CSR1_ACTVOSRDY
#define BP_PWR_CSR1_PVDO 4
#define BM_PWR_CSR1_PVDO 0x10
#define BF_PWR_CSR1_PVDO(v) (((v) & 0x1) << 4)
#define BFM_PWR_CSR1_PVDO(v) BM_PWR_CSR1_PVDO
#define BF_PWR_CSR1_PVDO_V(e) BF_PWR_CSR1_PVDO(BV_PWR_CSR1_PVDO__##e)
#define BFM_PWR_CSR1_PVDO_V(v) BM_PWR_CSR1_PVDO
#define REG_PWR_CR3 st_reg(PWR_CR3)
#define STA_PWR_CR3 (0x58024800 + 0xc)
#define STO_PWR_CR3 (0xc)
#define STT_PWR_CR3 STIO_32_RW
#define STN_PWR_CR3 PWR_CR3
#define BP_PWR_CR3_USB33RDY 26
#define BM_PWR_CR3_USB33RDY 0x4000000
#define BF_PWR_CR3_USB33RDY(v) (((v) & 0x1) << 26)
#define BFM_PWR_CR3_USB33RDY(v) BM_PWR_CR3_USB33RDY
#define BF_PWR_CR3_USB33RDY_V(e) BF_PWR_CR3_USB33RDY(BV_PWR_CR3_USB33RDY__##e)
#define BFM_PWR_CR3_USB33RDY_V(v) BM_PWR_CR3_USB33RDY
#define BP_PWR_CR3_USBREGEN 25
#define BM_PWR_CR3_USBREGEN 0x2000000
#define BF_PWR_CR3_USBREGEN(v) (((v) & 0x1) << 25)
#define BFM_PWR_CR3_USBREGEN(v) BM_PWR_CR3_USBREGEN
#define BF_PWR_CR3_USBREGEN_V(e) BF_PWR_CR3_USBREGEN(BV_PWR_CR3_USBREGEN__##e)
#define BFM_PWR_CR3_USBREGEN_V(v) BM_PWR_CR3_USBREGEN
#define BP_PWR_CR3_USB33DEN 24
#define BM_PWR_CR3_USB33DEN 0x1000000
#define BF_PWR_CR3_USB33DEN(v) (((v) & 0x1) << 24)
#define BFM_PWR_CR3_USB33DEN(v) BM_PWR_CR3_USB33DEN
#define BF_PWR_CR3_USB33DEN_V(e) BF_PWR_CR3_USB33DEN(BV_PWR_CR3_USB33DEN__##e)
#define BFM_PWR_CR3_USB33DEN_V(v) BM_PWR_CR3_USB33DEN
#define BP_PWR_CR3_VBRS 9
#define BM_PWR_CR3_VBRS 0x200
#define BF_PWR_CR3_VBRS(v) (((v) & 0x1) << 9)
#define BFM_PWR_CR3_VBRS(v) BM_PWR_CR3_VBRS
#define BF_PWR_CR3_VBRS_V(e) BF_PWR_CR3_VBRS(BV_PWR_CR3_VBRS__##e)
#define BFM_PWR_CR3_VBRS_V(v) BM_PWR_CR3_VBRS
#define BP_PWR_CR3_VBE 8
#define BM_PWR_CR3_VBE 0x100
#define BF_PWR_CR3_VBE(v) (((v) & 0x1) << 8)
#define BFM_PWR_CR3_VBE(v) BM_PWR_CR3_VBE
#define BF_PWR_CR3_VBE_V(e) BF_PWR_CR3_VBE(BV_PWR_CR3_VBE__##e)
#define BFM_PWR_CR3_VBE_V(v) BM_PWR_CR3_VBE
#define BP_PWR_CR3_SCUEN 2
#define BM_PWR_CR3_SCUEN 0x4
#define BF_PWR_CR3_SCUEN(v) (((v) & 0x1) << 2)
#define BFM_PWR_CR3_SCUEN(v) BM_PWR_CR3_SCUEN
#define BF_PWR_CR3_SCUEN_V(e) BF_PWR_CR3_SCUEN(BV_PWR_CR3_SCUEN__##e)
#define BFM_PWR_CR3_SCUEN_V(v) BM_PWR_CR3_SCUEN
#define BP_PWR_CR3_LDOEN 1
#define BM_PWR_CR3_LDOEN 0x2
#define BF_PWR_CR3_LDOEN(v) (((v) & 0x1) << 1)
#define BFM_PWR_CR3_LDOEN(v) BM_PWR_CR3_LDOEN
#define BF_PWR_CR3_LDOEN_V(e) BF_PWR_CR3_LDOEN(BV_PWR_CR3_LDOEN__##e)
#define BFM_PWR_CR3_LDOEN_V(v) BM_PWR_CR3_LDOEN
#define BP_PWR_CR3_BYPASS 0
#define BM_PWR_CR3_BYPASS 0x1
#define BF_PWR_CR3_BYPASS(v) (((v) & 0x1) << 0)
#define BFM_PWR_CR3_BYPASS(v) BM_PWR_CR3_BYPASS
#define BF_PWR_CR3_BYPASS_V(e) BF_PWR_CR3_BYPASS(BV_PWR_CR3_BYPASS__##e)
#define BFM_PWR_CR3_BYPASS_V(v) BM_PWR_CR3_BYPASS
#define REG_PWR_D3CR st_reg(PWR_D3CR)
#define STA_PWR_D3CR (0x58024800 + 0x18)
#define STO_PWR_D3CR (0x18)
#define STT_PWR_D3CR STIO_32_RW
#define STN_PWR_D3CR PWR_D3CR
#define BP_PWR_D3CR_VOS 14
#define BM_PWR_D3CR_VOS 0xc000
#define BV_PWR_D3CR_VOS__VOS3 0x1
#define BV_PWR_D3CR_VOS__VOS2 0x2
#define BV_PWR_D3CR_VOS__VOS1 0x3
#define BF_PWR_D3CR_VOS(v) (((v) & 0x3) << 14)
#define BFM_PWR_D3CR_VOS(v) BM_PWR_D3CR_VOS
#define BF_PWR_D3CR_VOS_V(e) BF_PWR_D3CR_VOS(BV_PWR_D3CR_VOS__##e)
#define BFM_PWR_D3CR_VOS_V(v) BM_PWR_D3CR_VOS
#define BP_PWR_D3CR_VOSRDY 13
#define BM_PWR_D3CR_VOSRDY 0x2000
#define BF_PWR_D3CR_VOSRDY(v) (((v) & 0x1) << 13)
#define BFM_PWR_D3CR_VOSRDY(v) BM_PWR_D3CR_VOSRDY
#define BF_PWR_D3CR_VOSRDY_V(e) BF_PWR_D3CR_VOSRDY(BV_PWR_D3CR_VOSRDY__##e)
#define BFM_PWR_D3CR_VOSRDY_V(v) BM_PWR_D3CR_VOSRDY
#endif /* __HEADERGEN_PWR_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stm32h743 version: 1.0
* stm32h743 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_RTC_H__
#define __HEADERGEN_RTC_H__
#include "macro.h"
#define STA_RTC (0x58004000)
#define REG_RTC_TR st_reg(RTC_TR)
#define STA_RTC_TR (0x58004000 + 0x0)
#define STO_RTC_TR (0x0)
#define STT_RTC_TR STIO_32_RW
#define STN_RTC_TR RTC_TR
#define BP_RTC_TR_HT 20
#define BM_RTC_TR_HT 0x300000
#define BF_RTC_TR_HT(v) (((v) & 0x3) << 20)
#define BFM_RTC_TR_HT(v) BM_RTC_TR_HT
#define BF_RTC_TR_HT_V(e) BF_RTC_TR_HT(BV_RTC_TR_HT__##e)
#define BFM_RTC_TR_HT_V(v) BM_RTC_TR_HT
#define BP_RTC_TR_HU 16
#define BM_RTC_TR_HU 0xf0000
#define BF_RTC_TR_HU(v) (((v) & 0xf) << 16)
#define BFM_RTC_TR_HU(v) BM_RTC_TR_HU
#define BF_RTC_TR_HU_V(e) BF_RTC_TR_HU(BV_RTC_TR_HU__##e)
#define BFM_RTC_TR_HU_V(v) BM_RTC_TR_HU
#define BP_RTC_TR_MNT 12
#define BM_RTC_TR_MNT 0x7000
#define BF_RTC_TR_MNT(v) (((v) & 0x7) << 12)
#define BFM_RTC_TR_MNT(v) BM_RTC_TR_MNT
#define BF_RTC_TR_MNT_V(e) BF_RTC_TR_MNT(BV_RTC_TR_MNT__##e)
#define BFM_RTC_TR_MNT_V(v) BM_RTC_TR_MNT
#define BP_RTC_TR_MNU 8
#define BM_RTC_TR_MNU 0xf00
#define BF_RTC_TR_MNU(v) (((v) & 0xf) << 8)
#define BFM_RTC_TR_MNU(v) BM_RTC_TR_MNU
#define BF_RTC_TR_MNU_V(e) BF_RTC_TR_MNU(BV_RTC_TR_MNU__##e)
#define BFM_RTC_TR_MNU_V(v) BM_RTC_TR_MNU
#define BP_RTC_TR_ST 4
#define BM_RTC_TR_ST 0x70
#define BF_RTC_TR_ST(v) (((v) & 0x7) << 4)
#define BFM_RTC_TR_ST(v) BM_RTC_TR_ST
#define BF_RTC_TR_ST_V(e) BF_RTC_TR_ST(BV_RTC_TR_ST__##e)
#define BFM_RTC_TR_ST_V(v) BM_RTC_TR_ST
#define BP_RTC_TR_SU 0
#define BM_RTC_TR_SU 0xf
#define BF_RTC_TR_SU(v) (((v) & 0xf) << 0)
#define BFM_RTC_TR_SU(v) BM_RTC_TR_SU
#define BF_RTC_TR_SU_V(e) BF_RTC_TR_SU(BV_RTC_TR_SU__##e)
#define BFM_RTC_TR_SU_V(v) BM_RTC_TR_SU
#define BP_RTC_TR_PM 22
#define BM_RTC_TR_PM 0x400000
#define BF_RTC_TR_PM(v) (((v) & 0x1) << 22)
#define BFM_RTC_TR_PM(v) BM_RTC_TR_PM
#define BF_RTC_TR_PM_V(e) BF_RTC_TR_PM(BV_RTC_TR_PM__##e)
#define BFM_RTC_TR_PM_V(v) BM_RTC_TR_PM
#define REG_RTC_TSTR st_reg(RTC_TSTR)
#define STA_RTC_TSTR (0x58004000 + 0x30)
#define STO_RTC_TSTR (0x30)
#define STT_RTC_TSTR STIO_32_RW
#define STN_RTC_TSTR RTC_TSTR
#define BP_RTC_TSTR_HT 20
#define BM_RTC_TSTR_HT 0x300000
#define BF_RTC_TSTR_HT(v) (((v) & 0x3) << 20)
#define BFM_RTC_TSTR_HT(v) BM_RTC_TSTR_HT
#define BF_RTC_TSTR_HT_V(e) BF_RTC_TSTR_HT(BV_RTC_TSTR_HT__##e)
#define BFM_RTC_TSTR_HT_V(v) BM_RTC_TSTR_HT
#define BP_RTC_TSTR_HU 16
#define BM_RTC_TSTR_HU 0xf0000
#define BF_RTC_TSTR_HU(v) (((v) & 0xf) << 16)
#define BFM_RTC_TSTR_HU(v) BM_RTC_TSTR_HU
#define BF_RTC_TSTR_HU_V(e) BF_RTC_TSTR_HU(BV_RTC_TSTR_HU__##e)
#define BFM_RTC_TSTR_HU_V(v) BM_RTC_TSTR_HU
#define BP_RTC_TSTR_MNT 12
#define BM_RTC_TSTR_MNT 0x7000
#define BF_RTC_TSTR_MNT(v) (((v) & 0x7) << 12)
#define BFM_RTC_TSTR_MNT(v) BM_RTC_TSTR_MNT
#define BF_RTC_TSTR_MNT_V(e) BF_RTC_TSTR_MNT(BV_RTC_TSTR_MNT__##e)
#define BFM_RTC_TSTR_MNT_V(v) BM_RTC_TSTR_MNT
#define BP_RTC_TSTR_MNU 8
#define BM_RTC_TSTR_MNU 0xf00
#define BF_RTC_TSTR_MNU(v) (((v) & 0xf) << 8)
#define BFM_RTC_TSTR_MNU(v) BM_RTC_TSTR_MNU
#define BF_RTC_TSTR_MNU_V(e) BF_RTC_TSTR_MNU(BV_RTC_TSTR_MNU__##e)
#define BFM_RTC_TSTR_MNU_V(v) BM_RTC_TSTR_MNU
#define BP_RTC_TSTR_ST 4
#define BM_RTC_TSTR_ST 0x70
#define BF_RTC_TSTR_ST(v) (((v) & 0x7) << 4)
#define BFM_RTC_TSTR_ST(v) BM_RTC_TSTR_ST
#define BF_RTC_TSTR_ST_V(e) BF_RTC_TSTR_ST(BV_RTC_TSTR_ST__##e)
#define BFM_RTC_TSTR_ST_V(v) BM_RTC_TSTR_ST
#define BP_RTC_TSTR_SU 0
#define BM_RTC_TSTR_SU 0xf
#define BF_RTC_TSTR_SU(v) (((v) & 0xf) << 0)
#define BFM_RTC_TSTR_SU(v) BM_RTC_TSTR_SU
#define BF_RTC_TSTR_SU_V(e) BF_RTC_TSTR_SU(BV_RTC_TSTR_SU__##e)
#define BFM_RTC_TSTR_SU_V(v) BM_RTC_TSTR_SU
#define BP_RTC_TSTR_PM 22
#define BM_RTC_TSTR_PM 0x400000
#define BF_RTC_TSTR_PM(v) (((v) & 0x1) << 22)
#define BFM_RTC_TSTR_PM(v) BM_RTC_TSTR_PM
#define BF_RTC_TSTR_PM_V(e) BF_RTC_TSTR_PM(BV_RTC_TSTR_PM__##e)
#define BFM_RTC_TSTR_PM_V(v) BM_RTC_TSTR_PM
#define REG_RTC_DR st_reg(RTC_DR)
#define STA_RTC_DR (0x58004000 + 0x4)
#define STO_RTC_DR (0x4)
#define STT_RTC_DR STIO_32_RW
#define STN_RTC_DR RTC_DR
#define BP_RTC_DR_YT 20
#define BM_RTC_DR_YT 0xf00000
#define BF_RTC_DR_YT(v) (((v) & 0xf) << 20)
#define BFM_RTC_DR_YT(v) BM_RTC_DR_YT
#define BF_RTC_DR_YT_V(e) BF_RTC_DR_YT(BV_RTC_DR_YT__##e)
#define BFM_RTC_DR_YT_V(v) BM_RTC_DR_YT
#define BP_RTC_DR_YU 16
#define BM_RTC_DR_YU 0xf0000
#define BF_RTC_DR_YU(v) (((v) & 0xf) << 16)
#define BFM_RTC_DR_YU(v) BM_RTC_DR_YU
#define BF_RTC_DR_YU_V(e) BF_RTC_DR_YU(BV_RTC_DR_YU__##e)
#define BFM_RTC_DR_YU_V(v) BM_RTC_DR_YU
#define BP_RTC_DR_WDU 13
#define BM_RTC_DR_WDU 0xe000
#define BF_RTC_DR_WDU(v) (((v) & 0x7) << 13)
#define BFM_RTC_DR_WDU(v) BM_RTC_DR_WDU
#define BF_RTC_DR_WDU_V(e) BF_RTC_DR_WDU(BV_RTC_DR_WDU__##e)
#define BFM_RTC_DR_WDU_V(v) BM_RTC_DR_WDU
#define BP_RTC_DR_MU 8
#define BM_RTC_DR_MU 0xf00
#define BF_RTC_DR_MU(v) (((v) & 0xf) << 8)
#define BFM_RTC_DR_MU(v) BM_RTC_DR_MU
#define BF_RTC_DR_MU_V(e) BF_RTC_DR_MU(BV_RTC_DR_MU__##e)
#define BFM_RTC_DR_MU_V(v) BM_RTC_DR_MU
#define BP_RTC_DR_DT 4
#define BM_RTC_DR_DT 0x30
#define BF_RTC_DR_DT(v) (((v) & 0x3) << 4)
#define BFM_RTC_DR_DT(v) BM_RTC_DR_DT
#define BF_RTC_DR_DT_V(e) BF_RTC_DR_DT(BV_RTC_DR_DT__##e)
#define BFM_RTC_DR_DT_V(v) BM_RTC_DR_DT
#define BP_RTC_DR_DU 0
#define BM_RTC_DR_DU 0xf
#define BF_RTC_DR_DU(v) (((v) & 0xf) << 0)
#define BFM_RTC_DR_DU(v) BM_RTC_DR_DU
#define BF_RTC_DR_DU_V(e) BF_RTC_DR_DU(BV_RTC_DR_DU__##e)
#define BFM_RTC_DR_DU_V(v) BM_RTC_DR_DU
#define BP_RTC_DR_MT 12
#define BM_RTC_DR_MT 0x1000
#define BF_RTC_DR_MT(v) (((v) & 0x1) << 12)
#define BFM_RTC_DR_MT(v) BM_RTC_DR_MT
#define BF_RTC_DR_MT_V(e) BF_RTC_DR_MT(BV_RTC_DR_MT__##e)
#define BFM_RTC_DR_MT_V(v) BM_RTC_DR_MT
#define REG_RTC_DRTR st_reg(RTC_DRTR)
#define STA_RTC_DRTR (0x58004000 + 0x34)
#define STO_RTC_DRTR (0x34)
#define STT_RTC_DRTR STIO_32_RW
#define STN_RTC_DRTR RTC_DRTR
#define BP_RTC_DRTR_YT 20
#define BM_RTC_DRTR_YT 0xf00000
#define BF_RTC_DRTR_YT(v) (((v) & 0xf) << 20)
#define BFM_RTC_DRTR_YT(v) BM_RTC_DRTR_YT
#define BF_RTC_DRTR_YT_V(e) BF_RTC_DRTR_YT(BV_RTC_DRTR_YT__##e)
#define BFM_RTC_DRTR_YT_V(v) BM_RTC_DRTR_YT
#define BP_RTC_DRTR_YU 16
#define BM_RTC_DRTR_YU 0xf0000
#define BF_RTC_DRTR_YU(v) (((v) & 0xf) << 16)
#define BFM_RTC_DRTR_YU(v) BM_RTC_DRTR_YU
#define BF_RTC_DRTR_YU_V(e) BF_RTC_DRTR_YU(BV_RTC_DRTR_YU__##e)
#define BFM_RTC_DRTR_YU_V(v) BM_RTC_DRTR_YU
#define BP_RTC_DRTR_WDU 13
#define BM_RTC_DRTR_WDU 0xe000
#define BF_RTC_DRTR_WDU(v) (((v) & 0x7) << 13)
#define BFM_RTC_DRTR_WDU(v) BM_RTC_DRTR_WDU
#define BF_RTC_DRTR_WDU_V(e) BF_RTC_DRTR_WDU(BV_RTC_DRTR_WDU__##e)
#define BFM_RTC_DRTR_WDU_V(v) BM_RTC_DRTR_WDU
#define BP_RTC_DRTR_MU 8
#define BM_RTC_DRTR_MU 0xf00
#define BF_RTC_DRTR_MU(v) (((v) & 0xf) << 8)
#define BFM_RTC_DRTR_MU(v) BM_RTC_DRTR_MU
#define BF_RTC_DRTR_MU_V(e) BF_RTC_DRTR_MU(BV_RTC_DRTR_MU__##e)
#define BFM_RTC_DRTR_MU_V(v) BM_RTC_DRTR_MU
#define BP_RTC_DRTR_DT 4
#define BM_RTC_DRTR_DT 0x30
#define BF_RTC_DRTR_DT(v) (((v) & 0x3) << 4)
#define BFM_RTC_DRTR_DT(v) BM_RTC_DRTR_DT
#define BF_RTC_DRTR_DT_V(e) BF_RTC_DRTR_DT(BV_RTC_DRTR_DT__##e)
#define BFM_RTC_DRTR_DT_V(v) BM_RTC_DRTR_DT
#define BP_RTC_DRTR_DU 0
#define BM_RTC_DRTR_DU 0xf
#define BF_RTC_DRTR_DU(v) (((v) & 0xf) << 0)
#define BFM_RTC_DRTR_DU(v) BM_RTC_DRTR_DU
#define BF_RTC_DRTR_DU_V(e) BF_RTC_DRTR_DU(BV_RTC_DRTR_DU__##e)
#define BFM_RTC_DRTR_DU_V(v) BM_RTC_DRTR_DU
#define BP_RTC_DRTR_MT 12
#define BM_RTC_DRTR_MT 0x1000
#define BF_RTC_DRTR_MT(v) (((v) & 0x1) << 12)
#define BFM_RTC_DRTR_MT(v) BM_RTC_DRTR_MT
#define BF_RTC_DRTR_MT_V(e) BF_RTC_DRTR_MT(BV_RTC_DRTR_MT__##e)
#define BFM_RTC_DRTR_MT_V(v) BM_RTC_DRTR_MT
#define REG_RTC_CR st_reg(RTC_CR)
#define STA_RTC_CR (0x58004000 + 0x8)
#define STO_RTC_CR (0x8)
#define STT_RTC_CR STIO_32_RW
#define STN_RTC_CR RTC_CR
#define BP_RTC_CR_OSEL 21
#define BM_RTC_CR_OSEL 0x600000
#define BV_RTC_CR_OSEL__DISABLED 0x0
#define BV_RTC_CR_OSEL__ALARM_A 0x1
#define BV_RTC_CR_OSEL__ALARM_B 0x2
#define BV_RTC_CR_OSEL__WAKEUP 0x3
#define BF_RTC_CR_OSEL(v) (((v) & 0x3) << 21)
#define BFM_RTC_CR_OSEL(v) BM_RTC_CR_OSEL
#define BF_RTC_CR_OSEL_V(e) BF_RTC_CR_OSEL(BV_RTC_CR_OSEL__##e)
#define BFM_RTC_CR_OSEL_V(v) BM_RTC_CR_OSEL
#define BP_RTC_CR_ITSE 24
#define BM_RTC_CR_ITSE 0x1000000
#define BF_RTC_CR_ITSE(v) (((v) & 0x1) << 24)
#define BFM_RTC_CR_ITSE(v) BM_RTC_CR_ITSE
#define BF_RTC_CR_ITSE_V(e) BF_RTC_CR_ITSE(BV_RTC_CR_ITSE__##e)
#define BFM_RTC_CR_ITSE_V(v) BM_RTC_CR_ITSE
#define BP_RTC_CR_COE 23
#define BM_RTC_CR_COE 0x800000
#define BF_RTC_CR_COE(v) (((v) & 0x1) << 23)
#define BFM_RTC_CR_COE(v) BM_RTC_CR_COE
#define BF_RTC_CR_COE_V(e) BF_RTC_CR_COE(BV_RTC_CR_COE__##e)
#define BFM_RTC_CR_COE_V(v) BM_RTC_CR_COE
#define BP_RTC_CR_POL 20
#define BM_RTC_CR_POL 0x100000
#define BF_RTC_CR_POL(v) (((v) & 0x1) << 20)
#define BFM_RTC_CR_POL(v) BM_RTC_CR_POL
#define BF_RTC_CR_POL_V(e) BF_RTC_CR_POL(BV_RTC_CR_POL__##e)
#define BFM_RTC_CR_POL_V(v) BM_RTC_CR_POL
#define BP_RTC_CR_COSEL 19
#define BM_RTC_CR_COSEL 0x80000
#define BF_RTC_CR_COSEL(v) (((v) & 0x1) << 19)
#define BFM_RTC_CR_COSEL(v) BM_RTC_CR_COSEL
#define BF_RTC_CR_COSEL_V(e) BF_RTC_CR_COSEL(BV_RTC_CR_COSEL__##e)
#define BFM_RTC_CR_COSEL_V(v) BM_RTC_CR_COSEL
#define BP_RTC_CR_BKP 18
#define BM_RTC_CR_BKP 0x40000
#define BF_RTC_CR_BKP(v) (((v) & 0x1) << 18)
#define BFM_RTC_CR_BKP(v) BM_RTC_CR_BKP
#define BF_RTC_CR_BKP_V(e) BF_RTC_CR_BKP(BV_RTC_CR_BKP__##e)
#define BFM_RTC_CR_BKP_V(v) BM_RTC_CR_BKP
#define BP_RTC_CR_SUB1H 17
#define BM_RTC_CR_SUB1H 0x20000
#define BF_RTC_CR_SUB1H(v) (((v) & 0x1) << 17)
#define BFM_RTC_CR_SUB1H(v) BM_RTC_CR_SUB1H
#define BF_RTC_CR_SUB1H_V(e) BF_RTC_CR_SUB1H(BV_RTC_CR_SUB1H__##e)
#define BFM_RTC_CR_SUB1H_V(v) BM_RTC_CR_SUB1H
#define BP_RTC_CR_ADD1H 16
#define BM_RTC_CR_ADD1H 0x10000
#define BF_RTC_CR_ADD1H(v) (((v) & 0x1) << 16)
#define BFM_RTC_CR_ADD1H(v) BM_RTC_CR_ADD1H
#define BF_RTC_CR_ADD1H_V(e) BF_RTC_CR_ADD1H(BV_RTC_CR_ADD1H__##e)
#define BFM_RTC_CR_ADD1H_V(v) BM_RTC_CR_ADD1H
#define BP_RTC_CR_TSIE 15
#define BM_RTC_CR_TSIE 0x8000
#define BF_RTC_CR_TSIE(v) (((v) & 0x1) << 15)
#define BFM_RTC_CR_TSIE(v) BM_RTC_CR_TSIE
#define BF_RTC_CR_TSIE_V(e) BF_RTC_CR_TSIE(BV_RTC_CR_TSIE__##e)
#define BFM_RTC_CR_TSIE_V(v) BM_RTC_CR_TSIE
#define BP_RTC_CR_WUTIE 14
#define BM_RTC_CR_WUTIE 0x4000
#define BF_RTC_CR_WUTIE(v) (((v) & 0x1) << 14)
#define BFM_RTC_CR_WUTIE(v) BM_RTC_CR_WUTIE
#define BF_RTC_CR_WUTIE_V(e) BF_RTC_CR_WUTIE(BV_RTC_CR_WUTIE__##e)
#define BFM_RTC_CR_WUTIE_V(v) BM_RTC_CR_WUTIE
#define BP_RTC_CR_ALRBIE 13
#define BM_RTC_CR_ALRBIE 0x2000
#define BF_RTC_CR_ALRBIE(v) (((v) & 0x1) << 13)
#define BFM_RTC_CR_ALRBIE(v) BM_RTC_CR_ALRBIE
#define BF_RTC_CR_ALRBIE_V(e) BF_RTC_CR_ALRBIE(BV_RTC_CR_ALRBIE__##e)
#define BFM_RTC_CR_ALRBIE_V(v) BM_RTC_CR_ALRBIE
#define BP_RTC_CR_ALRAIE 12
#define BM_RTC_CR_ALRAIE 0x1000
#define BF_RTC_CR_ALRAIE(v) (((v) & 0x1) << 12)
#define BFM_RTC_CR_ALRAIE(v) BM_RTC_CR_ALRAIE
#define BF_RTC_CR_ALRAIE_V(e) BF_RTC_CR_ALRAIE(BV_RTC_CR_ALRAIE__##e)
#define BFM_RTC_CR_ALRAIE_V(v) BM_RTC_CR_ALRAIE
#define BP_RTC_CR_TSE 11
#define BM_RTC_CR_TSE 0x800
#define BF_RTC_CR_TSE(v) (((v) & 0x1) << 11)
#define BFM_RTC_CR_TSE(v) BM_RTC_CR_TSE
#define BF_RTC_CR_TSE_V(e) BF_RTC_CR_TSE(BV_RTC_CR_TSE__##e)
#define BFM_RTC_CR_TSE_V(v) BM_RTC_CR_TSE
#define BP_RTC_CR_WUTE 10
#define BM_RTC_CR_WUTE 0x400
#define BF_RTC_CR_WUTE(v) (((v) & 0x1) << 10)
#define BFM_RTC_CR_WUTE(v) BM_RTC_CR_WUTE
#define BF_RTC_CR_WUTE_V(e) BF_RTC_CR_WUTE(BV_RTC_CR_WUTE__##e)
#define BFM_RTC_CR_WUTE_V(v) BM_RTC_CR_WUTE
#define BP_RTC_CR_ALRBE 9
#define BM_RTC_CR_ALRBE 0x200
#define BF_RTC_CR_ALRBE(v) (((v) & 0x1) << 9)
#define BFM_RTC_CR_ALRBE(v) BM_RTC_CR_ALRBE
#define BF_RTC_CR_ALRBE_V(e) BF_RTC_CR_ALRBE(BV_RTC_CR_ALRBE__##e)
#define BFM_RTC_CR_ALRBE_V(v) BM_RTC_CR_ALRBE
#define BP_RTC_CR_ALRAE 8
#define BM_RTC_CR_ALRAE 0x100
#define BF_RTC_CR_ALRAE(v) (((v) & 0x1) << 8)
#define BFM_RTC_CR_ALRAE(v) BM_RTC_CR_ALRAE
#define BF_RTC_CR_ALRAE_V(e) BF_RTC_CR_ALRAE(BV_RTC_CR_ALRAE__##e)
#define BFM_RTC_CR_ALRAE_V(v) BM_RTC_CR_ALRAE
#define BP_RTC_CR_FMT 6
#define BM_RTC_CR_FMT 0x40
#define BF_RTC_CR_FMT(v) (((v) & 0x1) << 6)
#define BFM_RTC_CR_FMT(v) BM_RTC_CR_FMT
#define BF_RTC_CR_FMT_V(e) BF_RTC_CR_FMT(BV_RTC_CR_FMT__##e)
#define BFM_RTC_CR_FMT_V(v) BM_RTC_CR_FMT
#define BP_RTC_CR_BYPSHAD 5
#define BM_RTC_CR_BYPSHAD 0x20
#define BF_RTC_CR_BYPSHAD(v) (((v) & 0x1) << 5)
#define BFM_RTC_CR_BYPSHAD(v) BM_RTC_CR_BYPSHAD
#define BF_RTC_CR_BYPSHAD_V(e) BF_RTC_CR_BYPSHAD(BV_RTC_CR_BYPSHAD__##e)
#define BFM_RTC_CR_BYPSHAD_V(v) BM_RTC_CR_BYPSHAD
#define BP_RTC_CR_REFCKON 4
#define BM_RTC_CR_REFCKON 0x10
#define BF_RTC_CR_REFCKON(v) (((v) & 0x1) << 4)
#define BFM_RTC_CR_REFCKON(v) BM_RTC_CR_REFCKON
#define BF_RTC_CR_REFCKON_V(e) BF_RTC_CR_REFCKON(BV_RTC_CR_REFCKON__##e)
#define BFM_RTC_CR_REFCKON_V(v) BM_RTC_CR_REFCKON
#define BP_RTC_CR_TSEDGE 3
#define BM_RTC_CR_TSEDGE 0x8
#define BF_RTC_CR_TSEDGE(v) (((v) & 0x1) << 3)
#define BFM_RTC_CR_TSEDGE(v) BM_RTC_CR_TSEDGE
#define BF_RTC_CR_TSEDGE_V(e) BF_RTC_CR_TSEDGE(BV_RTC_CR_TSEDGE__##e)
#define BFM_RTC_CR_TSEDGE_V(v) BM_RTC_CR_TSEDGE
#define BP_RTC_CR_WUCKSEL 0
#define BM_RTC_CR_WUCKSEL 0x7
#define BV_RTC_CR_WUCKSEL__RTC_16 0x0
#define BV_RTC_CR_WUCKSEL__RTC_8 0x1
#define BV_RTC_CR_WUCKSEL__RTC_4 0x2
#define BV_RTC_CR_WUCKSEL__RTC_2 0x3
#define BV_RTC_CR_WUCKSEL__CK_SPRE 0x4
#define BV_RTC_CR_WUCKSEL__CK_SPRE_ADDWUT 0x6
#define BF_RTC_CR_WUCKSEL(v) (((v) & 0x7) << 0)
#define BFM_RTC_CR_WUCKSEL(v) BM_RTC_CR_WUCKSEL
#define BF_RTC_CR_WUCKSEL_V(e) BF_RTC_CR_WUCKSEL(BV_RTC_CR_WUCKSEL__##e)
#define BFM_RTC_CR_WUCKSEL_V(v) BM_RTC_CR_WUCKSEL
#define REG_RTC_ISR st_reg(RTC_ISR)
#define STA_RTC_ISR (0x58004000 + 0xc)
#define STO_RTC_ISR (0xc)
#define STT_RTC_ISR STIO_32_RW
#define STN_RTC_ISR RTC_ISR
#define BP_RTC_ISR_ITSF 17
#define BM_RTC_ISR_ITSF 0x20000
#define BF_RTC_ISR_ITSF(v) (((v) & 0x1) << 17)
#define BFM_RTC_ISR_ITSF(v) BM_RTC_ISR_ITSF
#define BF_RTC_ISR_ITSF_V(e) BF_RTC_ISR_ITSF(BV_RTC_ISR_ITSF__##e)
#define BFM_RTC_ISR_ITSF_V(v) BM_RTC_ISR_ITSF
#define BP_RTC_ISR_RECALPF 16
#define BM_RTC_ISR_RECALPF 0x10000
#define BF_RTC_ISR_RECALPF(v) (((v) & 0x1) << 16)
#define BFM_RTC_ISR_RECALPF(v) BM_RTC_ISR_RECALPF
#define BF_RTC_ISR_RECALPF_V(e) BF_RTC_ISR_RECALPF(BV_RTC_ISR_RECALPF__##e)
#define BFM_RTC_ISR_RECALPF_V(v) BM_RTC_ISR_RECALPF
#define BP_RTC_ISR_TAMP3F 15
#define BM_RTC_ISR_TAMP3F 0x8000
#define BF_RTC_ISR_TAMP3F(v) (((v) & 0x1) << 15)
#define BFM_RTC_ISR_TAMP3F(v) BM_RTC_ISR_TAMP3F
#define BF_RTC_ISR_TAMP3F_V(e) BF_RTC_ISR_TAMP3F(BV_RTC_ISR_TAMP3F__##e)
#define BFM_RTC_ISR_TAMP3F_V(v) BM_RTC_ISR_TAMP3F
#define BP_RTC_ISR_TAMP2F 14
#define BM_RTC_ISR_TAMP2F 0x4000
#define BF_RTC_ISR_TAMP2F(v) (((v) & 0x1) << 14)
#define BFM_RTC_ISR_TAMP2F(v) BM_RTC_ISR_TAMP2F
#define BF_RTC_ISR_TAMP2F_V(e) BF_RTC_ISR_TAMP2F(BV_RTC_ISR_TAMP2F__##e)
#define BFM_RTC_ISR_TAMP2F_V(v) BM_RTC_ISR_TAMP2F
#define BP_RTC_ISR_TAMP1F 13
#define BM_RTC_ISR_TAMP1F 0x2000
#define BF_RTC_ISR_TAMP1F(v) (((v) & 0x1) << 13)
#define BFM_RTC_ISR_TAMP1F(v) BM_RTC_ISR_TAMP1F
#define BF_RTC_ISR_TAMP1F_V(e) BF_RTC_ISR_TAMP1F(BV_RTC_ISR_TAMP1F__##e)
#define BFM_RTC_ISR_TAMP1F_V(v) BM_RTC_ISR_TAMP1F
#define BP_RTC_ISR_TSOVF 12
#define BM_RTC_ISR_TSOVF 0x1000
#define BF_RTC_ISR_TSOVF(v) (((v) & 0x1) << 12)
#define BFM_RTC_ISR_TSOVF(v) BM_RTC_ISR_TSOVF
#define BF_RTC_ISR_TSOVF_V(e) BF_RTC_ISR_TSOVF(BV_RTC_ISR_TSOVF__##e)
#define BFM_RTC_ISR_TSOVF_V(v) BM_RTC_ISR_TSOVF
#define BP_RTC_ISR_TSF 11
#define BM_RTC_ISR_TSF 0x800
#define BF_RTC_ISR_TSF(v) (((v) & 0x1) << 11)
#define BFM_RTC_ISR_TSF(v) BM_RTC_ISR_TSF
#define BF_RTC_ISR_TSF_V(e) BF_RTC_ISR_TSF(BV_RTC_ISR_TSF__##e)
#define BFM_RTC_ISR_TSF_V(v) BM_RTC_ISR_TSF
#define BP_RTC_ISR_WUTF 10
#define BM_RTC_ISR_WUTF 0x400
#define BF_RTC_ISR_WUTF(v) (((v) & 0x1) << 10)
#define BFM_RTC_ISR_WUTF(v) BM_RTC_ISR_WUTF
#define BF_RTC_ISR_WUTF_V(e) BF_RTC_ISR_WUTF(BV_RTC_ISR_WUTF__##e)
#define BFM_RTC_ISR_WUTF_V(v) BM_RTC_ISR_WUTF
#define BP_RTC_ISR_ALRBF 9
#define BM_RTC_ISR_ALRBF 0x200
#define BF_RTC_ISR_ALRBF(v) (((v) & 0x1) << 9)
#define BFM_RTC_ISR_ALRBF(v) BM_RTC_ISR_ALRBF
#define BF_RTC_ISR_ALRBF_V(e) BF_RTC_ISR_ALRBF(BV_RTC_ISR_ALRBF__##e)
#define BFM_RTC_ISR_ALRBF_V(v) BM_RTC_ISR_ALRBF
#define BP_RTC_ISR_ALRAF 8
#define BM_RTC_ISR_ALRAF 0x100
#define BF_RTC_ISR_ALRAF(v) (((v) & 0x1) << 8)
#define BFM_RTC_ISR_ALRAF(v) BM_RTC_ISR_ALRAF
#define BF_RTC_ISR_ALRAF_V(e) BF_RTC_ISR_ALRAF(BV_RTC_ISR_ALRAF__##e)
#define BFM_RTC_ISR_ALRAF_V(v) BM_RTC_ISR_ALRAF
#define BP_RTC_ISR_INIT 7
#define BM_RTC_ISR_INIT 0x80
#define BF_RTC_ISR_INIT(v) (((v) & 0x1) << 7)
#define BFM_RTC_ISR_INIT(v) BM_RTC_ISR_INIT
#define BF_RTC_ISR_INIT_V(e) BF_RTC_ISR_INIT(BV_RTC_ISR_INIT__##e)
#define BFM_RTC_ISR_INIT_V(v) BM_RTC_ISR_INIT
#define BP_RTC_ISR_INITF 6
#define BM_RTC_ISR_INITF 0x40
#define BF_RTC_ISR_INITF(v) (((v) & 0x1) << 6)
#define BFM_RTC_ISR_INITF(v) BM_RTC_ISR_INITF
#define BF_RTC_ISR_INITF_V(e) BF_RTC_ISR_INITF(BV_RTC_ISR_INITF__##e)
#define BFM_RTC_ISR_INITF_V(v) BM_RTC_ISR_INITF
#define BP_RTC_ISR_RSF 5
#define BM_RTC_ISR_RSF 0x20
#define BF_RTC_ISR_RSF(v) (((v) & 0x1) << 5)
#define BFM_RTC_ISR_RSF(v) BM_RTC_ISR_RSF
#define BF_RTC_ISR_RSF_V(e) BF_RTC_ISR_RSF(BV_RTC_ISR_RSF__##e)
#define BFM_RTC_ISR_RSF_V(v) BM_RTC_ISR_RSF
#define BP_RTC_ISR_INITS 4
#define BM_RTC_ISR_INITS 0x10
#define BF_RTC_ISR_INITS(v) (((v) & 0x1) << 4)
#define BFM_RTC_ISR_INITS(v) BM_RTC_ISR_INITS
#define BF_RTC_ISR_INITS_V(e) BF_RTC_ISR_INITS(BV_RTC_ISR_INITS__##e)
#define BFM_RTC_ISR_INITS_V(v) BM_RTC_ISR_INITS
#define BP_RTC_ISR_SHPF 3
#define BM_RTC_ISR_SHPF 0x8
#define BF_RTC_ISR_SHPF(v) (((v) & 0x1) << 3)
#define BFM_RTC_ISR_SHPF(v) BM_RTC_ISR_SHPF
#define BF_RTC_ISR_SHPF_V(e) BF_RTC_ISR_SHPF(BV_RTC_ISR_SHPF__##e)
#define BFM_RTC_ISR_SHPF_V(v) BM_RTC_ISR_SHPF
#define BP_RTC_ISR_WUTWF 2
#define BM_RTC_ISR_WUTWF 0x4
#define BF_RTC_ISR_WUTWF(v) (((v) & 0x1) << 2)
#define BFM_RTC_ISR_WUTWF(v) BM_RTC_ISR_WUTWF
#define BF_RTC_ISR_WUTWF_V(e) BF_RTC_ISR_WUTWF(BV_RTC_ISR_WUTWF__##e)
#define BFM_RTC_ISR_WUTWF_V(v) BM_RTC_ISR_WUTWF
#define BP_RTC_ISR_ALRBWF 1
#define BM_RTC_ISR_ALRBWF 0x2
#define BF_RTC_ISR_ALRBWF(v) (((v) & 0x1) << 1)
#define BFM_RTC_ISR_ALRBWF(v) BM_RTC_ISR_ALRBWF
#define BF_RTC_ISR_ALRBWF_V(e) BF_RTC_ISR_ALRBWF(BV_RTC_ISR_ALRBWF__##e)
#define BFM_RTC_ISR_ALRBWF_V(v) BM_RTC_ISR_ALRBWF
#define BP_RTC_ISR_ALRAWF 0
#define BM_RTC_ISR_ALRAWF 0x1
#define BF_RTC_ISR_ALRAWF(v) (((v) & 0x1) << 0)
#define BFM_RTC_ISR_ALRAWF(v) BM_RTC_ISR_ALRAWF
#define BF_RTC_ISR_ALRAWF_V(e) BF_RTC_ISR_ALRAWF(BV_RTC_ISR_ALRAWF__##e)
#define BFM_RTC_ISR_ALRAWF_V(v) BM_RTC_ISR_ALRAWF
#define REG_RTC_PRER st_reg(RTC_PRER)
#define STA_RTC_PRER (0x58004000 + 0x10)
#define STO_RTC_PRER (0x10)
#define STT_RTC_PRER STIO_32_RW
#define STN_RTC_PRER RTC_PRER
#define BP_RTC_PRER_PREDIV_A 16
#define BM_RTC_PRER_PREDIV_A 0x7f0000
#define BF_RTC_PRER_PREDIV_A(v) (((v) & 0x7f) << 16)
#define BFM_RTC_PRER_PREDIV_A(v) BM_RTC_PRER_PREDIV_A
#define BF_RTC_PRER_PREDIV_A_V(e) BF_RTC_PRER_PREDIV_A(BV_RTC_PRER_PREDIV_A__##e)
#define BFM_RTC_PRER_PREDIV_A_V(v) BM_RTC_PRER_PREDIV_A
#define BP_RTC_PRER_PREDIV_S 0
#define BM_RTC_PRER_PREDIV_S 0x7fff
#define BF_RTC_PRER_PREDIV_S(v) (((v) & 0x7fff) << 0)
#define BFM_RTC_PRER_PREDIV_S(v) BM_RTC_PRER_PREDIV_S
#define BF_RTC_PRER_PREDIV_S_V(e) BF_RTC_PRER_PREDIV_S(BV_RTC_PRER_PREDIV_S__##e)
#define BFM_RTC_PRER_PREDIV_S_V(v) BM_RTC_PRER_PREDIV_S
#define REG_RTC_WPR st_reg(RTC_WPR)
#define STA_RTC_WPR (0x58004000 + 0x24)
#define STO_RTC_WPR (0x24)
#define STT_RTC_WPR STIO_32_RW
#define STN_RTC_WPR RTC_WPR
#define BP_RTC_WPR_KEY 0
#define BM_RTC_WPR_KEY 0xff
#define BV_RTC_WPR_KEY__KEY1 0xca
#define BV_RTC_WPR_KEY__KEY2 0x53
#define BF_RTC_WPR_KEY(v) (((v) & 0xff) << 0)
#define BFM_RTC_WPR_KEY(v) BM_RTC_WPR_KEY
#define BF_RTC_WPR_KEY_V(e) BF_RTC_WPR_KEY(BV_RTC_WPR_KEY__##e)
#define BFM_RTC_WPR_KEY_V(v) BM_RTC_WPR_KEY
#define REG_RTC_SSR st_reg(RTC_SSR)
#define STA_RTC_SSR (0x58004000 + 0x28)
#define STO_RTC_SSR (0x28)
#define STT_RTC_SSR STIO_32_RW
#define STN_RTC_SSR RTC_SSR
#define BP_RTC_SSR_SS 0
#define BM_RTC_SSR_SS 0xffff
#define BF_RTC_SSR_SS(v) (((v) & 0xffff) << 0)
#define BFM_RTC_SSR_SS(v) BM_RTC_SSR_SS
#define BF_RTC_SSR_SS_V(e) BF_RTC_SSR_SS(BV_RTC_SSR_SS__##e)
#define BFM_RTC_SSR_SS_V(v) BM_RTC_SSR_SS
#define REG_RTC_TSSSR st_reg(RTC_TSSSR)
#define STA_RTC_TSSSR (0x58004000 + 0x38)
#define STO_RTC_TSSSR (0x38)
#define STT_RTC_TSSSR STIO_32_RW
#define STN_RTC_TSSSR RTC_TSSSR
#define BP_RTC_TSSSR_SS 0
#define BM_RTC_TSSSR_SS 0xffff
#define BF_RTC_TSSSR_SS(v) (((v) & 0xffff) << 0)
#define BFM_RTC_TSSSR_SS(v) BM_RTC_TSSSR_SS
#define BF_RTC_TSSSR_SS_V(e) BF_RTC_TSSSR_SS(BV_RTC_TSSSR_SS__##e)
#define BFM_RTC_TSSSR_SS_V(v) BM_RTC_TSSSR_SS
#define REG_RTC_OR st_reg(RTC_OR)
#define STA_RTC_OR (0x58004000 + 0x4c)
#define STO_RTC_OR (0x4c)
#define STT_RTC_OR STIO_32_RW
#define STN_RTC_OR RTC_OR
#define BP_RTC_OR_RTC_OUT_RMP 1
#define BM_RTC_OR_RTC_OUT_RMP 0x2
#define BF_RTC_OR_RTC_OUT_RMP(v) (((v) & 0x1) << 1)
#define BFM_RTC_OR_RTC_OUT_RMP(v) BM_RTC_OR_RTC_OUT_RMP
#define BF_RTC_OR_RTC_OUT_RMP_V(e) BF_RTC_OR_RTC_OUT_RMP(BV_RTC_OR_RTC_OUT_RMP__##e)
#define BFM_RTC_OR_RTC_OUT_RMP_V(v) BM_RTC_OR_RTC_OUT_RMP
#define BP_RTC_OR_RTC_ALARM_TYPE 0
#define BM_RTC_OR_RTC_ALARM_TYPE 0x1
#define BV_RTC_OR_RTC_ALARM_TYPE__OPEN_DRAIN 0x0
#define BV_RTC_OR_RTC_ALARM_TYPE__PUSH_PULL 0x1
#define BF_RTC_OR_RTC_ALARM_TYPE(v) (((v) & 0x1) << 0)
#define BFM_RTC_OR_RTC_ALARM_TYPE(v) BM_RTC_OR_RTC_ALARM_TYPE
#define BF_RTC_OR_RTC_ALARM_TYPE_V(e) BF_RTC_OR_RTC_ALARM_TYPE(BV_RTC_OR_RTC_ALARM_TYPE__##e)
#define BFM_RTC_OR_RTC_ALARM_TYPE_V(v) BM_RTC_OR_RTC_ALARM_TYPE
#define REG_RTC_BKPR(_n1) st_reg(RTC_BKPR(_n1))
#define STA_RTC_BKPR(_n1) (0x58004000 + 0x50 + (_n1) * 0x4)
#define STO_RTC_BKPR(_n1) (0x50 + (_n1) * 0x4)
#define STT_RTC_BKPR(_n1) STIO_32_RW
#define STN_RTC_BKPR(_n1) RTC_BKPR
#endif /* __HEADERGEN_RTC_H__*/

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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stm32h743 version: 1.0
* stm32h743 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_SPI_H__
#define __HEADERGEN_SPI_H__
#include "macro.h"
#define STA_SPI1 (0x40013000)
#define STA_SPI2 (0x40003800)
#define STA_SPI3 (0x40003c00)
#define STA_SPI4 (0x40013400)
#define STA_SPI5 (0x40015000)
#define STA_SPI6 (0x58001400)
#define REG_SPI_CR1 st_reg(SPI_CR1)
#define STO_SPI_CR1 (0x0)
#define STT_SPI_CR1 STIO_32_RW
#define STN_SPI_CR1 SPI_CR1
#define BP_SPI_CR1_IO_LOCK 16
#define BM_SPI_CR1_IO_LOCK 0x10000
#define BF_SPI_CR1_IO_LOCK(v) (((v) & 0x1) << 16)
#define BFM_SPI_CR1_IO_LOCK(v) BM_SPI_CR1_IO_LOCK
#define BF_SPI_CR1_IO_LOCK_V(e) BF_SPI_CR1_IO_LOCK(BV_SPI_CR1_IO_LOCK__##e)
#define BFM_SPI_CR1_IO_LOCK_V(v) BM_SPI_CR1_IO_LOCK
#define BP_SPI_CR1_TCRCINI 15
#define BM_SPI_CR1_TCRCINI 0x8000
#define BF_SPI_CR1_TCRCINI(v) (((v) & 0x1) << 15)
#define BFM_SPI_CR1_TCRCINI(v) BM_SPI_CR1_TCRCINI
#define BF_SPI_CR1_TCRCINI_V(e) BF_SPI_CR1_TCRCINI(BV_SPI_CR1_TCRCINI__##e)
#define BFM_SPI_CR1_TCRCINI_V(v) BM_SPI_CR1_TCRCINI
#define BP_SPI_CR1_RCRCINI 14
#define BM_SPI_CR1_RCRCINI 0x4000
#define BF_SPI_CR1_RCRCINI(v) (((v) & 0x1) << 14)
#define BFM_SPI_CR1_RCRCINI(v) BM_SPI_CR1_RCRCINI
#define BF_SPI_CR1_RCRCINI_V(e) BF_SPI_CR1_RCRCINI(BV_SPI_CR1_RCRCINI__##e)
#define BFM_SPI_CR1_RCRCINI_V(v) BM_SPI_CR1_RCRCINI
#define BP_SPI_CR1_CRC33_17 13
#define BM_SPI_CR1_CRC33_17 0x2000
#define BF_SPI_CR1_CRC33_17(v) (((v) & 0x1) << 13)
#define BFM_SPI_CR1_CRC33_17(v) BM_SPI_CR1_CRC33_17
#define BF_SPI_CR1_CRC33_17_V(e) BF_SPI_CR1_CRC33_17(BV_SPI_CR1_CRC33_17__##e)
#define BFM_SPI_CR1_CRC33_17_V(v) BM_SPI_CR1_CRC33_17
#define BP_SPI_CR1_SSI 12
#define BM_SPI_CR1_SSI 0x1000
#define BF_SPI_CR1_SSI(v) (((v) & 0x1) << 12)
#define BFM_SPI_CR1_SSI(v) BM_SPI_CR1_SSI
#define BF_SPI_CR1_SSI_V(e) BF_SPI_CR1_SSI(BV_SPI_CR1_SSI__##e)
#define BFM_SPI_CR1_SSI_V(v) BM_SPI_CR1_SSI
#define BP_SPI_CR1_HDDIR 11
#define BM_SPI_CR1_HDDIR 0x800
#define BF_SPI_CR1_HDDIR(v) (((v) & 0x1) << 11)
#define BFM_SPI_CR1_HDDIR(v) BM_SPI_CR1_HDDIR
#define BF_SPI_CR1_HDDIR_V(e) BF_SPI_CR1_HDDIR(BV_SPI_CR1_HDDIR__##e)
#define BFM_SPI_CR1_HDDIR_V(v) BM_SPI_CR1_HDDIR
#define BP_SPI_CR1_CSUSP 10
#define BM_SPI_CR1_CSUSP 0x400
#define BF_SPI_CR1_CSUSP(v) (((v) & 0x1) << 10)
#define BFM_SPI_CR1_CSUSP(v) BM_SPI_CR1_CSUSP
#define BF_SPI_CR1_CSUSP_V(e) BF_SPI_CR1_CSUSP(BV_SPI_CR1_CSUSP__##e)
#define BFM_SPI_CR1_CSUSP_V(v) BM_SPI_CR1_CSUSP
#define BP_SPI_CR1_CSTART 9
#define BM_SPI_CR1_CSTART 0x200
#define BF_SPI_CR1_CSTART(v) (((v) & 0x1) << 9)
#define BFM_SPI_CR1_CSTART(v) BM_SPI_CR1_CSTART
#define BF_SPI_CR1_CSTART_V(e) BF_SPI_CR1_CSTART(BV_SPI_CR1_CSTART__##e)
#define BFM_SPI_CR1_CSTART_V(v) BM_SPI_CR1_CSTART
#define BP_SPI_CR1_MASRX 8
#define BM_SPI_CR1_MASRX 0x100
#define BF_SPI_CR1_MASRX(v) (((v) & 0x1) << 8)
#define BFM_SPI_CR1_MASRX(v) BM_SPI_CR1_MASRX
#define BF_SPI_CR1_MASRX_V(e) BF_SPI_CR1_MASRX(BV_SPI_CR1_MASRX__##e)
#define BFM_SPI_CR1_MASRX_V(v) BM_SPI_CR1_MASRX
#define BP_SPI_CR1_SPE 0
#define BM_SPI_CR1_SPE 0x1
#define BF_SPI_CR1_SPE(v) (((v) & 0x1) << 0)
#define BFM_SPI_CR1_SPE(v) BM_SPI_CR1_SPE
#define BF_SPI_CR1_SPE_V(e) BF_SPI_CR1_SPE(BV_SPI_CR1_SPE__##e)
#define BFM_SPI_CR1_SPE_V(v) BM_SPI_CR1_SPE
#define REG_SPI_CR2 st_reg(SPI_CR2)
#define STO_SPI_CR2 (0x4)
#define STT_SPI_CR2 STIO_32_RW
#define STN_SPI_CR2 SPI_CR2
#define BP_SPI_CR2_TSER 16
#define BM_SPI_CR2_TSER 0xffff0000
#define BF_SPI_CR2_TSER(v) (((v) & 0xffff) << 16)
#define BFM_SPI_CR2_TSER(v) BM_SPI_CR2_TSER
#define BF_SPI_CR2_TSER_V(e) BF_SPI_CR2_TSER(BV_SPI_CR2_TSER__##e)
#define BFM_SPI_CR2_TSER_V(v) BM_SPI_CR2_TSER
#define BP_SPI_CR2_TSIZE 0
#define BM_SPI_CR2_TSIZE 0xffff
#define BF_SPI_CR2_TSIZE(v) (((v) & 0xffff) << 0)
#define BFM_SPI_CR2_TSIZE(v) BM_SPI_CR2_TSIZE
#define BF_SPI_CR2_TSIZE_V(e) BF_SPI_CR2_TSIZE(BV_SPI_CR2_TSIZE__##e)
#define BFM_SPI_CR2_TSIZE_V(v) BM_SPI_CR2_TSIZE
#define REG_SPI_CFG1 st_reg(SPI_CFG1)
#define STO_SPI_CFG1 (0x8)
#define STT_SPI_CFG1 STIO_32_RW
#define STN_SPI_CFG1 SPI_CFG1
#define BP_SPI_CFG1_MBR 28
#define BM_SPI_CFG1_MBR 0x70000000
#define BF_SPI_CFG1_MBR(v) (((v) & 0x7) << 28)
#define BFM_SPI_CFG1_MBR(v) BM_SPI_CFG1_MBR
#define BF_SPI_CFG1_MBR_V(e) BF_SPI_CFG1_MBR(BV_SPI_CFG1_MBR__##e)
#define BFM_SPI_CFG1_MBR_V(v) BM_SPI_CFG1_MBR
#define BP_SPI_CFG1_CRCSIZE 16
#define BM_SPI_CFG1_CRCSIZE 0x1f0000
#define BF_SPI_CFG1_CRCSIZE(v) (((v) & 0x1f) << 16)
#define BFM_SPI_CFG1_CRCSIZE(v) BM_SPI_CFG1_CRCSIZE
#define BF_SPI_CFG1_CRCSIZE_V(e) BF_SPI_CFG1_CRCSIZE(BV_SPI_CFG1_CRCSIZE__##e)
#define BFM_SPI_CFG1_CRCSIZE_V(v) BM_SPI_CFG1_CRCSIZE
#define BP_SPI_CFG1_UDRDET 11
#define BM_SPI_CFG1_UDRDET 0x1800
#define BF_SPI_CFG1_UDRDET(v) (((v) & 0x3) << 11)
#define BFM_SPI_CFG1_UDRDET(v) BM_SPI_CFG1_UDRDET
#define BF_SPI_CFG1_UDRDET_V(e) BF_SPI_CFG1_UDRDET(BV_SPI_CFG1_UDRDET__##e)
#define BFM_SPI_CFG1_UDRDET_V(v) BM_SPI_CFG1_UDRDET
#define BP_SPI_CFG1_UDRCFG 9
#define BM_SPI_CFG1_UDRCFG 0x600
#define BF_SPI_CFG1_UDRCFG(v) (((v) & 0x3) << 9)
#define BFM_SPI_CFG1_UDRCFG(v) BM_SPI_CFG1_UDRCFG
#define BF_SPI_CFG1_UDRCFG_V(e) BF_SPI_CFG1_UDRCFG(BV_SPI_CFG1_UDRCFG__##e)
#define BFM_SPI_CFG1_UDRCFG_V(v) BM_SPI_CFG1_UDRCFG
#define BP_SPI_CFG1_FTHLV 5
#define BM_SPI_CFG1_FTHLV 0x1e0
#define BF_SPI_CFG1_FTHLV(v) (((v) & 0xf) << 5)
#define BFM_SPI_CFG1_FTHLV(v) BM_SPI_CFG1_FTHLV
#define BF_SPI_CFG1_FTHLV_V(e) BF_SPI_CFG1_FTHLV(BV_SPI_CFG1_FTHLV__##e)
#define BFM_SPI_CFG1_FTHLV_V(v) BM_SPI_CFG1_FTHLV
#define BP_SPI_CFG1_DSIZE 0
#define BM_SPI_CFG1_DSIZE 0x1f
#define BF_SPI_CFG1_DSIZE(v) (((v) & 0x1f) << 0)
#define BFM_SPI_CFG1_DSIZE(v) BM_SPI_CFG1_DSIZE
#define BF_SPI_CFG1_DSIZE_V(e) BF_SPI_CFG1_DSIZE(BV_SPI_CFG1_DSIZE__##e)
#define BFM_SPI_CFG1_DSIZE_V(v) BM_SPI_CFG1_DSIZE
#define BP_SPI_CFG1_CRCEN 22
#define BM_SPI_CFG1_CRCEN 0x400000
#define BF_SPI_CFG1_CRCEN(v) (((v) & 0x1) << 22)
#define BFM_SPI_CFG1_CRCEN(v) BM_SPI_CFG1_CRCEN
#define BF_SPI_CFG1_CRCEN_V(e) BF_SPI_CFG1_CRCEN(BV_SPI_CFG1_CRCEN__##e)
#define BFM_SPI_CFG1_CRCEN_V(v) BM_SPI_CFG1_CRCEN
#define BP_SPI_CFG1_TXDMAEN 15
#define BM_SPI_CFG1_TXDMAEN 0x8000
#define BF_SPI_CFG1_TXDMAEN(v) (((v) & 0x1) << 15)
#define BFM_SPI_CFG1_TXDMAEN(v) BM_SPI_CFG1_TXDMAEN
#define BF_SPI_CFG1_TXDMAEN_V(e) BF_SPI_CFG1_TXDMAEN(BV_SPI_CFG1_TXDMAEN__##e)
#define BFM_SPI_CFG1_TXDMAEN_V(v) BM_SPI_CFG1_TXDMAEN
#define BP_SPI_CFG1_RXDMAEN 14
#define BM_SPI_CFG1_RXDMAEN 0x4000
#define BF_SPI_CFG1_RXDMAEN(v) (((v) & 0x1) << 14)
#define BFM_SPI_CFG1_RXDMAEN(v) BM_SPI_CFG1_RXDMAEN
#define BF_SPI_CFG1_RXDMAEN_V(e) BF_SPI_CFG1_RXDMAEN(BV_SPI_CFG1_RXDMAEN__##e)
#define BFM_SPI_CFG1_RXDMAEN_V(v) BM_SPI_CFG1_RXDMAEN
#define REG_SPI_CFG2 st_reg(SPI_CFG2)
#define STO_SPI_CFG2 (0xc)
#define STT_SPI_CFG2 STIO_32_RW
#define STN_SPI_CFG2 SPI_CFG2
#define BP_SPI_CFG2_SP 19
#define BM_SPI_CFG2_SP 0x380000
#define BV_SPI_CFG2_SP__MOTOROLA 0x0
#define BV_SPI_CFG2_SP__TI 0x1
#define BF_SPI_CFG2_SP(v) (((v) & 0x7) << 19)
#define BFM_SPI_CFG2_SP(v) BM_SPI_CFG2_SP
#define BF_SPI_CFG2_SP_V(e) BF_SPI_CFG2_SP(BV_SPI_CFG2_SP__##e)
#define BFM_SPI_CFG2_SP_V(v) BM_SPI_CFG2_SP
#define BP_SPI_CFG2_COMM 17
#define BM_SPI_CFG2_COMM 0x60000
#define BV_SPI_CFG2_COMM__DUPLEX 0x0
#define BV_SPI_CFG2_COMM__TXONLY 0x1
#define BV_SPI_CFG2_COMM__RXONLY 0x2
#define BV_SPI_CFG2_COMM__HALF_DUPLEX 0x3
#define BF_SPI_CFG2_COMM(v) (((v) & 0x3) << 17)
#define BFM_SPI_CFG2_COMM(v) BM_SPI_CFG2_COMM
#define BF_SPI_CFG2_COMM_V(e) BF_SPI_CFG2_COMM(BV_SPI_CFG2_COMM__##e)
#define BFM_SPI_CFG2_COMM_V(v) BM_SPI_CFG2_COMM
#define BP_SPI_CFG2_MIDI 4
#define BM_SPI_CFG2_MIDI 0xf0
#define BF_SPI_CFG2_MIDI(v) (((v) & 0xf) << 4)
#define BFM_SPI_CFG2_MIDI(v) BM_SPI_CFG2_MIDI
#define BF_SPI_CFG2_MIDI_V(e) BF_SPI_CFG2_MIDI(BV_SPI_CFG2_MIDI__##e)
#define BFM_SPI_CFG2_MIDI_V(v) BM_SPI_CFG2_MIDI
#define BP_SPI_CFG2_MSSI 0
#define BM_SPI_CFG2_MSSI 0xf
#define BF_SPI_CFG2_MSSI(v) (((v) & 0xf) << 0)
#define BFM_SPI_CFG2_MSSI(v) BM_SPI_CFG2_MSSI
#define BF_SPI_CFG2_MSSI_V(e) BF_SPI_CFG2_MSSI(BV_SPI_CFG2_MSSI__##e)
#define BFM_SPI_CFG2_MSSI_V(v) BM_SPI_CFG2_MSSI
#define BP_SPI_CFG2_AFCNTR 31
#define BM_SPI_CFG2_AFCNTR 0x80000000
#define BF_SPI_CFG2_AFCNTR(v) (((v) & 0x1) << 31)
#define BFM_SPI_CFG2_AFCNTR(v) BM_SPI_CFG2_AFCNTR
#define BF_SPI_CFG2_AFCNTR_V(e) BF_SPI_CFG2_AFCNTR(BV_SPI_CFG2_AFCNTR__##e)
#define BFM_SPI_CFG2_AFCNTR_V(v) BM_SPI_CFG2_AFCNTR
#define BP_SPI_CFG2_SSOM 30
#define BM_SPI_CFG2_SSOM 0x40000000
#define BF_SPI_CFG2_SSOM(v) (((v) & 0x1) << 30)
#define BFM_SPI_CFG2_SSOM(v) BM_SPI_CFG2_SSOM
#define BF_SPI_CFG2_SSOM_V(e) BF_SPI_CFG2_SSOM(BV_SPI_CFG2_SSOM__##e)
#define BFM_SPI_CFG2_SSOM_V(v) BM_SPI_CFG2_SSOM
#define BP_SPI_CFG2_SSOE 29
#define BM_SPI_CFG2_SSOE 0x20000000
#define BF_SPI_CFG2_SSOE(v) (((v) & 0x1) << 29)
#define BFM_SPI_CFG2_SSOE(v) BM_SPI_CFG2_SSOE
#define BF_SPI_CFG2_SSOE_V(e) BF_SPI_CFG2_SSOE(BV_SPI_CFG2_SSOE__##e)
#define BFM_SPI_CFG2_SSOE_V(v) BM_SPI_CFG2_SSOE
#define BP_SPI_CFG2_SSIOP 28
#define BM_SPI_CFG2_SSIOP 0x10000000
#define BF_SPI_CFG2_SSIOP(v) (((v) & 0x1) << 28)
#define BFM_SPI_CFG2_SSIOP(v) BM_SPI_CFG2_SSIOP
#define BF_SPI_CFG2_SSIOP_V(e) BF_SPI_CFG2_SSIOP(BV_SPI_CFG2_SSIOP__##e)
#define BFM_SPI_CFG2_SSIOP_V(v) BM_SPI_CFG2_SSIOP
#define BP_SPI_CFG2_SSM 26
#define BM_SPI_CFG2_SSM 0x4000000
#define BV_SPI_CFG2_SSM__SS_PAD 0x0
#define BV_SPI_CFG2_SSM__SSI_BIT 0x1
#define BF_SPI_CFG2_SSM(v) (((v) & 0x1) << 26)
#define BFM_SPI_CFG2_SSM(v) BM_SPI_CFG2_SSM
#define BF_SPI_CFG2_SSM_V(e) BF_SPI_CFG2_SSM(BV_SPI_CFG2_SSM__##e)
#define BFM_SPI_CFG2_SSM_V(v) BM_SPI_CFG2_SSM
#define BP_SPI_CFG2_CPOL 25
#define BM_SPI_CFG2_CPOL 0x2000000
#define BF_SPI_CFG2_CPOL(v) (((v) & 0x1) << 25)
#define BFM_SPI_CFG2_CPOL(v) BM_SPI_CFG2_CPOL
#define BF_SPI_CFG2_CPOL_V(e) BF_SPI_CFG2_CPOL(BV_SPI_CFG2_CPOL__##e)
#define BFM_SPI_CFG2_CPOL_V(v) BM_SPI_CFG2_CPOL
#define BP_SPI_CFG2_CPHA 24
#define BM_SPI_CFG2_CPHA 0x1000000
#define BF_SPI_CFG2_CPHA(v) (((v) & 0x1) << 24)
#define BFM_SPI_CFG2_CPHA(v) BM_SPI_CFG2_CPHA
#define BF_SPI_CFG2_CPHA_V(e) BF_SPI_CFG2_CPHA(BV_SPI_CFG2_CPHA__##e)
#define BFM_SPI_CFG2_CPHA_V(v) BM_SPI_CFG2_CPHA
#define BP_SPI_CFG2_LSBFIRST 23
#define BM_SPI_CFG2_LSBFIRST 0x800000
#define BF_SPI_CFG2_LSBFIRST(v) (((v) & 0x1) << 23)
#define BFM_SPI_CFG2_LSBFIRST(v) BM_SPI_CFG2_LSBFIRST
#define BF_SPI_CFG2_LSBFIRST_V(e) BF_SPI_CFG2_LSBFIRST(BV_SPI_CFG2_LSBFIRST__##e)
#define BFM_SPI_CFG2_LSBFIRST_V(v) BM_SPI_CFG2_LSBFIRST
#define BP_SPI_CFG2_MASTER 22
#define BM_SPI_CFG2_MASTER 0x400000
#define BF_SPI_CFG2_MASTER(v) (((v) & 0x1) << 22)
#define BFM_SPI_CFG2_MASTER(v) BM_SPI_CFG2_MASTER
#define BF_SPI_CFG2_MASTER_V(e) BF_SPI_CFG2_MASTER(BV_SPI_CFG2_MASTER__##e)
#define BFM_SPI_CFG2_MASTER_V(v) BM_SPI_CFG2_MASTER
#define BP_SPI_CFG2_IOSWP 15
#define BM_SPI_CFG2_IOSWP 0x8000
#define BF_SPI_CFG2_IOSWP(v) (((v) & 0x1) << 15)
#define BFM_SPI_CFG2_IOSWP(v) BM_SPI_CFG2_IOSWP
#define BF_SPI_CFG2_IOSWP_V(e) BF_SPI_CFG2_IOSWP(BV_SPI_CFG2_IOSWP__##e)
#define BFM_SPI_CFG2_IOSWP_V(v) BM_SPI_CFG2_IOSWP
#define REG_SPI_IER st_reg(SPI_IER)
#define STO_SPI_IER (0x10)
#define STT_SPI_IER STIO_32_RW
#define STN_SPI_IER SPI_IER
#define BP_SPI_IER_TSERFIE 10
#define BM_SPI_IER_TSERFIE 0x400
#define BF_SPI_IER_TSERFIE(v) (((v) & 0x1) << 10)
#define BFM_SPI_IER_TSERFIE(v) BM_SPI_IER_TSERFIE
#define BF_SPI_IER_TSERFIE_V(e) BF_SPI_IER_TSERFIE(BV_SPI_IER_TSERFIE__##e)
#define BFM_SPI_IER_TSERFIE_V(v) BM_SPI_IER_TSERFIE
#define BP_SPI_IER_MODFIE 9
#define BM_SPI_IER_MODFIE 0x200
#define BF_SPI_IER_MODFIE(v) (((v) & 0x1) << 9)
#define BFM_SPI_IER_MODFIE(v) BM_SPI_IER_MODFIE
#define BF_SPI_IER_MODFIE_V(e) BF_SPI_IER_MODFIE(BV_SPI_IER_MODFIE__##e)
#define BFM_SPI_IER_MODFIE_V(v) BM_SPI_IER_MODFIE
#define BP_SPI_IER_TIFREIE 8
#define BM_SPI_IER_TIFREIE 0x100
#define BF_SPI_IER_TIFREIE(v) (((v) & 0x1) << 8)
#define BFM_SPI_IER_TIFREIE(v) BM_SPI_IER_TIFREIE
#define BF_SPI_IER_TIFREIE_V(e) BF_SPI_IER_TIFREIE(BV_SPI_IER_TIFREIE__##e)
#define BFM_SPI_IER_TIFREIE_V(v) BM_SPI_IER_TIFREIE
#define BP_SPI_IER_CRCEIE 7
#define BM_SPI_IER_CRCEIE 0x80
#define BF_SPI_IER_CRCEIE(v) (((v) & 0x1) << 7)
#define BFM_SPI_IER_CRCEIE(v) BM_SPI_IER_CRCEIE
#define BF_SPI_IER_CRCEIE_V(e) BF_SPI_IER_CRCEIE(BV_SPI_IER_CRCEIE__##e)
#define BFM_SPI_IER_CRCEIE_V(v) BM_SPI_IER_CRCEIE
#define BP_SPI_IER_OVRIE 6
#define BM_SPI_IER_OVRIE 0x40
#define BF_SPI_IER_OVRIE(v) (((v) & 0x1) << 6)
#define BFM_SPI_IER_OVRIE(v) BM_SPI_IER_OVRIE
#define BF_SPI_IER_OVRIE_V(e) BF_SPI_IER_OVRIE(BV_SPI_IER_OVRIE__##e)
#define BFM_SPI_IER_OVRIE_V(v) BM_SPI_IER_OVRIE
#define BP_SPI_IER_UDRIE 5
#define BM_SPI_IER_UDRIE 0x20
#define BF_SPI_IER_UDRIE(v) (((v) & 0x1) << 5)
#define BFM_SPI_IER_UDRIE(v) BM_SPI_IER_UDRIE
#define BF_SPI_IER_UDRIE_V(e) BF_SPI_IER_UDRIE(BV_SPI_IER_UDRIE__##e)
#define BFM_SPI_IER_UDRIE_V(v) BM_SPI_IER_UDRIE
#define BP_SPI_IER_TXTFIE 4
#define BM_SPI_IER_TXTFIE 0x10
#define BF_SPI_IER_TXTFIE(v) (((v) & 0x1) << 4)
#define BFM_SPI_IER_TXTFIE(v) BM_SPI_IER_TXTFIE
#define BF_SPI_IER_TXTFIE_V(e) BF_SPI_IER_TXTFIE(BV_SPI_IER_TXTFIE__##e)
#define BFM_SPI_IER_TXTFIE_V(v) BM_SPI_IER_TXTFIE
#define BP_SPI_IER_EOTIE 3
#define BM_SPI_IER_EOTIE 0x8
#define BF_SPI_IER_EOTIE(v) (((v) & 0x1) << 3)
#define BFM_SPI_IER_EOTIE(v) BM_SPI_IER_EOTIE
#define BF_SPI_IER_EOTIE_V(e) BF_SPI_IER_EOTIE(BV_SPI_IER_EOTIE__##e)
#define BFM_SPI_IER_EOTIE_V(v) BM_SPI_IER_EOTIE
#define BP_SPI_IER_DXPIE 2
#define BM_SPI_IER_DXPIE 0x4
#define BF_SPI_IER_DXPIE(v) (((v) & 0x1) << 2)
#define BFM_SPI_IER_DXPIE(v) BM_SPI_IER_DXPIE
#define BF_SPI_IER_DXPIE_V(e) BF_SPI_IER_DXPIE(BV_SPI_IER_DXPIE__##e)
#define BFM_SPI_IER_DXPIE_V(v) BM_SPI_IER_DXPIE
#define BP_SPI_IER_TXPIE 1
#define BM_SPI_IER_TXPIE 0x2
#define BF_SPI_IER_TXPIE(v) (((v) & 0x1) << 1)
#define BFM_SPI_IER_TXPIE(v) BM_SPI_IER_TXPIE
#define BF_SPI_IER_TXPIE_V(e) BF_SPI_IER_TXPIE(BV_SPI_IER_TXPIE__##e)
#define BFM_SPI_IER_TXPIE_V(v) BM_SPI_IER_TXPIE
#define BP_SPI_IER_RXPIE 0
#define BM_SPI_IER_RXPIE 0x1
#define BF_SPI_IER_RXPIE(v) (((v) & 0x1) << 0)
#define BFM_SPI_IER_RXPIE(v) BM_SPI_IER_RXPIE
#define BF_SPI_IER_RXPIE_V(e) BF_SPI_IER_RXPIE(BV_SPI_IER_RXPIE__##e)
#define BFM_SPI_IER_RXPIE_V(v) BM_SPI_IER_RXPIE
#define REG_SPI_SR st_reg(SPI_SR)
#define STO_SPI_SR (0x14)
#define STT_SPI_SR STIO_32_RW
#define STN_SPI_SR SPI_SR
#define BP_SPI_SR_CTSIZE 16
#define BM_SPI_SR_CTSIZE 0xffff0000
#define BF_SPI_SR_CTSIZE(v) (((v) & 0xffff) << 16)
#define BFM_SPI_SR_CTSIZE(v) BM_SPI_SR_CTSIZE
#define BF_SPI_SR_CTSIZE_V(e) BF_SPI_SR_CTSIZE(BV_SPI_SR_CTSIZE__##e)
#define BFM_SPI_SR_CTSIZE_V(v) BM_SPI_SR_CTSIZE
#define BP_SPI_SR_RXPLVL 13
#define BM_SPI_SR_RXPLVL 0x6000
#define BF_SPI_SR_RXPLVL(v) (((v) & 0x3) << 13)
#define BFM_SPI_SR_RXPLVL(v) BM_SPI_SR_RXPLVL
#define BF_SPI_SR_RXPLVL_V(e) BF_SPI_SR_RXPLVL(BV_SPI_SR_RXPLVL__##e)
#define BFM_SPI_SR_RXPLVL_V(v) BM_SPI_SR_RXPLVL
#define BP_SPI_SR_RXWNE 15
#define BM_SPI_SR_RXWNE 0x8000
#define BF_SPI_SR_RXWNE(v) (((v) & 0x1) << 15)
#define BFM_SPI_SR_RXWNE(v) BM_SPI_SR_RXWNE
#define BF_SPI_SR_RXWNE_V(e) BF_SPI_SR_RXWNE(BV_SPI_SR_RXWNE__##e)
#define BFM_SPI_SR_RXWNE_V(v) BM_SPI_SR_RXWNE
#define BP_SPI_SR_TXC 12
#define BM_SPI_SR_TXC 0x1000
#define BF_SPI_SR_TXC(v) (((v) & 0x1) << 12)
#define BFM_SPI_SR_TXC(v) BM_SPI_SR_TXC
#define BF_SPI_SR_TXC_V(e) BF_SPI_SR_TXC(BV_SPI_SR_TXC__##e)
#define BFM_SPI_SR_TXC_V(v) BM_SPI_SR_TXC
#define BP_SPI_SR_SUSP 11
#define BM_SPI_SR_SUSP 0x800
#define BF_SPI_SR_SUSP(v) (((v) & 0x1) << 11)
#define BFM_SPI_SR_SUSP(v) BM_SPI_SR_SUSP
#define BF_SPI_SR_SUSP_V(e) BF_SPI_SR_SUSP(BV_SPI_SR_SUSP__##e)
#define BFM_SPI_SR_SUSP_V(v) BM_SPI_SR_SUSP
#define BP_SPI_SR_TSERF 10
#define BM_SPI_SR_TSERF 0x400
#define BF_SPI_SR_TSERF(v) (((v) & 0x1) << 10)
#define BFM_SPI_SR_TSERF(v) BM_SPI_SR_TSERF
#define BF_SPI_SR_TSERF_V(e) BF_SPI_SR_TSERF(BV_SPI_SR_TSERF__##e)
#define BFM_SPI_SR_TSERF_V(v) BM_SPI_SR_TSERF
#define BP_SPI_SR_MODF 9
#define BM_SPI_SR_MODF 0x200
#define BF_SPI_SR_MODF(v) (((v) & 0x1) << 9)
#define BFM_SPI_SR_MODF(v) BM_SPI_SR_MODF
#define BF_SPI_SR_MODF_V(e) BF_SPI_SR_MODF(BV_SPI_SR_MODF__##e)
#define BFM_SPI_SR_MODF_V(v) BM_SPI_SR_MODF
#define BP_SPI_SR_TIFRE 8
#define BM_SPI_SR_TIFRE 0x100
#define BF_SPI_SR_TIFRE(v) (((v) & 0x1) << 8)
#define BFM_SPI_SR_TIFRE(v) BM_SPI_SR_TIFRE
#define BF_SPI_SR_TIFRE_V(e) BF_SPI_SR_TIFRE(BV_SPI_SR_TIFRE__##e)
#define BFM_SPI_SR_TIFRE_V(v) BM_SPI_SR_TIFRE
#define BP_SPI_SR_CRCE 7
#define BM_SPI_SR_CRCE 0x80
#define BF_SPI_SR_CRCE(v) (((v) & 0x1) << 7)
#define BFM_SPI_SR_CRCE(v) BM_SPI_SR_CRCE
#define BF_SPI_SR_CRCE_V(e) BF_SPI_SR_CRCE(BV_SPI_SR_CRCE__##e)
#define BFM_SPI_SR_CRCE_V(v) BM_SPI_SR_CRCE
#define BP_SPI_SR_OVR 6
#define BM_SPI_SR_OVR 0x40
#define BF_SPI_SR_OVR(v) (((v) & 0x1) << 6)
#define BFM_SPI_SR_OVR(v) BM_SPI_SR_OVR
#define BF_SPI_SR_OVR_V(e) BF_SPI_SR_OVR(BV_SPI_SR_OVR__##e)
#define BFM_SPI_SR_OVR_V(v) BM_SPI_SR_OVR
#define BP_SPI_SR_UDR 5
#define BM_SPI_SR_UDR 0x20
#define BF_SPI_SR_UDR(v) (((v) & 0x1) << 5)
#define BFM_SPI_SR_UDR(v) BM_SPI_SR_UDR
#define BF_SPI_SR_UDR_V(e) BF_SPI_SR_UDR(BV_SPI_SR_UDR__##e)
#define BFM_SPI_SR_UDR_V(v) BM_SPI_SR_UDR
#define BP_SPI_SR_TXTF 4
#define BM_SPI_SR_TXTF 0x10
#define BF_SPI_SR_TXTF(v) (((v) & 0x1) << 4)
#define BFM_SPI_SR_TXTF(v) BM_SPI_SR_TXTF
#define BF_SPI_SR_TXTF_V(e) BF_SPI_SR_TXTF(BV_SPI_SR_TXTF__##e)
#define BFM_SPI_SR_TXTF_V(v) BM_SPI_SR_TXTF
#define BP_SPI_SR_EOT 3
#define BM_SPI_SR_EOT 0x8
#define BF_SPI_SR_EOT(v) (((v) & 0x1) << 3)
#define BFM_SPI_SR_EOT(v) BM_SPI_SR_EOT
#define BF_SPI_SR_EOT_V(e) BF_SPI_SR_EOT(BV_SPI_SR_EOT__##e)
#define BFM_SPI_SR_EOT_V(v) BM_SPI_SR_EOT
#define BP_SPI_SR_DXP 2
#define BM_SPI_SR_DXP 0x4
#define BF_SPI_SR_DXP(v) (((v) & 0x1) << 2)
#define BFM_SPI_SR_DXP(v) BM_SPI_SR_DXP
#define BF_SPI_SR_DXP_V(e) BF_SPI_SR_DXP(BV_SPI_SR_DXP__##e)
#define BFM_SPI_SR_DXP_V(v) BM_SPI_SR_DXP
#define BP_SPI_SR_TXP 1
#define BM_SPI_SR_TXP 0x2
#define BF_SPI_SR_TXP(v) (((v) & 0x1) << 1)
#define BFM_SPI_SR_TXP(v) BM_SPI_SR_TXP
#define BF_SPI_SR_TXP_V(e) BF_SPI_SR_TXP(BV_SPI_SR_TXP__##e)
#define BFM_SPI_SR_TXP_V(v) BM_SPI_SR_TXP
#define BP_SPI_SR_RXP 0
#define BM_SPI_SR_RXP 0x1
#define BF_SPI_SR_RXP(v) (((v) & 0x1) << 0)
#define BFM_SPI_SR_RXP(v) BM_SPI_SR_RXP
#define BF_SPI_SR_RXP_V(e) BF_SPI_SR_RXP(BV_SPI_SR_RXP__##e)
#define BFM_SPI_SR_RXP_V(v) BM_SPI_SR_RXP
#define REG_SPI_IFCR st_reg(SPI_IFCR)
#define STO_SPI_IFCR (0x18)
#define STT_SPI_IFCR STIO_32_RW
#define STN_SPI_IFCR SPI_IFCR
#define BP_SPI_IFCR_SUSPC 11
#define BM_SPI_IFCR_SUSPC 0x800
#define BF_SPI_IFCR_SUSPC(v) (((v) & 0x1) << 11)
#define BFM_SPI_IFCR_SUSPC(v) BM_SPI_IFCR_SUSPC
#define BF_SPI_IFCR_SUSPC_V(e) BF_SPI_IFCR_SUSPC(BV_SPI_IFCR_SUSPC__##e)
#define BFM_SPI_IFCR_SUSPC_V(v) BM_SPI_IFCR_SUSPC
#define BP_SPI_IFCR_TSERFC 10
#define BM_SPI_IFCR_TSERFC 0x400
#define BF_SPI_IFCR_TSERFC(v) (((v) & 0x1) << 10)
#define BFM_SPI_IFCR_TSERFC(v) BM_SPI_IFCR_TSERFC
#define BF_SPI_IFCR_TSERFC_V(e) BF_SPI_IFCR_TSERFC(BV_SPI_IFCR_TSERFC__##e)
#define BFM_SPI_IFCR_TSERFC_V(v) BM_SPI_IFCR_TSERFC
#define BP_SPI_IFCR_MODFC 9
#define BM_SPI_IFCR_MODFC 0x200
#define BF_SPI_IFCR_MODFC(v) (((v) & 0x1) << 9)
#define BFM_SPI_IFCR_MODFC(v) BM_SPI_IFCR_MODFC
#define BF_SPI_IFCR_MODFC_V(e) BF_SPI_IFCR_MODFC(BV_SPI_IFCR_MODFC__##e)
#define BFM_SPI_IFCR_MODFC_V(v) BM_SPI_IFCR_MODFC
#define BP_SPI_IFCR_TIFREC 8
#define BM_SPI_IFCR_TIFREC 0x100
#define BF_SPI_IFCR_TIFREC(v) (((v) & 0x1) << 8)
#define BFM_SPI_IFCR_TIFREC(v) BM_SPI_IFCR_TIFREC
#define BF_SPI_IFCR_TIFREC_V(e) BF_SPI_IFCR_TIFREC(BV_SPI_IFCR_TIFREC__##e)
#define BFM_SPI_IFCR_TIFREC_V(v) BM_SPI_IFCR_TIFREC
#define BP_SPI_IFCR_CRCEC 7
#define BM_SPI_IFCR_CRCEC 0x80
#define BF_SPI_IFCR_CRCEC(v) (((v) & 0x1) << 7)
#define BFM_SPI_IFCR_CRCEC(v) BM_SPI_IFCR_CRCEC
#define BF_SPI_IFCR_CRCEC_V(e) BF_SPI_IFCR_CRCEC(BV_SPI_IFCR_CRCEC__##e)
#define BFM_SPI_IFCR_CRCEC_V(v) BM_SPI_IFCR_CRCEC
#define BP_SPI_IFCR_OVRC 6
#define BM_SPI_IFCR_OVRC 0x40
#define BF_SPI_IFCR_OVRC(v) (((v) & 0x1) << 6)
#define BFM_SPI_IFCR_OVRC(v) BM_SPI_IFCR_OVRC
#define BF_SPI_IFCR_OVRC_V(e) BF_SPI_IFCR_OVRC(BV_SPI_IFCR_OVRC__##e)
#define BFM_SPI_IFCR_OVRC_V(v) BM_SPI_IFCR_OVRC
#define BP_SPI_IFCR_UDRC 5
#define BM_SPI_IFCR_UDRC 0x20
#define BF_SPI_IFCR_UDRC(v) (((v) & 0x1) << 5)
#define BFM_SPI_IFCR_UDRC(v) BM_SPI_IFCR_UDRC
#define BF_SPI_IFCR_UDRC_V(e) BF_SPI_IFCR_UDRC(BV_SPI_IFCR_UDRC__##e)
#define BFM_SPI_IFCR_UDRC_V(v) BM_SPI_IFCR_UDRC
#define BP_SPI_IFCR_TXTFC 4
#define BM_SPI_IFCR_TXTFC 0x10
#define BF_SPI_IFCR_TXTFC(v) (((v) & 0x1) << 4)
#define BFM_SPI_IFCR_TXTFC(v) BM_SPI_IFCR_TXTFC
#define BF_SPI_IFCR_TXTFC_V(e) BF_SPI_IFCR_TXTFC(BV_SPI_IFCR_TXTFC__##e)
#define BFM_SPI_IFCR_TXTFC_V(v) BM_SPI_IFCR_TXTFC
#define BP_SPI_IFCR_EOTC 3
#define BM_SPI_IFCR_EOTC 0x8
#define BF_SPI_IFCR_EOTC(v) (((v) & 0x1) << 3)
#define BFM_SPI_IFCR_EOTC(v) BM_SPI_IFCR_EOTC
#define BF_SPI_IFCR_EOTC_V(e) BF_SPI_IFCR_EOTC(BV_SPI_IFCR_EOTC__##e)
#define BFM_SPI_IFCR_EOTC_V(v) BM_SPI_IFCR_EOTC
#define REG_SPI_TXDR8 st_reg(SPI_TXDR8)
#define STO_SPI_TXDR8 (0x20)
#define STT_SPI_TXDR8 STIO_8_RW
#define STN_SPI_TXDR8 SPI_TXDR8
#define REG_SPI_TXDR16 st_reg(SPI_TXDR16)
#define STO_SPI_TXDR16 (0x20)
#define STT_SPI_TXDR16 STIO_16_RW
#define STN_SPI_TXDR16 SPI_TXDR16
#define REG_SPI_TXDR32 st_reg(SPI_TXDR32)
#define STO_SPI_TXDR32 (0x20)
#define STT_SPI_TXDR32 STIO_32_RW
#define STN_SPI_TXDR32 SPI_TXDR32
#define REG_SPI_RXDR8 st_reg(SPI_RXDR8)
#define STO_SPI_RXDR8 (0x30)
#define STT_SPI_RXDR8 STIO_8_RW
#define STN_SPI_RXDR8 SPI_RXDR8
#define REG_SPI_RXDR16 st_reg(SPI_RXDR16)
#define STO_SPI_RXDR16 (0x30)
#define STT_SPI_RXDR16 STIO_16_RW
#define STN_SPI_RXDR16 SPI_RXDR16
#define REG_SPI_RXDR32 st_reg(SPI_RXDR32)
#define STO_SPI_RXDR32 (0x30)
#define STT_SPI_RXDR32 STIO_32_RW
#define STN_SPI_RXDR32 SPI_RXDR32
#define REG_SPI_CRCPOLY st_reg(SPI_CRCPOLY)
#define STO_SPI_CRCPOLY (0x40)
#define STT_SPI_CRCPOLY STIO_32_RW
#define STN_SPI_CRCPOLY SPI_CRCPOLY
#define REG_SPI_TXCRC st_reg(SPI_TXCRC)
#define STO_SPI_TXCRC (0x44)
#define STT_SPI_TXCRC STIO_32_RW
#define STN_SPI_TXCRC SPI_TXCRC
#define REG_SPI_RXCRC st_reg(SPI_RXCRC)
#define STO_SPI_RXCRC (0x48)
#define STT_SPI_RXCRC STIO_32_RW
#define STN_SPI_RXCRC SPI_RXCRC
#define REG_SPI_UDRDR st_reg(SPI_UDRDR)
#define STO_SPI_UDRDR (0x4c)
#define STT_SPI_UDRDR STIO_32_RW
#define STN_SPI_UDRDR SPI_UDRDR
#define REG_SPI_I2SCFGR st_reg(SPI_I2SCFGR)
#define STO_SPI_I2SCFGR (0x50)
#define STT_SPI_I2SCFGR STIO_32_RW
#define STN_SPI_I2SCFGR SPI_I2SCFGR
#define BP_SPI_I2SCFGR_I2SDIV 16
#define BM_SPI_I2SCFGR_I2SDIV 0xff0000
#define BF_SPI_I2SCFGR_I2SDIV(v) (((v) & 0xff) << 16)
#define BFM_SPI_I2SCFGR_I2SDIV(v) BM_SPI_I2SCFGR_I2SDIV
#define BF_SPI_I2SCFGR_I2SDIV_V(e) BF_SPI_I2SCFGR_I2SDIV(BV_SPI_I2SCFGR_I2SDIV__##e)
#define BFM_SPI_I2SCFGR_I2SDIV_V(v) BM_SPI_I2SCFGR_I2SDIV
#define BP_SPI_I2SCFGR_DATLEN 8
#define BM_SPI_I2SCFGR_DATLEN 0x300
#define BV_SPI_I2SCFGR_DATLEN__16BIT 0x0
#define BV_SPI_I2SCFGR_DATLEN__24BIT 0x1
#define BV_SPI_I2SCFGR_DATLEN__32BIT 0x2
#define BF_SPI_I2SCFGR_DATLEN(v) (((v) & 0x3) << 8)
#define BFM_SPI_I2SCFGR_DATLEN(v) BM_SPI_I2SCFGR_DATLEN
#define BF_SPI_I2SCFGR_DATLEN_V(e) BF_SPI_I2SCFGR_DATLEN(BV_SPI_I2SCFGR_DATLEN__##e)
#define BFM_SPI_I2SCFGR_DATLEN_V(v) BM_SPI_I2SCFGR_DATLEN
#define BP_SPI_I2SCFGR_I2SSTD 4
#define BM_SPI_I2SCFGR_I2SSTD 0x30
#define BV_SPI_I2SCFGR_I2SSTD__I2S 0x0
#define BV_SPI_I2SCFGR_I2SSTD__MSB_JUSTIFIED 0x1
#define BV_SPI_I2SCFGR_I2SSTD__LSB_JUSTIFIED 0x2
#define BV_SPI_I2SCFGR_I2SSTD__PCM 0x3
#define BF_SPI_I2SCFGR_I2SSTD(v) (((v) & 0x3) << 4)
#define BFM_SPI_I2SCFGR_I2SSTD(v) BM_SPI_I2SCFGR_I2SSTD
#define BF_SPI_I2SCFGR_I2SSTD_V(e) BF_SPI_I2SCFGR_I2SSTD(BV_SPI_I2SCFGR_I2SSTD__##e)
#define BFM_SPI_I2SCFGR_I2SSTD_V(v) BM_SPI_I2SCFGR_I2SSTD
#define BP_SPI_I2SCFGR_I2SCFG 1
#define BM_SPI_I2SCFGR_I2SCFG 0xe
#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_TX 0x0
#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_RX 0x1
#define BV_SPI_I2SCFGR_I2SCFG__MASTER_TX 0x2
#define BV_SPI_I2SCFGR_I2SCFG__MASTER_RX 0x3
#define BV_SPI_I2SCFGR_I2SCFG__SLAVE_DUPLEX 0x4
#define BV_SPI_I2SCFGR_I2SCFG__MASTER_DUPLEX 0x5
#define BF_SPI_I2SCFGR_I2SCFG(v) (((v) & 0x7) << 1)
#define BFM_SPI_I2SCFGR_I2SCFG(v) BM_SPI_I2SCFGR_I2SCFG
#define BF_SPI_I2SCFGR_I2SCFG_V(e) BF_SPI_I2SCFGR_I2SCFG(BV_SPI_I2SCFGR_I2SCFG__##e)
#define BFM_SPI_I2SCFGR_I2SCFG_V(v) BM_SPI_I2SCFGR_I2SCFG
#define BP_SPI_I2SCFGR_MCKOE 25
#define BM_SPI_I2SCFGR_MCKOE 0x2000000
#define BF_SPI_I2SCFGR_MCKOE(v) (((v) & 0x1) << 25)
#define BFM_SPI_I2SCFGR_MCKOE(v) BM_SPI_I2SCFGR_MCKOE
#define BF_SPI_I2SCFGR_MCKOE_V(e) BF_SPI_I2SCFGR_MCKOE(BV_SPI_I2SCFGR_MCKOE__##e)
#define BFM_SPI_I2SCFGR_MCKOE_V(v) BM_SPI_I2SCFGR_MCKOE
#define BP_SPI_I2SCFGR_ODD 24
#define BM_SPI_I2SCFGR_ODD 0x1000000
#define BF_SPI_I2SCFGR_ODD(v) (((v) & 0x1) << 24)
#define BFM_SPI_I2SCFGR_ODD(v) BM_SPI_I2SCFGR_ODD
#define BF_SPI_I2SCFGR_ODD_V(e) BF_SPI_I2SCFGR_ODD(BV_SPI_I2SCFGR_ODD__##e)
#define BFM_SPI_I2SCFGR_ODD_V(v) BM_SPI_I2SCFGR_ODD
#define BP_SPI_I2SCFGR_DATFMT 14
#define BM_SPI_I2SCFGR_DATFMT 0x4000
#define BV_SPI_I2SCFGR_DATFMT__RIGHT_ALIGNED 0x0
#define BV_SPI_I2SCFGR_DATFMT__LEFT_ALIGNED 0x1
#define BF_SPI_I2SCFGR_DATFMT(v) (((v) & 0x1) << 14)
#define BFM_SPI_I2SCFGR_DATFMT(v) BM_SPI_I2SCFGR_DATFMT
#define BF_SPI_I2SCFGR_DATFMT_V(e) BF_SPI_I2SCFGR_DATFMT(BV_SPI_I2SCFGR_DATFMT__##e)
#define BFM_SPI_I2SCFGR_DATFMT_V(v) BM_SPI_I2SCFGR_DATFMT
#define BP_SPI_I2SCFGR_WSINV 13
#define BM_SPI_I2SCFGR_WSINV 0x2000
#define BF_SPI_I2SCFGR_WSINV(v) (((v) & 0x1) << 13)
#define BFM_SPI_I2SCFGR_WSINV(v) BM_SPI_I2SCFGR_WSINV
#define BF_SPI_I2SCFGR_WSINV_V(e) BF_SPI_I2SCFGR_WSINV(BV_SPI_I2SCFGR_WSINV__##e)
#define BFM_SPI_I2SCFGR_WSINV_V(v) BM_SPI_I2SCFGR_WSINV
#define BP_SPI_I2SCFGR_FIXCH 12
#define BM_SPI_I2SCFGR_FIXCH 0x1000
#define BF_SPI_I2SCFGR_FIXCH(v) (((v) & 0x1) << 12)
#define BFM_SPI_I2SCFGR_FIXCH(v) BM_SPI_I2SCFGR_FIXCH
#define BF_SPI_I2SCFGR_FIXCH_V(e) BF_SPI_I2SCFGR_FIXCH(BV_SPI_I2SCFGR_FIXCH__##e)
#define BFM_SPI_I2SCFGR_FIXCH_V(v) BM_SPI_I2SCFGR_FIXCH
#define BP_SPI_I2SCFGR_CKPOL 11
#define BM_SPI_I2SCFGR_CKPOL 0x800
#define BF_SPI_I2SCFGR_CKPOL(v) (((v) & 0x1) << 11)
#define BFM_SPI_I2SCFGR_CKPOL(v) BM_SPI_I2SCFGR_CKPOL
#define BF_SPI_I2SCFGR_CKPOL_V(e) BF_SPI_I2SCFGR_CKPOL(BV_SPI_I2SCFGR_CKPOL__##e)
#define BFM_SPI_I2SCFGR_CKPOL_V(v) BM_SPI_I2SCFGR_CKPOL
#define BP_SPI_I2SCFGR_CHLEN 10
#define BM_SPI_I2SCFGR_CHLEN 0x400
#define BV_SPI_I2SCFGR_CHLEN__16BIT 0x0
#define BV_SPI_I2SCFGR_CHLEN__32BIT 0x1
#define BF_SPI_I2SCFGR_CHLEN(v) (((v) & 0x1) << 10)
#define BFM_SPI_I2SCFGR_CHLEN(v) BM_SPI_I2SCFGR_CHLEN
#define BF_SPI_I2SCFGR_CHLEN_V(e) BF_SPI_I2SCFGR_CHLEN(BV_SPI_I2SCFGR_CHLEN__##e)
#define BFM_SPI_I2SCFGR_CHLEN_V(v) BM_SPI_I2SCFGR_CHLEN
#define BP_SPI_I2SCFGR_PCMSYNC 7
#define BM_SPI_I2SCFGR_PCMSYNC 0x80
#define BV_SPI_I2SCFGR_PCMSYNC__SHORT 0x0
#define BV_SPI_I2SCFGR_PCMSYNC__LONG 0x1
#define BF_SPI_I2SCFGR_PCMSYNC(v) (((v) & 0x1) << 7)
#define BFM_SPI_I2SCFGR_PCMSYNC(v) BM_SPI_I2SCFGR_PCMSYNC
#define BF_SPI_I2SCFGR_PCMSYNC_V(e) BF_SPI_I2SCFGR_PCMSYNC(BV_SPI_I2SCFGR_PCMSYNC__##e)
#define BFM_SPI_I2SCFGR_PCMSYNC_V(v) BM_SPI_I2SCFGR_PCMSYNC
#define BP_SPI_I2SCFGR_I2SMOD 0
#define BM_SPI_I2SCFGR_I2SMOD 0x1
#define BF_SPI_I2SCFGR_I2SMOD(v) (((v) & 0x1) << 0)
#define BFM_SPI_I2SCFGR_I2SMOD(v) BM_SPI_I2SCFGR_I2SMOD
#define BF_SPI_I2SCFGR_I2SMOD_V(e) BF_SPI_I2SCFGR_I2SMOD(BV_SPI_I2SCFGR_I2SMOD__##e)
#define BFM_SPI_I2SCFGR_I2SMOD_V(v) BM_SPI_I2SCFGR_I2SMOD
#endif /* __HEADERGEN_SPI_H__*/

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firmware/target/arm/stm32/stm32h7/syscfg.h Normal file
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/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* This file was automatically generated by headergen, DO NOT EDIT it.
* headergen version: 3.0.0
* stm32h743 version: 1.0
* stm32h743 authors: Aidan MacDonald
*
* Copyright (C) 2015 by the authors
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __HEADERGEN_SYSCFG_H__
#define __HEADERGEN_SYSCFG_H__
#include "macro.h"
#define STA_SYSCFG (0x58000400)
#define REG_SYSCFG_PWRCFG st_reg(SYSCFG_PWRCFG)
#define STA_SYSCFG_PWRCFG (0x58000400 + 0x2c)
#define STO_SYSCFG_PWRCFG (0x2c)
#define STT_SYSCFG_PWRCFG STIO_32_RW
#define STN_SYSCFG_PWRCFG SYSCFG_PWRCFG
#define BP_SYSCFG_PWRCFG_ODEN 0
#define BM_SYSCFG_PWRCFG_ODEN 0x1
#define BF_SYSCFG_PWRCFG_ODEN(v) (((v) & 0x1) << 0)
#define BFM_SYSCFG_PWRCFG_ODEN(v) BM_SYSCFG_PWRCFG_ODEN
#define BF_SYSCFG_PWRCFG_ODEN_V(e) BF_SYSCFG_PWRCFG_ODEN(BV_SYSCFG_PWRCFG_ODEN__##e)
#define BFM_SYSCFG_PWRCFG_ODEN_V(v) BM_SYSCFG_PWRCFG_ODEN
#endif /* __HEADERGEN_SYSCFG_H__*/

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name "stm32h743"
title "STM32H743"
isa "armv7-m"
version "1.0"
author "Aidan MacDonald"
node FLASH {
title "Embedded flash memory"
addr 0x52002000
reg ACR 0x00 {
fld 5 3 WRHIGHFREQ
fld 3 0 LATENCY
}
}
node PWR {
title "Power control"
addr 0x58024800
reg CR1 0x00 {
fld 18 17 ALS
bit 16 AVDEN
fld 15 14 SVOS
bit 9 FLPS
bit 8 DBP
fld 7 5 PLS
bit 4 PVDE
bit 0 LPDS
}
reg CSR1 0x04 {
bit 16 AVDO
fld 15 14 ACTVOS
bit 13 ACTVOSRDY
bit 4 PVDO
}
reg CR3 0x0c {
bit 26 USB33RDY
bit 25 USBREGEN
bit 24 USB33DEN
bit 9 VBRS
bit 8 VBE
bit 2 SCUEN
bit 1 LDOEN
bit 0 BYPASS
}
reg D3CR 0x18 {
fld 15 14 VOS { enum VOS3 1; enum VOS2 2; enum VOS1 3; }
bit 13 VOSRDY
}
}
node RCC {
title "Reset and clock control"
addr 0x58024400
reg CR 0x00 {
bit 29 PLL3RDY
bit 28 PLL3ON
bit 27 PLL2RDY
bit 26 PLL2ON
bit 25 PLL1RDY
bit 24 PLL1ON
bit 19 HSECSSON
bit 18 HSEBYP
bit 17 HSERDY
bit 16 HSEON
bit 15 D2CKRDY
bit 14 D1CKRDY
bit 13 HSI48RDY
bit 12 HSI48ON
bit 9 CSIKERON
bit 8 CSIRDY
bit 7 CSION
bit 5 HSIDIVF
fld 4 3 HSIDIV
bit 2 HSIRDY
bit 1 HSIKERON
bit 0 HSION
}
reg CFGR 0x10 {
fld 31 29 MCO2 { enum SYSCLK 0; enum PLL2P 1; enum HSE 2; enum PLL1P 3; enum CSI 4; enum LSI 5 }
fld 28 25 MCO2PRE
fld 24 22 MCO1 { enum HSI 0; enum LSE 1; enum HSE 2; enum PLL1Q 3; enum HSI48 4 }
fld 21 18 MCO1PRE
bit 15 TIMPRE
bit 14 HRTIMSEL
fld 13 8 RTCPRE
bit 7 STOPKERWUCK
bit 6 STOPWUCK
fld 5 3 SWS
fld 2 0 SW { enum HSI 0; enum CSI 1; enum HSE 2; enum PLL1P 3; }
}
reg D1CFGR 0x18 {
fld 11 8 D1CPRE
fld 6 4 D1PPRE
fld 4 0 HPRE
}
reg D2CFGR 0x1c {
fld 10 8 D2PPRE2
fld 6 4 D2PPRE1
}
reg D3CFGR 0x20 {
fld 6 4 D3PPRE
}
reg PLLCKSELR 0x28 {
fld 25 20 DIVM3
fld 17 12 DIVM2
fld 9 4 DIVM1
fld 1 0 PLLSRC { enum HSI 0; enum CSI 1; enum HSE 2; enum NONE 3; }
}
reg PLLCFGR 0x2c {
bit 24 DIVR3EN
bit 23 DIVQ3EN
bit 22 DIVP3EN
bit 21 DIVR2EN
bit 20 DIVQ2EN
bit 19 DIVP2EN
bit 18 DIVR1EN
bit 17 DIVQ1EN
bit 16 DIVP1EN
fld 11 10 PLL3RGE { enum 1_2MHZ 0; enum 2_4MHz 1; enum 4_8MHz 2; enum 8_16MHz 3; }
bit 9 PLL3VCOSEL { enum WIDE 0; enum MEDIUM 1; }
bit 8 PLL3FRACEN
fld 7 6 PLL2RGE { enum 1_2MHZ 0; enum 2_4MHz 1; enum 4_8MHz 2; enum 8_16MHz 3; }
bit 5 PLL2VCOSEL { enum WIDE 0; enum MEDIUM 1; }
bit 4 PLL2FRACEN
fld 3 2 PLL1RGE { enum 1_2MHZ 0; enum 2_4MHz 1; enum 4_8MHz 2; enum 8_16MHz 3; }
bit 1 PLL1VCOSEL { enum WIDE 0; enum MEDIUM 1; }
bit 0 PLL1FRACEN
}
reg PLLxDIVR {
instance PLL1DIVR 0x30
instance PLL2DIVR 0x38
instance PLL3DIVR 0x40
fld 30 24 DIVR
fld 22 16 DIVQ
fld 15 9 DIVP
fld 8 0 DIVN
}
reg PLLxFRACR {
instance PLL1FRACR 0x34
instance PLL2FRACR 0x3c
instance PLL3FRACR 0x44
fld 15 3 FRACN
}
reg D1CCIPR 0x4c {
fld 29 28 CKPERSEL { enum HSI 0; enum CSI 1; enum HSE 2; }
bit 16 SDMMCSEL { enum PLL1Q 0; enum PLL2R 1; }
fld 5 4 QSPISEL { enum AHB 0; enum PLL1Q 1; enum PLL2R 2; enum PER 3; }
fld 1 0 FMCSEL { enum AHB 0; enum PLL1Q 1; enum PLL2R 2; enum PER 3; }
}
reg D2CCIP1R 0x50 {
bit 31 SWPSEL { enum APB1 0; enum HSI 1; }
fld 29 28 FDCANSEL { enum HSE 0; enum PLL1Q 1; enum PLL2Q 1; }
bit 24 DFSDM1SEL { enum APB2 0; enum SYSCLK 1; }
fld 21 20 SPDIFSEL { enum PLL1Q 0; enum PLL2R 1; enum PLL3R 2; enum HSI 3; }
fld 18 16 SPI45SEL { enum APB2 0; enum PLL2Q 1; enum PLL3Q 2; enum HSI 3;
enum CSI 4; enum HSE 5; }
fld 14 12 SPI123SEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2; enum I2SCKIN 3;
enum PER 4; }
fld 8 6 SAI23SEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2; enum I2SCKIN 4;
enum PER 4; }
fld 2 0 SAI1SEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2; enum I2SCKIN 4;
enum PER 4; }
}
reg D2CCIP2R 0x54 {
fld 30 28 LPTIM1SEL { enum APB1 0; enum PLL2P 1; enum PLL3R 2;
enum LSE 3; enum LSI 4; enum PER 5; }
fld 23 22 CECSEL { enum LSE 0; enum LSI 1; enum CSI 2; }
fld 21 20 USBSEL { enum DISABLE 0; enum PLL1Q 1; enum PLL3Q 2; enum HSI48 3; }
fld 13 12 I2C123SEL { enum APB1 0; enum PLL3R 1; enum HSI 2; enum CSI 3; }
fld 9 8 RNGSEL { enum HSI 0; enum PLL1Q 1; enum LSE 2; enum LSI 3; }
fld 5 3 USART16SEL { enum APB2 0; enum PLL2Q 1; enum PLL3Q 2;
enum HSI 3; enum CSI 4; enum LSE 5; }
fld 2 0 USART234578SEL { enum APB1 0; enum PLL2Q 1; enum PLL3Q 2;
enum HSI 3; enum CSI 4; enum LSE 5; }
}
reg D3CCIPR 0x58 {
fld 30 28 SPI6SEL { enum APB4 0; enum PLL2Q 1; enum PLL3Q 2;
enum HSI 3; enum CSI 4; enum HSE 5; }
fld 26 24 SAI4BSEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2;
enum I2S_CKIN 3; enum PER 4; }
fld 23 21 SAI4ASEL { enum PLL1Q 0; enum PLL2P 1; enum PLL3P 2;
enum I2S_CKIN 3; enum PER 4; }
fld 17 16 ADCSEL { enum PLL2P 0; enum PLL3R 1; enum PER 2; }
fld 15 13 LPTIM345SEL { enum APB4 0; enum PLL2P 1; enum PLL3R 2;
enum LSE 3; enum LSI 4; enum PER 5; }
fld 12 10 LPTIM2SEL { enum APB4 0; enum PLL2P 1; enum PLL3R 2;
enum LSE 3; enum LSI 4; enum PER 5; }
fld 9 8 I2C4SEL { enum APB4 0; enum PLL3R 1; enum HSI 2; enum CSI 3; }
fld 2 0 LPUART1SEL { enum APB4 0; enum PLL2Q 1; enum PLL3Q 2;
enum HSI 3; enum CSI 4; enum LSE 5; }
}
reg BDCR 0x70 {
bit 16 BDRST
bit 15 RTCEN
fld 9 8 RTCSEL { enum NONE 0; enum LSE 1; enum LSI 2; enum HSE 3; }
bit 6 LSECSSD
bit 5 LSECSSON
fld 4 3 LSEDRV { enum LOW 0; enum MED_LOW 1; enum MED_HIGH 2; enum HIGH 3; }
bit 2 LSEBYP
bit 1 LSERDY
bit 0 LSEON
}
reg CSR 0x74 {
bit 1 LSIRDY
bit 0 LSION
}
reg AHB3EN {
instance AHB3ENR 0xd4
instance AHB3LPENR 0xfc
# note:
# - bits 8 and 28-31 exist in AHB3LPENR only
# - all other bits are common
bit 31 AXISRAMEN
bit 30 ITCMEN
bit 29 DTCM2EN
bit 28 D1DTCM1EN
bit 16 SDMMC1EN
bit 14 QSPIEN
bit 12 FMCEN
bit 8 FLASHEN
bit 5 JPEGDECEN
bit 4 DMA2DEN
bit 0 MDMAEN
}
reg AHB4EN {
instance AHB4ENR 0xe0
instance AHB4LPENR 0x108
# note:
# - bit 29 exists in AHB4LPENR only
# - bit 25 exists in AHB4ENR only
# - all other bits are common
bit 29 SRAM4EN
bit 28 BKPRAMEN
bit 25 HSEMEN
bit 24 ADC3EN
bit 21 BDMAEN
bit 19 CRCEN
bit 10 GPIOKEN
bit 9 GPIOJEN
bit 8 GPIOIEN
bit 7 GPIOHEN
bit 6 GPIOGEN
bit 5 GPIOFEN
bit 4 GPIOEEN
bit 3 GPIODEN
bit 2 GPIOCEN
bit 1 GPIOBEN
bit 0 GPIOAEN
}
reg APB3EN {
instance APB3ENR 0xe4
instance APB3LPENR 0x10c
bit 6 WWDG1EN
bit 3 LTDCEN
}
reg APB1LEN {
instance APB1LENR 0xe8
instance APB1LLPENR 0x110
bit 31 UART8EN
bit 30 UART7EN
bit 29 DAC12EN
bit 27 CECEN
bit 23 I2C3EN
bit 22 I2C2EN
bit 21 I2C1EN
bit 20 UART5EN
bit 19 UART4EN
bit 18 USART3EN
bit 17 USART2EN
bit 16 SPDIFRXEN
bit 15 SPI3EN
bit 14 SPI2EN
bit 9 LPTIM1EN
bit 8 TIM14EN
bit 7 TIM13EN
bit 6 TIM12EN
bit 5 TIM7EN
bit 4 TIM6EN
bit 3 TIM5EN
bit 2 TIM4EN
bit 1 TIM3EN
bit 0 TIM2EN
}
reg APB1HEN {
instance APB1HENR 0xec
instance APB1HLPENR 0x114
bit 8 FDCANEN
bit 5 MDIOSEN
bit 4 OPAMPEN
bit 2 SWPEN
bit 1 CRSEN
}
reg APB2EN {
instance APB2ENR 0xf0
instance APB2LPENR 0x118
bit 29 HRTIMEN
bit 28 DFSDM1EN
bit 24 SAI3EN
bit 23 SAI2EN
bit 22 SAI1EN
bit 20 SPI5EN
bit 18 TIM17EN
bit 17 TIM16EN
bit 16 TIM15EN
bit 13 SPI4EN
bit 12 SPI1EN
bit 5 USART6EN
bit 4 USART1EN
bit 1 TIM8EN
bit 0 TIM1EN
}
reg APB4EN {
instance APB4ENR 0xf4
instance APB4LPENR 0x11c
bit 21 SAI4EN
bit 16 RTCAPBEN
bit 15 VREFEN
bit 14 COMP12EN
bit 12 LPTIM5EN
bit 11 LPTIM4EN
bit 10 LPTIM3EN
bit 9 LPTIM2EN
bit 7 I2C4EN
bit 5 SPI6EN
bit 3 LPUART1EN
bit 1 SYSCFGEN
}
}
node GPIO {
title "General-purpose I/Os"
instance 0x58020000 0x400 11
reg MODER 0x00
reg OTYPER 0x04
reg OSPEEDR 0x08
reg PUPDR 0x0c
reg IDR 0x10
reg ODR 0x14
reg BSRR 0x18
reg LCKR 0x1c
reg AFRL 0x20
reg AFRH 0x24
}
node SYSCFG {
title "System configuration controller"
addr 0x58000400
reg PWRCFG 0x2c {
bit 0 ODEN
}
}
node FMC {
title "Flexible memory controller"
addr 0x52004000
reg BCR {
instance 0x000 0x8 4
bit 31 FMCEN
fld 25 24 BMAP
bit 21 WFDIS
}
reg SDCR {
instance 0x140 0x4 2
fld 14 13 RPIPE
bit 12 RBURST
fld 11 10 SDCLK
bit 9 WP
fld 8 7 CAS
bit 6 NB
fld 5 4 MWID
fld 3 2 NR
fld 1 0 NC
}
reg SDTR {
instance 0x148 0x4 2
fld 27 24 TRCD
fld 23 20 TRP
fld 19 16 TWR
fld 15 12 TRC
fld 11 8 TRAS
fld 7 4 TXSR
fld 3 0 TMRD
}
reg SDCMR 0x150 {
fld 22 9 MRD
fld 8 5 NRFS
bit 4 CTB1
bit 3 CTB2
fld 2 0 MODE
}
reg SDRTR 0x154 {
bit 14 REIE
fld 13 1 COUNT
bit 0 CRE
}
reg SDSR 0x158 {
fld 4 3 MODES2
fld 2 1 MODES1
bit 0 RE
}
}
node RTC {
title "Real time clock"
addr 0x58004000
reg TR {
instance TR 0x00
instance TSTR 0x30
bit 22 PM
fld 21 20 HT
fld 19 16 HU
fld 14 12 MNT
fld 11 8 MNU
fld 6 4 ST
fld 3 0 SU
}
reg DR {
instance DR 0x04
instance DRTR 0x34
fld 23 20 YT
fld 19 16 YU
fld 15 13 WDU
bit 12 MT
fld 11 8 MU
fld 5 4 DT
fld 3 0 DU
}
reg CR 0x08 {
bit 24 ITSE
bit 23 COE
fld 22 21 OSEL { enum DISABLED 0; enum ALARM_A 1; enum ALARM_B 2; enum WAKEUP 3; }
bit 20 POL
bit 19 COSEL
bit 18 BKP
bit 17 SUB1H
bit 16 ADD1H
bit 15 TSIE
bit 14 WUTIE
bit 13 ALRBIE
bit 12 ALRAIE
bit 11 TSE
bit 10 WUTE
bit 9 ALRBE
bit 8 ALRAE
bit 6 FMT
bit 5 BYPSHAD
bit 4 REFCKON
bit 3 TSEDGE
bit 2 0 WUCKSEL { enum RTC_16 0; enum RTC_8 1; enum RTC_4 2; enum RTC_2 3;
enum CK_SPRE 4; enum CK_SPRE_ADDWUT 6; }
}
reg ISR 0x0c {
bit 17 ITSF
bit 16 RECALPF
bit 15 TAMP3F
bit 14 TAMP2F
bit 13 TAMP1F
bit 12 TSOVF
bit 11 TSF
bit 10 WUTF
bit 9 ALRBF
bit 8 ALRAF
bit 7 INIT
bit 6 INITF
bit 5 RSF
bit 4 INITS
bit 3 SHPF
bit 2 WUTWF
bit 1 ALRBWF
bit 0 ALRAWF
}
reg PRER 0x10 {
fld 22 16 PREDIV_A
fld 14 0 PREDIV_S
}
reg WPR 0x24 {
fld 7 0 KEY { enum KEY1 0xCA; enum KEY2 0x53; }
}
reg SSR {
instance SSR 0x28
instance TSSSR 0x38
fld 15 0 SS
}
reg OR 0x4c {
bit 1 RTC_OUT_RMP
bit 0 RTC_ALARM_TYPE { enum OPEN_DRAIN 0; enum PUSH_PULL 1; }
}
reg BKPR {
instance 0x50 0x4 32
}
}
node SPI {
title "Serial peripheral interface"
instance nochild SPI1 0x40013000
instance nochild SPI2 0x40003800
instance nochild SPI3 0x40003c00
instance nochild SPI4 0x40013400
instance nochild SPI5 0x40015000
instance nochild SPI6 0x58001400
instance floating
reg CR1 0x00 {
bit 16 IO_LOCK
bit 15 TCRCINI
bit 14 RCRCINI
bit 13 CRC33_17
bit 12 SSI
bit 11 HDDIR
bit 10 CSUSP
bit 9 CSTART
bit 8 MASRX
bit 0 SPE
}
reg CR2 0x04 {
fld 31 16 TSER
fld 15 0 TSIZE
}
reg CFG1 0x08 {
fld 30 28 MBR
bit 22 CRCEN
fld 20 16 CRCSIZE
bit 15 TXDMAEN
bit 14 RXDMAEN
fld 12 11 UDRDET
fld 10 9 UDRCFG
fld 8 5 FTHLV
fld 4 0 DSIZE
}
reg CFG2 0x0c {
bit 31 AFCNTR
bit 30 SSOM
bit 29 SSOE
bit 28 SSIOP
bit 26 SSM { enum SS_PAD 0; enum SSI_BIT 1; }
bit 25 CPOL
bit 24 CPHA
bit 23 LSBFIRST
bit 22 MASTER
fld 21 19 SP { enum MOTOROLA 0; enum TI 1; }
fld 18 17 COMM { enum DUPLEX 0; enum TXONLY 1; enum RXONLY 2; enum HALF_DUPLEX 3; }
bit 15 IOSWP
fld 7 4 MIDI
fld 3 0 MSSI
}
reg IER 0x10 {
bit 10 TSERFIE
bit 9 MODFIE
bit 8 TIFREIE
bit 7 CRCEIE
bit 6 OVRIE
bit 5 UDRIE
bit 4 TXTFIE
bit 3 EOTIE
bit 2 DXPIE
bit 1 TXPIE
bit 0 RXPIE
}
reg SR 0x14 {
fld 31 16 CTSIZE
bit 15 RXWNE
fld 14 13 RXPLVL
bit 12 TXC
bit 11 SUSP
bit 10 TSERF
bit 9 MODF
bit 8 TIFRE
bit 7 CRCE
bit 6 OVR
bit 5 UDR
bit 4 TXTF
bit 3 EOT
bit 2 DXP
bit 1 TXP
bit 0 RXP
}
reg IFCR 0x18 {
bit 11 SUSPC
bit 10 TSERFC
bit 9 MODFC
bit 8 TIFREC
bit 7 CRCEC
bit 6 OVRC
bit 5 UDRC
bit 4 TXTFC
bit 3 EOTC
}
reg 8 TXDR8 0x20
reg 16 TXDR16 0x20
reg 32 TXDR32 0x20
reg 8 RXDR8 0x30
reg 16 RXDR16 0x30
reg 32 RXDR32 0x30
reg CRCPOLY 0x40
reg TXCRC 0x44
reg RXCRC 0x48
reg UDRDR 0x4c
reg I2SCFGR 0x50 {
bit 25 MCKOE
bit 24 ODD
fld 23 16 I2SDIV
bit 14 DATFMT { enum RIGHT_ALIGNED 0; enum LEFT_ALIGNED 1; }
bit 13 WSINV
bit 12 FIXCH
bit 11 CKPOL
bit 10 CHLEN { enum 16BIT 0; enum 32BIT 1; }
fld 9 8 DATLEN { enum 16BIT 0; enum 24BIT 1; enum 32BIT 2; }
bit 7 PCMSYNC { enum SHORT 0; enum LONG 1; }
fld 5 4 I2SSTD { enum I2S 0; enum MSB_JUSTIFIED 1; enum LSB_JUSTIFIED 2; enum PCM 3; }
fld 3 1 I2SCFG { enum SLAVE_TX 0; enum SLAVE_RX 1;
enum MASTER_TX 2; enum MASTER_RX 3;
enum SLAVE_DUPLEX 4; enum MASTER_DUPLEX 5; }
bit 0 I2SMOD
}
}