- Use unsigned bitfields in 'lcd_tgt_config'
- Set DTIMES when using an 8-bit bus width
- Allow using DMA big-endian mode
- Provide an #ifdef to avoid stopping DMA in the middle of a frame
- Correctly #ifdef LCD sleep code when target does not implement it
Change-Id: I327c6b05223638b876d5ab62cb6e48f82e6d5fa5
- Change busy loop to wait on the timer flag instead of hoping to
catch the timer at exactly the right moment... unsurprisingly,
that did not work well with higher frequency PWM outputs.
- Put GPIO data into a dedicated const array.
Change-Id: I2a920ed265c192da197a18c7242f3205d11636d3
The old name was a bit misleading. AXP173 is sort of the lowest common
denominator of a series of related chips. The M3K uses an AXP192 which
has a few extra features vs. the AXP173.
New voltage regulator stuff was added for the sake of the Shanling Q1
native port (that player also uses an AXP192).
Change-Id: Id0c162c23094bb03d13fae2d6c332e3047968d6e
- Drop obsolete NAND patch script (it's simpler to use 'dd' directly)
- Remove an outdated comment
- Fix missing 'void' in a function definition
- Reset the poweroff timer when we poke the backlight
Change-Id: I752624386f30ac95f41a731d2b6be837e12275a9
Some audiohw API calls are shared between playback and recording,
eg. frequency settings. Implementing these in the DAC driver won't
work for the M3K, as it uses a separate codec for microphone input.
Change-Id: Ieb0a267f8a81b9e2bbf0bbca951c5778f8dcd203
I think this covers everything now, although some fields are missing
enum values. Those can be added in if and when they are needed.
Change-Id: Ib1a94ba9c9a5949b6a038f8c1a49786823fae58f
- Add support for skip and seek while the player is locked.
(Thanks to @bahus for the suggestion)
- Fix touch zones because the down button zone ended up being
a lot smaller than expected due to the touchpad's wonkiness.
Also added a visual display of the touchpad to its debug menu.
- Fixes the pictureflow keymap because it was mostly unusable.
Change-Id: Ic0da4f8df3613ff7828ce1cb940ed9e77ada3281
SPL and UCL-compressed bootloader are now packed into one output,
bootloader.m3k, eliminating the separate SPL build phase.
The Rockbox bootloader now has a recovery menu, accessible by
holding VOL+ when booting, that lets you back up, restore, and
update the bootloader from the device.
Change-Id: I642c6e5fb83587a013ab2fbfd1adab439561ced2
- Removed unnecessary layers of generic code
- Software ECC is gone since we don't need it now (and maybe not ever)
- Removed bounce buffering, so callers must now align buffers
Change-Id: I33fbac9d9d12a4657980b8618c7d62bfa91e2ea0
This overwrote the first 2 instructions of crt0 in the bootloader!
I'm really not sure how this *didn't* cause a fatal exception.
This address isn't special as far as I know, so just move it to the
TCSM by making it a static variable.
Change-Id: I58e1486804aeb2b68325e8de2aa1874c97abef19
The abiflags data is only used to communicate ABI information to a
program loader -- you can see what info is stored with readelf -A.
Dropping it shaves 24 bytes off of every binary (including plugins).
Change-Id: Iae78eeffe5c840ff67717707fb94821d24aac8ec
There's absolutely no way for gpio_config() to get called from two
different threads due to the co-operative threading model, and it
is unsafe to call from IRQ context no matter what we do.
Change-Id: I58f7d1f68c7a414610bb020e26b774cb1015a3b0
Using a macro to put each function in its own .icode-based section
allows us to put the functions in IRAM _and_ have linker GC. This
removes a troublesome #ifdef BOOTLOADER_SPL on the X1000 target.
Change-Id: Ia7b59778f5c36b7970dee4280547e434a1f4fc5a
This only required a minor patch to the usb-designware driver due
to DMA requiring physical addresses -- on the X1000, these differ
from virtual addresses so we have to do the usual conversion.
Both the mass storage and HID drivers work, but there are a few
issues so this can't be considered 100% stable yet.
- Mass storage might not be detected properly on insertion,
and USB has to be replugged before it shows up
- HID driver may occasionally panic or hang the machine
Change-Id: Ia3ce7591d5928ec7cbca7953abfef01bdbd873ef
- Added register names to reduce usage of magic numbers
- Added function to control max charging current, needed for USB
- Corrected comment about axp173, since FiiO M3K has an axp192
Change-Id: I6604ce8d44e5a2ee84061cf042d17ccc4734ac57
After conducting some simplistic tests, I found that the power usage
did not appear to be affected by the CPU frequency.
I tested by playing back a 44.1 KHz FLAC file on single track repeat,
and measured current with the AXP173's battery discharge current ADC.
The button and LCD backlights were set to always on. Headphones were
unplugged and the volume was muted to eliminate any influence from
the headphone amp.
On average the current usage was between 78-81 mA at 1008 MHz, 252 MHz,
and 112 MHz. If anything, 1008 MHz drew _less_ current than the lower
frequencies, by about 1-3 mA.
A possible explanation for this, assuming it's not just a bias of the
test, is that the CPU idle state saves so much power that it's better
to maximize the real time that the CPU spends idling. More systematic
testing is needed to confirm this.
Change-Id: I527473e8c4c12bc1e94f8d4e849fecc108022abe
There's no point including this in normal builds: the stats are not
used for anything, they are not really of interest to anyone except
developers, and add a small overhead to the kernel tick.
Change-Id: I1b4f67cc62d11d634a8cec279dca513dd10eea96
Initializing the clocks in the SPL brings Rockbox in line with
how the FiiO M3K's original SPL works. It's likely other X1000
devices do this too.
There was a logic error in the previous setup: the code falsely
assumed that DDR memory would always be running from MPLL, but
it would be switched to APLL by the bootloader. Rockbox would
then try to re-init APLL, albeit with the same parameters. Maybe
this was the cause of the boot hang on some units.
Change-Id: I64064585e491bbdf1e95fe9428c91a9314f2a917
What we really want is to avoid any interrupts being generated
before the drivers which handle them are properly initialized.
Intead of trashing all GPIOs, search for the problem pins and
fix them, leaving the others alone.
This fixes the M3K's button light flickering on boot and should
stop the M3K from entering a potentially confusing "dead" state
where all the lights are off but the CPU is still on.
Change-Id: I13a6da0f0950190396bff5d6e8c343c668e8fea1
SPL is now designed so core X1000 code is in control of the boot,
under the reasonable assumption that the device boots from flash.
It should not be too hard to adapt to other X1000 ports.
The biggest functional change is that the SPL can now read/write
the flash, under the control of a host computer. The SPL relies
on the boot ROM for USB communication, so the host has to execute
the SPL multiple times following a protocol.
Change-Id: I3ffaa00e4bf191e043c9df0e2e64d15193ff42c9
The X3's line out is a bit hot, at ~4.3Vpp, so allow it to be backed off.
(On my X3, backing it off to -6dB brings Vpp down to ~3.4V)
Change-Id: Iea38ef1c6a1b183d0f8fb4eaf2bf9ed6b350a532
- Proper error codes are now returned from all functions. These codes will
be used by a host-side flash tool for error reporting.
- nand_erase_block() was replaced by nand_erase_bytes(). The caller can't
know how big an eraseblock is with the current API, so next best thing
is to verify the correct alignment inside the call and reject the erase
if it isn't properly aligned.
- Fixed typo in nandcmd_block_erase() which would cause an SFC error to be
interpreted as success. Yikes.
Change-Id: Id4ac9b44fa7fc2fcb81ff19ba730df78457c0383
Enable its use in the jz47xx MIPS targets.
(accidently committed g#3249 before making these changes)
Change-Id: I1791946f632901f0c7a94b04b009671aa0d71717
Previously these were placed in DRAM, which is overwritten by RoLo
when it loads a new image, but RoLo must call commit_discard_idcache()
after loading the image.
Change-Id: I5dcc4ca711b774166f83c668695edbcabfab2604
The filesystem API often passes in unaligned receive buffers, and some
code (eg BMP reader) processes data in-place, leading to data loss when
we dropped the cache.
(And document exactly what we're doing, so we don't go through this again
at $future_date)
Change-Id: If47a7f2148a5a1a43777f0bd3be1bdfe8239e91e
In fixing the original bug I tried to optimize discard_dcache_range()
to minimize writeback and inadvertently introduced a second bug, which
typically ends in a TLB refill panic.
It occurs only if the range fits within one cache line, and when both
the start and end of the range are not aligned to a cache line. This
causes ptr to be incremented and end to be decremented, so ptr > end,
and the loop can't terminate.
Change-Id: Ibaac072f1369268d3327d534ad08ef9dcee3db65
- The range-based cache operations on MIPS were broken and only worked
properly when BOTH the address and size were multiples of the cache
line size. If this was not the case, the last cache line of the range
would not be touched!
Fix is to align start/end pointers to cache lines before iterating.
- To my knowledge all MIPS processors have a cache, so I enabled
HAVE_CPU_CACHE_ALIGN by default. This also allows mmu-mips.c to use
the CACHEALIGN_UP/DOWN macros.
- Make jz4760/system-target.h define its cache line size properly.
Change-Id: I1fcd04a59791daa233b9699f04d5ac1cc6bacee7
* pcm_get_bytes_remaining()
* pcm_calculate_peaks()
* pcm_get_peak_buffer()
Nothing in-tree uses these at all (except for the lua plugin wrapper)
Change-Id: I971b7beed6760250c8b1ce58f401a601e1e2d585
Nothing in the core has used it for some time. It's exported to the
plugin API but the last plugins to use it were switched to the mixer API
back in 2011.
This allows us to get rid of pcm_play_dma_pause() from all audio drivers
Change-Id: Ic3fa02592316f84963e41d792d1cabb436d1ff6b
Whether or not this is correct depends on how the source material was
mastered, digitized, and/or encoded. There is no setting appropriate
for everything.
Eventually I'd like to make this configurable, but I'd want to have it
shared with more than one target first.
Change-Id: I20a0eff4b3dc2517c33db49d4f72e85bf81d1ca6
Note: PCM mix buffer sizes are _way_ too small for these high bitrates
(We really need to make the mixer stuff use dynamic buffer sizes based
on the bitrate. Maybe pre-allocate a max size based on upper bitrate limit,
but use only part of it at lower bitrates? So we can have sane latency..)
Change-Id: Id7b4afd73dba7f1ffb84b2e1c016859fae5d6835
Can be disabled at runtime by setting hold switch.
Boosts sysbench sequential write performance by 34-58%
Change-Id: I060c9d7dddc1b448f18aa46af8f8aff046e07843
* DMA Bulk IN (ie our TX) results in sequential transfers 33-68% faster.
* DMA Bulk OUT (ie RX) is mostly stripped out due to complete brokenness.
* Interrupt and control endpoints remain PIO-driven.
Other improvements:
1) Use consistent endpoint references (no magic numbers)
2) Greatly enhanced logging
3) DMA support can be compiled out completely
4) Setting lockswitch will disable all DMA operations at runtime
5) Much more robust error checking and recovery
Change-Id: I57b82e655e55ced0dfe289e379b0b61d8fe443b4
