Aidan MacDonald 01d1eb4258 FiiO M3K/X1000: Do system clock initialization in the SPL ... Initializing the clocks in the SPL brings Rockbox in line with how the FiiO M3K's original SPL works. It's likely other X1000 devices do this too. There was a logic error in the previous setup: the code falsely assumed that DDR memory would always be running from MPLL, but it would be switched to APLL by the bootloader. Rockbox would then try to re-init APLL, albeit with the same parameters. Maybe this was the cause of the boot hang on some units. Change-Id: I64064585e491bbdf1e95fe9428c91a9314f2a917		2021-04-17 20:24:07 +00:00
..
ingenic_jz47xx	xduoox3: Global volume_limit now applies to the line output as well	2021-04-09 15:54:04 -04:00
ingenic_x1000	FiiO M3K/X1000: Do system clock initialization in the SPL	2021-04-17 20:24:07 +00:00
mipsr2-endian.h	New port: FiiO M3K on bare metal	2021-03-28 00:01:37 +00:00
mmu-mips.c	New port: FiiO M3K on bare metal	2021-03-28 00:01:37 +00:00
mmu-mips.h	Move MIPS cache management functions to IRAM	2021-03-09 20:04:30 +00:00