To keep the code size small, this hardcodes the D-Cache line
size and set/way information (which is defined by the target
and should be fixed for a given CPU) and assumes there is only
one level of cache.
Change-Id: Ia6d0e6a87b5dbfc6c39bda83b58461ed8767edf6
Cortex-M processors don't have an MMU, but can still have caches
that need software management, so on those platforms we don't want
to include the MMU related functions.
While here, remove an outdated section of a comment referring to
deprecated cache maintenance functions which no longer exist.
Change-Id: I6f0fe694560bdee25ed7c69a846bf46e3e544cb1
This is an internal macro which is only used if has_sct()
is set by the generator, so don't generate it if we don't
need to.
Change-Id: I7ad51ad34ecabd833b84a270b5046e77131dcb41
When registers have lot of 1- and 2-bit fields it's possible
to exceed the 13 argument limit. Usually this only shows up
when programming a configuration register, but it's annoying
to have to split up the write. 20 arguments should be enough
to avoid that.
Change-Id: I6240fae4a51ae14600afcfb8a4e3f1e983cbffa6
Add a relative version of the register/field read/write operations
which takes a base address (which may be a void pointer or integer)
and computes the register address using offsets.
Change-Id: I7c012192e67adcd675a0fc1975ca4b16ed87bcac
Floating instances don't have an address and will only generate
child nodes and registers with offsets. The 'nochild' flag will
disable generating the children for a node but will generate the
node's own address, which can be used to generate base addresses.
Change-Id: Ib1014de94531436d5708db46aa684741e7740ace
Register offsets are defined as the address of the register minus
the address of the parent node. If enabled by the generator, these
will be emitted alongside defines for the node base addresses.
This allows the base address to be stored in a variable, and the
offset can be used to access registers relative to the base.
Change-Id: I15576aeb2945293a259007da7f00a26055f4d0f0
sample_to_chunk last value was ignored in some cases leading to invalid sample value in lookup_table.
Fixes FS#13600
Change-Id: I8f066966e15c384d3185f689b68a2cc2a3abad1d
Instead of 'this phrase missing entirely [...]' followed by the
verbatim phrase copied from English, instead the message now
reads 'the 'PHRASE_ID' is missing entirely [...]. This allows
the warning to be self-contained.
Change-Id: I413c29e0c1f6616e74d875d197b34c4724330d67
It may make sense to only show these in the
file browser, where you'd expect to do more
general file operations involving other folders.
Change-Id: I008569d2017811ee54b4449acb30359843f35294
Cortex-M7 support was added in GCC 5, while GCC 4.9 only
supports the M4. The instruction set is almost identical
between both processors; the only difference is that the
M7 supports double-precision floating point and the M4
doesn't.
Since Rockbox currently doesn't use the FPU, building M7
targets as M4 works fine.
Change-Id: I5880d6e81a85fa9b3e16e08d57e7955b4493df0b
Some assembly routines don't work on Thumb as-is. For now
just disable these so the codecs compile.
Affected codecs:
- libflac
- libmad
- libspeex
- libtta
- libwavpack
A few DSP routines need to be disabled for the same reason:
- crossfeed_process
- crossfeed_meier_process
- resample_hermite
- filter_process
- sample_output_stereo
Change-Id: I277e0719652096745a19a7e2b597eff32d8e1553
We can't use Operand2 with register based shifts on ARMv7-M as it
isn't supported in the Thumb encoding. Instead, perform the shift
separately.
Change-Id: Ie96aa0a565e98bbca724dffc2ffc6d64fdb5d7c3
GAS warns about unpredictable behavior of "ldr sp, [a1], #4"
that exists on Cortex-M3 (errata 752419) but this warning is
incorrectly issued on other cores too (eg, Cortex-M7).
Since the fix is just one extra instruction we may as well
apply the workaround for all Cortex-M targets.
Change-Id: I0c2aa46837f776d67d0236b627af1572aa5ab307
Even though ARMv7-M has a hardware divider, 64-bit division is
handled in software and needs a div0 handler. The libgcc routines
call __aeabi_{i,l}div0 so we alias those to __div0.
Change-Id: I5152c43d39e25e03f31404753f13978a614aca06
Currently, only the development bootloader can be built successfully.
This is a part of the large iPod Nano 3G and iPod Nano 4G support patch.
Credit: Cástor Muñoz <cmvidal@gmail.com>
Change-Id: I74ea0da999ddb1d8ce5d0f5434141b3f0b5f7448
Currently, only a bootloader can be built successfully. The development bootloader is functional, it enables further progress on the port.
This is a part of the large iPod Nano 3G and iPod Nano 4G support patch.
Credit: Cástor Muñoz <cmvidal@gmail.com>
Change-Id: Idf85e42334b0e0ae36f9ed273e2940d5d7736e34
M-profile cores manage interrupts differently from classic cores
and lack the FIQ. Split the interrupt management parts out into
separate headers but keep the endian swapping routines (which are
not profile-dependent) in the common system-arm header.
The initial part of the vector table is common to all Cortex-M
CPUs and is intended to be included by the target linker script,
with the vendor-specific part of the vector table appended to it.
Change-Id: Ib2ad5b9dc41db27940e39033cfef4308923db66d
On Cortex-M we can just return SP directly, which will return
PSP/MSP depending on the current processor mode.
Note that unwarminder doesn't handle Cortex-M exception frames
yet, so a panic from an interrupt handler will currently stop
at the exception boundary.
Change-Id: I8818126c065c896d781bd52b877965a4094dee2a
GCC cannot compile the existing assembly here on ARMv7-M,
claiming impossible constraints. It is actually possible to
compile if the input arguments (addresses and sizes) are
first moved to a high register so as not to conflict with
the use of r0-r7 in ldm/stm -- this is exactly what GCC does
for ARMv6, but it won't do it on ARMv7-M for some reason.
We can get a result similar to the ARMv6 code by manually
moving the inputs into temporaries, but the generated code
is a actually a bit smaller on ARMv7-M if the r0-r7 block is
shifted up to r3-r10. This only works since ARMv7-M supports
the 32-bit Thumb encoding -- 16-bit Thumb can't represent an
ldm/stm instruction of this type.
It's worth #ifdef'ing the code because although the ARMv7-M
version works on ARMv6 too, it spills a lot of registers on
the stack even though register use is mostly similar.
Change-Id: I9bc8b5c76e198aecfd0a0e7a2158b1c00f82c4df
On ARMv7-M, stm/ldm instructions can't include SP, so we must
load and store that separately. This changes the order of
registers in the context struct, but it doesn't seem to be
accessed anywhere else so this shouldn't cause any problems.
Change-Id: Ie1cd23272f23384e030f51f0b76739624fa7332b
Commit 1fb906500a ("x1000: LCD DMA fix") caused a regression
on the Q1 by breaking the LCD_X1000_DMA_WAIT_FOR_FRAME logic,
since the wrong branch of lcd_wait_frame() was taken.
Change-Id: Icb44335f506a1a691280de8219188526bb11468f
All the X1000 targets use "fast" sleep, as opposed to the normal
HAVE_LCD_SLEEP define which creates a user-configurable option.
Remove the ifdefs to make the code a bit easier to read.
Change-Id: Ibb80c92a8e23191651fee61fc8cf6f4e4fac8750
Looks like they were always off-by-one, so the wrong functions have been used to rectify this bug. This is now properly fixed.
No changes to the ipodnano2g binaries (bootloader, rockbox)
Change-Id: I19fe1b89f9e5d722f7e877d60f68fc3275c3642a
This makes these files compileable, or in some cases less
broken, on Cortex-M targets.
In lcd-16bit.c, newer versions of GAS complain about the
infix condition codes so we use the suffix form instead,
which requires unified syntax to compile on GCC 4.9.
Change-Id: If45166d3fc83d64c692cbb331096a966397aa9e9
ARMv7-M has hardware division, so it doesn't require __div0
or any support functions for 32-bit division.
Change-Id: I840683a1a77d737f378899ca4bcf858216b81014
Add some logic to detect classic and M-profile cores, and make
this info available to the build system. All existing targets
are classic profile.
Change-Id: I07bfcd418bcaa6297b9bbf889fc189f167147428
When the database isn't loaded into RAM,
or the "quick" load setting is enabled,
filenames for tracks must be retrieved
from disk.
With a single track selected, this
can cause a delay before its context
menu is displayed.
Since filenames are only needed after the
user has selected something from the menu,
it makes sense to defer retrieval until
disk access becomes inevitable.
Change-Id: I72b57eff3102b50f3e19441119e20aad903b1f2b
Temporarily enable icons for required lists. Probably not a proper fix but a simple workaround.
Fixes FS#13574
Change-Id: I011a80e2a9f03019927b32e92cd5a35275c051e1
...Its coverage is below the 80% threshold. If anyone complains, they
can help improve the translation coverage first.
Change-Id: I0201497ec1209a7d125ac99ec45de6e2a9e41098
