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firmware: refactor CACHEALIGN_BITS/SIZE defines

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Mostly motivated by PP needing CACHEALIGN_SIZE in linker
scripts, which can't include system.h, so move these to
cpu.h instead. Also gets rid of the default 32 byte line
size that was used if the target didn't define alignment
itself. RK24xx, DM320, and JZ4740 were missing this but
have been confirmed (from datasheets) to use 32-byte cache
lines.

Add checks to make sure the macros are appropriately
(un)defined based on the HAVE_CPU_CACHE_ALIGN define,
and make sure their values are consistent when they
are defined.

Disable HAVE_CPU_CACHE_ALIGN for hosted targets since it
arguably doesn't matter if there's a cache, if we aren't
responsible for cache maintenance.

A few files in rbcodec use CACHEALIGN_SIZE, but these
can be converted to MEM_ALIGN_SIZE, which is identical
to CACHEALIGN_SIZE if the latter is defined. On other
targets, it aligns to at least sizeof(intptr_t).

Change-Id: If8cf8f6ec327dc3732f4cd5022a858546b9e63d6
This commit is contained in:
Aidan MacDonald 2026-02-05 15:17:15 +00:00
parent e61bf40542
commit 7eeb4e4302
23 changed files with 83 additions and 86 deletions
Download patch file Download diff file Expand all files Collapse all files

4
apps/codecs.c
View file

@ -159,7 +159,7 @@ void codec_get_full_path(char *path, const char *codec_root_fn)
CODEC_EXTENSION, codec_root_fn);
}
/* Returns pointer to and size of free codec RAM. Aligns to CACHEALIGN_SIZE. */
/* Returns pointer to and size of free codec RAM. Aligns to MEM_ALIGN_SIZE. */
void *codec_get_buffer_callback(size_t *size)
{
void *buf = &codecbuf[codec_size];
@ -169,7 +169,7 @@ void *codec_get_buffer_callback(size_t *size)
return NULL;
*size = s;
ALIGN_BUFFER(buf, *size, CACHEALIGN_SIZE);
ALIGN_BUFFER(buf, *size, MEM_ALIGN_SIZE);
return buf;
}

1
apps/plugins/plugin.lds
View file

@ -21,7 +21,6 @@ OUTPUT_FORMAT(elf32-littlemips)
#else
#define NOCACHE_BASE 0x28000000
#endif /* CPU_* */
#define CACHEALIGN_SIZE 16
#endif /* CPU_PP */
#if CONFIG_CPU==IMX31L

1
firmware/export/as3525.h
View file

@ -21,6 +21,7 @@
#define __AS3525_H__
#define CACHEALIGN_BITS (5)
#define CACHEALIGN_SIZE (32)
#define UART_CHANNELS 1

72
firmware/export/cpu.h
View file

@ -25,60 +25,60 @@
#if CONFIG_CPU == MCF5249
#include "mcf5249.h"
#endif
#if CONFIG_CPU == MCF5250
#elif CONFIG_CPU == MCF5250
#include "mcf5250.h"
#endif
#if (CONFIG_CPU == PP5020) || (CONFIG_CPU == PP5022)
#elif (CONFIG_CPU == PP5020) || (CONFIG_CPU == PP5022)
#include "pp5020.h"
#endif
#if CONFIG_CPU == PP5002
#elif CONFIG_CPU == PP5002
#include "pp5002.h"
#endif
#if CONFIG_CPU == PP5024
#elif CONFIG_CPU == PP5024
#include "pp5024.h"
#endif
#if CONFIG_CPU == PP6100
#elif CONFIG_CPU == PP6100
#include "pp6100.h"
#endif
#if CONFIG_CPU == S3C2440
#elif CONFIG_CPU == S3C2440
#include "s3c2440.h"
#endif
#if CONFIG_CPU == DM320
#elif CONFIG_CPU == DM320
#include "dm320.h"
#endif
#if CONFIG_CPU == IMX31L
#elif CONFIG_CPU == IMX31L
#include "imx31l.h"
#endif
#ifdef CPU_TCC780X
#elif defined(CPU_TCC780X)
#include "tcc780x.h"
#endif
#ifdef CPU_S5L87XX
#elif defined(CPU_S5L87XX)
#include "s5l87xx.h"
#endif
#if CONFIG_CPU == JZ4732
#elif CONFIG_CPU == JZ4732
#include "jz4740.h"
#endif
#if CONFIG_CPU == JZ4760B
#elif CONFIG_CPU == JZ4760B
#include "jz4760b.h"
#endif
#if CONFIG_CPU == AS3525
#elif CONFIG_CPU == AS3525
#include "as3525.h"
#endif
#if CONFIG_CPU == AS3525v2
#elif CONFIG_CPU == AS3525v2
#include "as3525v2.h"
#endif
#if CONFIG_CPU == IMX233
#elif CONFIG_CPU == IMX233
#include "imx233.h"
#endif
#if CONFIG_CPU == RK27XX
#elif CONFIG_CPU == RK27XX
#include "rk27xx.h"
#endif
#if CONFIG_CPU == X1000
#elif CONFIG_CPU == X1000
#include "x1000.h"
#endif
#if CONFIG_CPU == STM32H743
#elif CONFIG_CPU == STM32H743
#include "stm32h743.h"
#endif
#if (CONFIG_PLATFORM & PLATFORM_NATIVE) && (defined(CPU_ARM) || defined(CPU_MIPS))
# define HAVE_CPU_CACHE_ALIGN
#endif
#if defined(HAVE_CPU_CACHE_ALIGN)
# if !defined(CACHEALIGN_BITS)
# error "CPU header must define CACHEALIGN_BITS"
# elif !defined(CACHEALIGN_SIZE)
# error "CPU header must define CACHEALIGN_SIZE"
# elif CACHEALIGN_SIZE != (1u << CACHEALIGN_BITS)
# error "CACHEALIGN_SIZE and CACHEALIGN_BITS are inconsistent"
# endif
#else
# if defined(CACHEALIGN_BITS) && defined(CACHEALIGN_SIZE)
# error "CACHEALIGN_BITS and CACHEALIGN_SIZE must not be defined for targets with no CPU cache"
# endif
#endif
#endif /* __CPU_H */

4
firmware/export/dm320.h
View file

@ -36,6 +36,10 @@ extern unsigned long _lcdbuf2;
extern unsigned long _ttbstart;
#endif
/* See https://www.heyrick.co.uk/blog/files/datasheets/tms320dm320part1.pdf */
#define CACHEALIGN_BITS 5
#define CACHEALIGN_SIZE 32
#define TTB_BASE_ADDR (_ttbstart) /* End of memory */
#define FRAME ((short *) (&_lcdbuf)) /* Right after TTB */
#ifdef MROBE_500

3
firmware/export/jz4740.h
View file

@ -40,6 +40,9 @@
#ifndef __JZ4740_H__
#define __JZ4740_H__
#define CACHEALIGN_BITS (5)
#define CACHEALIGN_SIZE (32)
#ifndef __ASSEMBLER__
#define REG8(addr) (*(volatile unsigned char *)(addr))

3
firmware/export/jz4760b.h
View file

@ -37,6 +37,9 @@
#ifndef __JZ4760B_H__
#define __JZ4760B_H__
#define CACHEALIGN_BITS (5)
#define CACHEALIGN_SIZE (32)
#if defined(__ASSEMBLER__)
#ifndef __MIPS_ASSEMBLER
#define __MIPS_ASSEMBLER

1
firmware/export/pp5002.h
View file

@ -24,6 +24,7 @@
/* Much info gleaned and/or copied from the iPodLinux project. */
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
#define CACHEALIGN_SIZE (16)
#define DRAM_START 0x28000000

1
firmware/export/pp5020.h
View file

@ -24,6 +24,7 @@
/* All info gleaned and/or copied from the iPodLinux project. */
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
#define CACHEALIGN_SIZE (16)
/* PCM addresses for obtaining buffers will be what DMA is using (physical) */
#define HAVE_PCM_DMA_ADDRESS

4
firmware/export/rk27xx.h
View file

@ -1,3 +1,7 @@
/* See https://rockchip.fr/Rockchip%20RK27xx%20TRM%20V1.1.pdf */
#define CACHEALIGN_BITS 5
#define CACHEALIGN_SIZE 32
/* ARM part only for now */
#define AHB_SRAM 0x00000000

1
firmware/export/s3c2440.h
View file

@ -22,6 +22,7 @@
#define __S3C2440_H__
#define CACHEALIGN_BITS (5)
#define CACHEALIGN_SIZE (32)
#define LCD_BUFFER_SIZE (320*240*2)
#define TTB_SIZE (0x4000)

2
firmware/export/s5l87xx.h
View file

@ -32,8 +32,10 @@
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
#define CACHEALIGN_SIZE (16)
#elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
#define CACHEALIGN_SIZE (32)
#endif
#if CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720

1
firmware/export/stm32h743.h
View file

@ -25,6 +25,7 @@
#define CACHE_SIZE (16 * 1024)
#define CACHEALIGN_BITS 5
#define CACHEALIGN_SIZE 32
#define DCACHE_SIZE CACHE_SIZE
#define DCACHE_WAYS 0x4

30
firmware/export/system.h
View file

@ -258,17 +258,6 @@ static inline void cpu_boost_unlock(void)
#define DISABLE_INTERRUPTS HIGHEST_IRQ_LEVEL
#endif
/* Define this, if the CPU may take advantage of cache aligment. Is enabled
* for all ARM CPUs. */
#ifdef CPU_ARM
#define HAVE_CPU_CACHE_ALIGN
#define MIN_STACK_ALIGN 8
#endif
#ifdef CPU_MIPS
#define HAVE_CPU_CACHE_ALIGN
#endif
/* Define this if target has support for generating backtraces */
#if defined(CPU_ARM) || \
(defined(CPU_MIPS) && (CONFIG_PLATFORM & PLATFORM_NATIVE))
@ -277,22 +266,13 @@ static inline void cpu_boost_unlock(void)
#endif
#endif
#ifndef MIN_STACK_ALIGN
#define MIN_STACK_ALIGN (sizeof (uintptr_t))
/* ARM ABIs generally require 8-byte stack alignment */
#ifdef CPU_ARM
#define MIN_STACK_ALIGN 8
#endif
/* Calculate CACHEALIGN_SIZE from CACHEALIGN_BITS */
#ifdef CACHEALIGN_SIZE
/* undefine, if defined. always calculate from CACHEALIGN_BITS */
#undef CACHEALIGN_SIZE
#endif
#ifdef CACHEALIGN_BITS
/* CACHEALIGN_SIZE = 2 ^ CACHEALIGN_BITS */
#define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS)
#else
/* FIXME: set to maximum known cache alignment of supported CPUs */
#define CACHEALIGN_BITS 5
#define CACHEALIGN_SIZE 32
#ifndef MIN_STACK_ALIGN
#define MIN_STACK_ALIGN (sizeof (uintptr_t))
#endif
#ifdef HAVE_CPU_CACHE_ALIGN

1
firmware/export/tcc780x.h
View file

@ -22,6 +22,7 @@
#define __TCC780X_H__
#define CACHEALIGN_BITS (5)
#define CACHEALIGN_SIZE (32)
#define TTB_SIZE (0x4000)
/* must be 16Kb (0x4000) aligned */

1
firmware/export/x1000.h
View file

@ -119,6 +119,7 @@
/* CPU cache parameters */
#define CACHEALIGN_BITS 5
#define CACHEALIGN_SIZE 32
#define CACHE_SIZE (16 * 1024)
#endif /* __X1000_H__ */

5
firmware/target/arm/pp/app-pp.lds
View file

@ -1,3 +1,6 @@
#define __ASSEMBLER__
#include "cpu.h"
/* Will have been included from app.lds */
ENTRY(start)
@ -20,8 +23,6 @@ STARTUP(target/arm/pp/crt0-pp.o)
#define NOCACHE_BASE 0x28000000
#endif
#define CACHEALIGN_SIZE 16
/* End of the audio buffer, where the codec buffer starts */
#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)

5
firmware/target/arm/pp/boot-pp502x-bl-usb.lds
View file

@ -1,3 +1,6 @@
#define __ASSEMBLER__
#include "cpu.h"
/* Will have been included from boot.lds */
ENTRY(start)
OUTPUT_FORMAT(elf32-littlearm)
@ -15,8 +18,6 @@ STARTUP(target/arm/pp/crt0-pp502x-bl-usb.o)
#define FLASHORIG 0x001f0000
#define FLASHSIZE 2M
#define CACHEALIGN_SIZE 16
MEMORY
{
DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE

1
firmware/target/mips/ingenic_jz47xx/system-target.h
View file

@ -30,7 +30,6 @@
#include "system-mips.h"
#define CACHE_SIZE 16*1024
#define CACHEALIGN_BITS 5
#include "mmu-mips.h"
#define CFG_UART_BASE UART1_BASE /* Base of the UART channel */

6
lib/rbcodec/codecs/lib/codeclib.c
View file

@ -35,7 +35,7 @@ static unsigned char* mallocbuf = NULL;
int codec_init(void)
{
/* codec_get_buffer() aligns the resulting point to CACHEALIGN_SIZE. */
/* codec_get_buffer() aligns the resulting point to MEM_ALIGN_SIZE. */
mem_ptr = 0;
mallocbuf = (unsigned char *)ci->codec_get_buffer((size_t *)&bufsize);
@ -67,8 +67,8 @@ void* codec_malloc(size_t size)
x=&mallocbuf[mem_ptr];
/* Keep memory aligned to CACHEALIGN_SIZE. */
mem_ptr += (size + (CACHEALIGN_SIZE-1)) & ~(CACHEALIGN_SIZE-1);
/* Keep memory aligned to MEM_ALIGN_SIZE. */
mem_ptr += MEM_ALIGN_UP(size);
return(x);
}

4
lib/rbcodec/codecs/libtremor/oggmalloc.c
View file

@ -72,8 +72,8 @@ void iram_malloc_init(void){
void *iram_malloc(size_t size){
void* x;
/* always ensure alignment to CACHEALIGN_SIZE byte */
size = (size + (CACHEALIGN_SIZE-1)) & ~(CACHEALIGN_SIZE-1);
/* align for best performance */
size = MEM_ALIGN_UP(size);
if(size>iram_remain)
return NULL;

3
lib/rbcodec/platform.h
View file

@ -117,9 +117,6 @@ size_t strlcpy(char *dst, const char *src, size_t siz);
# define MEM_ALIGN_ATTR
#endif
#ifndef CACHEALIGN_SIZE
# define CACHEALIGN_SIZE 1
#endif
/*
#ifndef HAVE_CLIP_SAMPLE_16
static inline int32_t clip_sample_16(int32_t sample)

7
lib/rbcodec/test/warble.c
View file

@ -428,12 +428,9 @@ static void perform_config(void)
static void *ci_codec_get_buffer(size_t *size)
{
static char buffer[64 * 1024 * 1024];
char *ptr = buffer;
static char buffer[64 * 1024 * 1024] MEM_ALIGN_ATTR;
*size = sizeof(buffer);
if ((intptr_t)ptr & (CACHEALIGN_SIZE - 1))
ptr += CACHEALIGN_SIZE - ((intptr_t)ptr & (CACHEALIGN_SIZE - 1));
return ptr;
return buffer;
}
static void ci_pcmbuf_insert(const void *ch1, const void *ch2, int count)