mirror of
https://github.com/Rockbox/rockbox.git
synced 2026-04-11 16:37:45 -04:00
7eeb4e4302
Mostly motivated by PP needing CACHEALIGN_SIZE in linker scripts, which can't include system.h, so move these to cpu.h instead. Also gets rid of the default 32 byte line size that was used if the target didn't define alignment itself. RK24xx, DM320, and JZ4740 were missing this but have been confirmed (from datasheets) to use 32-byte cache lines. Add checks to make sure the macros are appropriately (un)defined based on the HAVE_CPU_CACHE_ALIGN define, and make sure their values are consistent when they are defined. Disable HAVE_CPU_CACHE_ALIGN for hosted targets since it arguably doesn't matter if there's a cache, if we aren't responsible for cache maintenance. A few files in rbcodec use CACHEALIGN_SIZE, but these can be converted to MEM_ALIGN_SIZE, which is identical to CACHEALIGN_SIZE if the latter is defined. On other targets, it aligns to at least sizeof(intptr_t). Change-Id: If8cf8f6ec327dc3732f4cd5022a858546b9e63d6
125 lines
5.2 KiB
C
125 lines
5.2 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021-2022 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __X1000_H__
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#define __X1000_H__
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#include "config.h"
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/* Frequency of external oscillator EXCLK */
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//#define X1000_EXCLK_FREQ 24000000
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/* Maximum CPU frequency that can be achieved on the target */
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//#define CPU_FREQ 1008000000
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/* Only 24 MHz and 26 MHz external oscillators are supported by the X1000 */
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#if X1000_EXCLK_FREQ == 24000000
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# define X1000_EXCLK_24MHZ
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#elif X1000_EXCLK_FREQ == 26000000
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# define X1000_EXCLK_26MHZ
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#else
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# error "Unsupported EXCLK freq"
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#endif
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/* On-chip TCSM (tightly coupled shared memory), aka IRAM. The SPL runs from
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* here, but the rest of Rockbox doesn't use it - it is too difficult to use
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* as a normal memory region because it's not in KSEG0. */
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#define X1000_TCSM_BASE 0xf4000000
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#define X1000_TCSM_SIZE (16 * 1024)
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/* SPL load and entry point addresses, this is defined by the HW boot ROM.
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* First 4K is used by mask ROM for stack + variables, and the next 2K are
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* occupied by SPL header. Usable code+data size is 10K. */
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#define X1000_SPL_LOAD_ADDR (X1000_TCSM_BASE + 0x1000)
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#define X1000_SPL_EXEC_ADDR (X1000_TCSM_BASE + 0x1800)
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#define X1000_SPL_SIZE (X1000_TCSM_SIZE - 0x1800)
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/* External SDRAM - just one big linear mapping in KSEG0. */
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#define X1000_SDRAM_BASE 0x80000000
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#define X1000_SDRAM_SIZE (MEMORYSIZE * 1024 * 1024)
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#define X1000_SDRAM_END (X1000_SDRAM_BASE + X1000_SDRAM_SIZE)
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/* Memory definitions for Rockbox
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*
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* IRAM - Contains the exception handlers and acts as a safe stub area
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* from which you can overwrite the rest of DRAM (used by RoLo).
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*
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* DRAM - This is the main RAM area used for code, data, and bss sections.
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* The audio, codec, and plugin buffers also reside in here.
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*
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* X1000_IRAM_BASE is the base of the exception vectors and must be set to
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* the base of kseg0 (0x80000000). The X1000 supports the EBase register so
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* the vectors can be remapped, allowing IRAM to be moved to any 4K-aligned
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* address, but it would introduce more complexity and there's currently no
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* good reason to do this.
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*
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* X1000_DRAM_BASE doubles as the entry point address. There is some legacy
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* baggage surrounding this value so be careful when changing it.
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*
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* - Rockbox's DRAM_BASE should always equal X1000_STANDARD_DRAM_BASE because
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* this value is hardcoded by old bootloaders released in 2021. This can be
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* changed if truly necessary, but it should be avoided.
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* - The bootloader's DRAM_BASE can be changed freely but if it isn't equal
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* to X1000_STANDARD_DRAM_BASE, the update package generation *must* be
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* updated to use the "bootloader2.ucl" filename to ensure old jztools do
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* not try to incorrectly boot the binary at the wrong load address.
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*
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* The bootloader DRAM_BASE is also hardcoded in the SPL, but the SPL is
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* considered as part of the bootloader to avoid introducing unnecessary
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* ABI boundaries. Therefore this hardcoded use can safely be ignored.
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*
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* There is no requirement that IRAM and DRAM are contiguous, but they must
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* reside in the same segment (ie. upper 3 address bits must be identical),
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* otherwise we need long calls to go between the two.
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*/
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#define X1000_IRAM_BASE X1000_SDRAM_BASE
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#define X1000_IRAM_SIZE (16 * 1024)
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#define X1000_IRAM_END (X1000_IRAM_BASE + X1000_IRAM_SIZE)
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#define X1000_DRAM_BASE X1000_IRAM_END
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#define X1000_DRAM_SIZE (X1000_SDRAM_SIZE - X1000_IRAM_SIZE)
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#define X1000_DRAM_END (X1000_DRAM_BASE + X1000_DRAM_SIZE)
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/* Stacks are placed in IRAM to avoid various annoying issues in boot code. */
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#define X1000_STACKSIZE 0x1e00
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#define X1000_IRQSTACKSIZE 0x300
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/* Standard DRAM base address for backward compatibility */
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#define X1000_STANDARD_DRAM_BASE 0x80004000
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/* Required for pcm_rec_dma_get_peak_buffer(), doesn't do anything
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* except on targets with recording. */
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#define HAVE_PCM_DMA_ADDRESS
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#define HAVE_PCM_REC_DMA_ADDRESS
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/* Convert kseg0 address to physical address or uncached address */
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#define PHYSADDR(x) ((unsigned long)(x) & 0x1fffffff)
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#define UNCACHEDADDR(x) (PHYSADDR(x) | 0xa0000000)
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/* Defines for usb-designware driver */
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#define OTGBASE 0xb3500000
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#define USB_NUM_ENDPOINTS 9
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/* CPU cache parameters */
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#define CACHEALIGN_BITS 5
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#define CACHEALIGN_SIZE 32
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#define CACHE_SIZE (16 * 1024)
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#endif /* __X1000_H__ */
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