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s5l8702: add the Nano 3G's flash controller registers

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The S5L8702 has two flash memory controllers; the BootROM uses the first
at 0x38a00000 and addresses the second at +0x400. FMC_BASE was defined
for the S5L8700 and S5L8701 only.

Also add the registers Apple's NANDReadPage (BootROM 0x20009910) uses
that are not in the existing S5L8700 set, and three FMCSTAT bits. Their
real names are unknown, so they are named for what they were observed to
do and the comments say which are inferred rather than measured.

No functional change: this header only adds definitions.

AI provenance: developed with Claude Opus 5 (Anthropic), used through
Claude Code. The model wrote most of the code and this message under
Andrew Rice's direction. Any hardware testing described above was
carried out by Andrew Rice, who is responsible for this change.

Change-Id: Ib8c808128abc9a117cb811fe1fe47bffa4ec0abe
This commit is contained in:
Andrew Rice 2026-09-12 22:41:01 +10:00 • committed by Solomon Peachy
parent dc37bb1ba0
commit 2adcfa08cf
1 changed files with 17 additions and 0 deletions
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17
firmware/export/s5l87xx.h
View file

@ -870,6 +870,9 @@
#define FMC_BASE 0x3C200000
#elif CONFIG_CPU==S5L8701
#define FMC_BASE 0x39400000
#elif CONFIG_CPU==S5L8702
/* The first of two controllers; the BootROM addresses the second at +0x400 */
#define FMC_BASE 0x38a00000
#endif
#define FMCTRL0 (*(REG32_PTR_T)(FMC_BASE + 0x0000)) /* Control Register0 */
@ -925,8 +928,19 @@
#define RSSYND3_1 (*(REG32_PTR_T)(FMC_BASE + 0x0184)) /* On-the-fly Synd Register3[63:32] */
#define RSSYND3_2 (*(REG32_PTR_T)(FMC_BASE + 0x0188)) /* On-the-fly Synd Register3[71:64] */
#define FLAGSYND (*(REG32_PTR_T)(FMC_BASE + 0x0190)) /* On-the-fly ECC Result Flag */
/* S5L8702 registers used by Apple's NANDReadPage (BootROM 0x20009910).
* The real names are unknown. */
#define FMUNK78 (*(REG32_PTR_T)(FMC_BASE + 0x0078)) /* spare decode setup, 0x5140 */
#define FMUNK7C (*(REG32_PTR_T)(FMC_BASE + 0x007C)) /* bit 1 start/busy; FMSYND5..7 */
#define FMTRANS0 (*(REG32_PTR_T)(FMC_BASE + 0x080C)) /* per-chunk ECC correction kick */
#define FMUNK810 (*(REG32_PTR_T)(FMC_BASE + 0x0810)) /* bit 0: correction failed, inferred */
#define FMTRANS1 (*(REG32_PTR_T)(FMC_BASE + 0x0814)) /* correction mode, always 0x01000180 */
#define FMTRANSSTAT (*(REG32_PTR_T)(FMC_BASE + 0x0840)) /* correction status, w1c; bit 2 done */
#define FMCTRL0_ENABLEDMA (1 << 10)
#define FMCTRL0_UNK1 (1 << 11)
#define FMCTRL0_AUTOXFER (1 << 24) /* S5L8702: write the chunk to the address in FMDATAW0 */
#define FMCTRL1_DOTRANSADDR (1 << 0)
#define FMCTRL1_DOREADDATA (1 << 1)
#define FMCTRL1_DOWRITEDATA (1 << 2)
@ -940,6 +954,9 @@
#define FMCSTAT_BANK1READY (1 << 5)
#define FMCSTAT_BANK2READY (1 << 6)
#define FMCSTAT_BANK3READY (1 << 7)
#define FMCSTAT_UNK20 (1 << 20) /* S5L8702: chunk written to memory */
#define FMCSTAT_STATUSREADY (1 << 23) /* S5L8702: set after READ STATUS; not a ready bit */
#define FMCSTAT_UNK27 (1 << 27) /* S5L8702: chunk has ECC errors (inferred) */
/* 13. SECURE DIGITAL CARD INTERFACE (SDCI) */
#if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701