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opus: ARMv4 SILK resampler interpolation
On ARMv4 the fixed-phase FIR cycles at 8, 12 and 16 kHz run as adds of shifted samples rather than multiplies: every coefficient is a constant, and a shifted add is one cycle where mla plus loading the coefficient is five or six. Each sample is loaded once per cycle and added into the two or three outputs it feeds, sharing partial products such as 31x between them, about 27 adds per output. The kernels are generated by silk/arm/gen_resampler_armv4.py. Bit-exact; OPUS_ARM_NO_SILK_ASM disables them. Measured on the e200v1, silk_5.opus (WB SILK), with the previous commit: 36.31 -> 28.85 MHz, -20.5%. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Change-Id: Ic1fd5777e91d182248f43954e4b6ae977309dc5d
This commit is contained in:
Michael Giacomelli
Solomon Peachy
parent
89e9ade855
commit
15eec82d8f
5 changed files with 673 additions and 0 deletions
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@ -21,6 +21,9 @@ Celt:
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Silk:
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* added fixed-phase interpolation paths for the 8, 12 and 16 kHz to 48 kHz
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steps in resampler_private_IIR_FIR.c (disable with OPUS_NO_SILK_FIXED_PHASE)
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* resampler_private_IIR_FIR.c calls an ARMv4 kernel for those three steps,
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silk/arm/resampler_armv4_asm.S, generated by gen_resampler_armv4.py beside
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it (disable with OPUS_ARM_NO_SILK_ASM)
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Opus-tools:
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* copied src/opus_header.h and src/opus_header.c to lib/rbcodec/codecs/libopus
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@ -16,6 +16,7 @@ celt/arm/comb_filter_armv4_asm.S
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celt/arm/denorm_armv4_asm.S
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celt/arm/deemph_armv4_asm.S
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celt/arm/exp_rotation1_armv4_asm.S
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silk/arm/resampler_armv4_asm.S
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#elif defined(CPU_ARM) && (ARM_ARCH >= 5) && (ARCH_PROFILE != ARM_PROFILE_MICRO)
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celt/arm/kiss_fft_armv5e_asm.S
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celt/arm/mdct_armv5e_asm.S
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274
lib/rbcodec/codecs/libopus/silk/arm/gen_resampler_armv4.py
Normal file
274
lib/rbcodec/codecs/libopus/silk/arm/gen_resampler_armv4.py
Normal file
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@ -0,0 +1,274 @@
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#!/usr/bin/env python3
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"""Generate silk/arm/resampler_armv4_asm.S.
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The FIR half of silk_resampler_private_IIR_FIR at 8, 12 and 16 kHz uses two
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or three fixed phase filters in a fixed cycle (see the C), so every
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coefficient is a compile-time constant. On ARM7TDMI a constant multiply is
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cheaper as shifts and adds than as mla: each add with a shifted operand is
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one cycle, where mla is 3-4 cycles plus a load of the coefficient.
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The kernel is sample-major: each input sample is loaded once per cycle and
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added into the two or three accumulators it feeds, so a partial product
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such as x*(1+2^a) can be shared between the coefficients one sample meets.
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The search below finds, per sample, the cheapest set of up to two such
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temporaries and the fewest shifted terms per coefficient.
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python3 gen_resampler_armv4.py > resampler_armv4_asm.S
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"""
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import itertools
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import random
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import sys
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from functools import lru_cache
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T = [[189, -600, 617, 30567], [117, -159, -1070, 29704],
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[52, 221, -2392, 28276], [-4, 529, -3350, 26341],
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[-48, 758, -3956, 23973], [-80, 905, -4235, 21254],
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[-99, 972, -4222, 18278], [-107, 967, -3957, 15143],
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[-103, 896, -3487, 11950], [-91, 773, -2865, 8798],
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[-71, 611, -2143, 5784], [-46, 425, -1375, 2996]]
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# The eight taps of phase p, in sample order, as the C applies them.
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P = {p: T[p] + T[11 - p][::-1] for p in range(12)}
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LIM = 1 << 17
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def csd(c):
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"""Canonical signed digits of c as (sign, shift)."""
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d, e = [], 0
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while c:
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if c & 1:
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r = 2 - (c & 3)
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d.append((r, e))
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c -= r
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c >>= 1
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e += 1
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return d
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@lru_cache(None)
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def singles(V):
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s = {}
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for v in V:
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k = 0
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while (v << k) < LIM:
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for sg in (1, -1):
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s.setdefault(sg * (v << k), (sg, v, k))
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k += 1
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return s
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@lru_cache(None)
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def doubles(V):
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s1 = singles(V)
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d = {}
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for a, b in itertools.product(s1.items(), repeat=2):
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d.setdefault(a[0] + b[0], (a[1], b[1]))
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return d
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@lru_cache(None)
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def terms(c, V):
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"""Fewest (sign, v, shift) terms, v in V, summing to c (None if > 4)."""
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s1, s2 = singles(V), doubles(V)
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if c in s1:
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return [s1[c]]
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if c in s2:
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return list(s2[c])
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for a, ta in s1.items():
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if c - a in s2:
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return [ta] + list(s2[c - a])
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for a, ta in s2.items():
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if c - a in s2:
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return list(ta) + list(s2[c - a])
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return None
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def plain(c):
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return [(sg, 1, k) for sg, k in csd(c)]
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TEMPS = sorted({(1 << a) + 1 for a in range(1, 15)} |
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{(1 << a) - 1 for a in range(2, 15)})
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def program(cs):
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"""(temps, [terms per coefficient]) with the fewest instructions."""
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best = (sum(len(csd(c)) for c in cs), (), [plain(c) for c in cs])
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for n in (1, 2):
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for ts in itertools.combinations(TEMPS, n):
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V = (1,) + ts
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tl = []
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cost = n
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for c in cs:
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t = terms(c, V)
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if t is None or len(t) > len(csd(c)):
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t = plain(c)
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tl.append(t)
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cost += len(t)
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if cost >= best[0]:
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break
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else:
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best = (cost, ts, tl)
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return best
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# Rates: step, phases in cycle order, window offset of each output, samples
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# advanced per cycle.
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RATES = [
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("16k", 43691, [0, 8, 4], [0, 0, 1], 2),
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("8k", 21846, [0, 4, 8], [0, 0, 0], 1),
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("12k", 32768, [0, 6], [0, 0], 1),
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]
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ACC = ["r3", "r4", "r5"]
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XR = ["r6", "r7"]
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TR = ["r8", "r9"]
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def gen_rate(name, step, phases, offs, adv, out):
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nsamp = max(offs) + 8
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# coefficients each sample meets, per accumulator
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need = []
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for j in range(nsamp):
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cs = []
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for o, (p, off) in enumerate(zip(phases, offs)):
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i = j - off
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if 0 <= i < 8:
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cs.append((o, P[p][i]))
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need.append(cs)
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# Process x1 .. x(n-1), then x0, whose load post-increments the pointer.
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order = list(range(1, nsamp)) + [0]
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progs = {}
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total = 0
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for j in order:
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cost, ts, tl = program(tuple(c for _, c in need[j]))
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progs[j] = (ts, tl)
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total += cost
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# Check every program arithmetically before emitting it.
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for j in order:
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ts, tl = progs[j]
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for x in (1, -1, 32767, -32768, random.randint(-32768, 32767)):
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val = {1: x}
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for t in ts:
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val[t] = x * t
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for (o, c), tt in zip(need[j], tl):
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assert sum(sg * (val[v] << k) for sg, v, k in tt) == c * x, \
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(name, j, c, tt)
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w = out.write
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fn = "silk_IIR_FIR_%s_armv4" % name
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w("\n/* %s: phases %s, %d samples a cycle, advancing %d. %d shifted"
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" adds a\n cycle, %.1f an output. */\n"
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% (name, "/".join(map(str, phases)), nsamp, adv, total,
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total / len(phases)))
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w(" .global %s\n .type %s, %%function\n%s:\n" % (fn, fn, fn))
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w(" push {r4-r11, lr}\n")
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w(" mov r10, #0x7f00\n orr r10, r10, #0xff @ 0x7fff, for the clamp\n")
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w(" mov r11, #0x4000 @ the rounding bias\n")
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w(" ldrsh %s, [r1, #2] @ x1\n" % XR[0])
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w(".L%s_loop:\n" % name)
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started = set()
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for n, j in enumerate(order):
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xr = XR[n % 2]
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ts, tl = progs[j]
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body = []
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treg = {1: xr}
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for t, r in zip(ts, TR):
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treg[t] = r
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if (t - 1) & (t - 2) == 0: # 2^a + 1
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a = (t - 1).bit_length() - 1
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body.append("add %s, %s, %s, lsl #%d" % (r, xr, xr, a))
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else: # 2^a - 1
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a = (t + 1).bit_length() - 1
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assert (1 << a) - 1 == t
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body.append("rsb %s, %s, %s, lsl #%d" % (r, xr, xr, a))
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for (o, c), tt in zip(need[j], tl):
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acc = ACC[o]
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first = len(body)
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for sg, v, k in tt:
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sh = (", lsl #%d" % k) if k else ""
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base = acc if o in started else "r11"
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started.add(o)
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body.append("%s %s, %s, %s%s" % ("add" if sg > 0 else "sub",
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acc, base, treg[v], sh))
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body[first] += " " * max(1, 34 - len(body[first])) + \
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"@ x%d * %d" % (j, c)
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# The next sample's load goes after this program's first instruction,
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# into the register the sample before this one has finished with.
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if n + 1 < len(order):
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nj = order[n + 1]
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if nj == 0:
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ld = "ldrsh %s, [r1], #%d" % (XR[(n + 1) % 2], 2 * adv)
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ld += " " * max(1, 34 - len(ld)) + "@ x0, and advance"
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else:
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ld = "ldrsh %s, [r1, #%d]" % (XR[(n + 1) % 2], 2 * nj)
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ld += " " * max(1, 34 - len(ld)) + "@ x%d" % nj
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body.insert(1, ld)
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for b in body:
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w(" " + b + "\n")
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# Clamp and store; the next cycle's x1 loads under the first clamp.
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for o in range(len(phases)):
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acc, r = ACC[o], TR[o % 2]
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w(" teq %s, %s, lsl #1 @ out of 16 bits?\n" % (acc, acc))
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if o == 0:
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w(" ldrsh %s, [r1, #2] @ next x1\n" % XR[0])
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w(" mov %s, %s, asr #15\n" % (r, acc))
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w(" eormi %s, r10, %s, asr #31\n" % (r, acc))
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w(" strh %s, [r0], #2\n" % r)
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w(" subs r2, r2, #1\n")
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w(" bne .L%s_loop\n" % name)
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w(" pop {r4-r11, pc}\n")
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w(" .size %s, .-%s\n" % (fn, fn))
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return total
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HEAD = """/* Copyright (c) 2026 Michael Giacomelli
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the conditions stated in
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* silk/resampler_private_IIR_FIR.c are met.
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*/
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/* GENERATED by silk/arm/gen_resampler_armv4.py -- edit that, not this.
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*
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* ARMv4 FIR interpolation for silk_resampler_private_IIR_FIR at the three
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* SILK rates. Each step visits two or three fixed phase filters in a fixed
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* cycle, so every coefficient is a constant, and on ARM7TDMI a constant
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* multiply is cheaper as adds of shifted operands (one cycle each) than as
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* mla (three or four, plus loading the coefficient).
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*
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* Sample-major: each input sample is loaded once a cycle and added into the
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* two or three accumulators it feeds, sharing a partial product x*(2^a+-1)
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* between them where that saves an add. The rounding bias rides in on
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* each accumulator's first add. Every sum is exact in 32 bits: the largest
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* phase has sum |c| = 50,045, so |sum| < 2^31 for 16-bit input.
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*
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* opus_int16 *silk_IIR_FIR_<rate>_armv4(opus_int16 *out,
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* const opus_int16 *buf, int cycles)
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*
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* Runs `cycles` whole cycles (cycles > 0) and returns the advanced out.
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* r0 out, r1 buf, r2 cycles, r3-r5 accumulators, r6/r7 samples, r8/r9
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* partial products, r10 0x7fff, r11 the rounding bias.
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*/
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#if defined(__thumb__) || defined(__thumb2__)
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#error "resampler_armv4_asm.S must be assembled in ARM mode"
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#endif
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.text
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.align 2
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"""
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def main():
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random.seed(1)
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out = sys.stdout
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out.write(HEAD)
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tot = {}
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for r in RATES:
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tot[r[0]] = gen_rate(*r, out=out)
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sys.stderr.write("adds per cycle: %s\n" % tot)
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if __name__ == "__main__":
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main()
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356
lib/rbcodec/codecs/libopus/silk/arm/resampler_armv4_asm.S
Normal file
356
lib/rbcodec/codecs/libopus/silk/arm/resampler_armv4_asm.S
Normal file
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@ -0,0 +1,356 @@
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/* Copyright (c) 2026 Michael Giacomelli
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the conditions stated in
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* silk/resampler_private_IIR_FIR.c are met.
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*/
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/* GENERATED by silk/arm/gen_resampler_armv4.py -- edit that, not this.
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*
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* ARMv4 FIR interpolation for silk_resampler_private_IIR_FIR at the three
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* SILK rates. Each step visits two or three fixed phase filters in a fixed
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* cycle, so every coefficient is a constant, and on ARM7TDMI a constant
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* multiply is cheaper as adds of shifted operands (one cycle each) than as
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* mla (three or four, plus loading the coefficient).
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*
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* Sample-major: each input sample is loaded once a cycle and added into the
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* two or three accumulators it feeds, sharing a partial product x*(2^a+-1)
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* between them where that saves an add. The rounding bias rides in on
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* each accumulator's first add. Every sum is exact in 32 bits: the largest
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* phase has sum |c| = 50,045, so |sum| < 2^31 for 16-bit input.
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*
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* opus_int16 *silk_IIR_FIR_<rate>_armv4(opus_int16 *out,
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* const opus_int16 *buf, int cycles)
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*
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* Runs `cycles` whole cycles (cycles > 0) and returns the advanced out.
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* r0 out, r1 buf, r2 cycles, r3-r5 accumulators, r6/r7 samples, r8/r9
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* partial products, r10 0x7fff, r11 the rounding bias.
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*/
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#if defined(__thumb__) || defined(__thumb2__)
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#error "resampler_armv4_asm.S must be assembled in ARM mode"
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#endif
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.text
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.align 2
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/* 16k: phases 0/8/4, 9 samples a cycle, advancing 2. 82 shifted adds a
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cycle, 27.3 an output. */
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.global silk_IIR_FIR_16k_armv4
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.type silk_IIR_FIR_16k_armv4, %function
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silk_IIR_FIR_16k_armv4:
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push {r4-r11, lr}
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mov r10, #0x7f00
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orr r10, r10, #0xff @ 0x7fff, for the clamp
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mov r11, #0x4000 @ the rounding bias
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ldrsh r6, [r1, #2] @ x1
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.L16k_loop:
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add r8, r6, r6, lsl #1
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ldrsh r7, [r1, #4] @ x2
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add r3, r11, r6, lsl #3 @ x1 * -600
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sub r3, r3, r6, lsl #9
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sub r3, r3, r8, lsl #5
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add r4, r11, r6, lsl #7 @ x1 * 896
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add r4, r4, r8, lsl #8
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sub r5, r11, r8, lsl #4 @ x1 * -48
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rsb r8, r7, r7, lsl #5
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ldrsh r6, [r1, #6] @ x3
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add r3, r3, r7 @ x2 * 617
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sub r3, r3, r7, lsl #2
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add r3, r3, r8, lsl #2
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add r3, r3, r8, lsl #4
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add r4, r4, r7, lsl #9 @ x2 * -3487
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sub r4, r4, r8
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sub r4, r4, r8, lsl #7
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sub r5, r5, r7, lsl #1 @ x2 * 758
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add r5, r5, r7, lsl #9
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add r5, r5, r8, lsl #3
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rsb r8, r6, r6, lsl #5
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ldrsh r7, [r1, #8] @ x4
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add r3, r3, r6, lsl #15 @ x3 * 30567
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add r3, r3, r8
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sub r3, r3, r8, lsl #3
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sub r3, r3, r8, lsl #6
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sub r4, r4, r6, lsl #4 @ x3 * 11950
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add r4, r4, r8, lsl #1
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add r4, r4, r8, lsl #7
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add r4, r4, r8, lsl #8
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add r5, r5, r6, lsl #2 @ x3 * -3956
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add r5, r5, r6, lsl #3
|
||||
sub r5, r5, r8, lsl #7
|
||||
add r8, r7, r7, lsl #1
|
||||
ldrsh r6, [r1, #10] @ x5
|
||||
rsb r9, r7, r7, lsl #6
|
||||
sub r3, r3, r7, lsl #6 @ x4 * 2996
|
||||
sub r3, r3, r8, lsl #2
|
||||
add r3, r3, r8, lsl #10
|
||||
add r4, r4, r7 @ x4 * 26341
|
||||
add r4, r4, r8, lsl #13
|
||||
sub r4, r4, r9, lsl #2
|
||||
add r4, r4, r9, lsl #5
|
||||
sub r5, r5, r8 @ x4 * 23973
|
||||
sub r5, r5, r8, lsl #5
|
||||
add r5, r5, r8, lsl #13
|
||||
sub r5, r5, r9, lsl #3
|
||||
add r8, r6, r6, lsl #1
|
||||
ldrsh r7, [r1, #12] @ x6
|
||||
add r9, r6, r6, lsl #8
|
||||
sub r3, r3, r8, lsl #5 @ x5 * -1375
|
||||
sub r3, r3, r8, lsl #9
|
||||
add r3, r3, r9
|
||||
sub r4, r4, r8, lsl #1 @ x5 * -3350
|
||||
add r4, r4, r8, lsl #8
|
||||
sub r4, r4, r9, lsl #4
|
||||
sub r5, r5, r6, lsl #10 @ x5 * 15143
|
||||
sub r5, r5, r8, lsl #3
|
||||
sub r5, r5, r9
|
||||
add r5, r5, r9, lsl #6
|
||||
add r8, r7, r7, lsl #4
|
||||
ldrsh r6, [r1, #14] @ x7
|
||||
add r3, r3, r8 @ x6 * 425
|
||||
add r3, r3, r8, lsl #3
|
||||
add r3, r3, r8, lsl #4
|
||||
add r4, r4, r7, lsl #9 @ x6 * 529
|
||||
add r4, r4, r8
|
||||
add r5, r5, r7 @ x6 * -3957
|
||||
add r5, r5, r7, lsl #1
|
||||
sub r5, r5, r7, lsl #12
|
||||
add r5, r5, r8, lsl #3
|
||||
rsb r8, r6, r6, lsl #3
|
||||
ldrsh r7, [r1, #16] @ x8
|
||||
sub r3, r3, r6, lsl #5 @ x7 * -46
|
||||
sub r3, r3, r8, lsl #1
|
||||
sub r4, r4, r6, lsl #2 @ x7 * -4
|
||||
sub r5, r5, r6 @ x7 * 967
|
||||
add r5, r5, r6, lsl #10
|
||||
sub r5, r5, r8, lsl #3
|
||||
add r5, r5, r7 @ x8 * -107
|
||||
ldrsh r6, [r1], #4 @ x0, and advance
|
||||
add r5, r5, r7, lsl #2
|
||||
add r5, r5, r7, lsl #4
|
||||
sub r5, r5, r7, lsl #7
|
||||
add r8, r6, r6, lsl #1
|
||||
sub r3, r3, r8 @ x0 * 189
|
||||
add r3, r3, r8, lsl #6
|
||||
add r4, r4, r6 @ x0 * -103
|
||||
sub r4, r4, r6, lsl #3
|
||||
sub r4, r4, r8, lsl #5
|
||||
teq r3, r3, lsl #1 @ out of 16 bits?
|
||||
ldrsh r6, [r1, #2] @ next x1
|
||||
mov r8, r3, asr #15
|
||||
eormi r8, r10, r3, asr #31
|
||||
strh r8, [r0], #2
|
||||
teq r4, r4, lsl #1 @ out of 16 bits?
|
||||
mov r9, r4, asr #15
|
||||
eormi r9, r10, r4, asr #31
|
||||
strh r9, [r0], #2
|
||||
teq r5, r5, lsl #1 @ out of 16 bits?
|
||||
mov r8, r5, asr #15
|
||||
eormi r8, r10, r5, asr #31
|
||||
strh r8, [r0], #2
|
||||
subs r2, r2, #1
|
||||
bne .L16k_loop
|
||||
pop {r4-r11, pc}
|
||||
.size silk_IIR_FIR_16k_armv4, .-silk_IIR_FIR_16k_armv4
|
||||
|
||||
/* 8k: phases 0/4/8, 8 samples a cycle, advancing 1. 79 shifted adds a
|
||||
cycle, 26.3 an output. */
|
||||
.global silk_IIR_FIR_8k_armv4
|
||||
.type silk_IIR_FIR_8k_armv4, %function
|
||||
silk_IIR_FIR_8k_armv4:
|
||||
push {r4-r11, lr}
|
||||
mov r10, #0x7f00
|
||||
orr r10, r10, #0xff @ 0x7fff, for the clamp
|
||||
mov r11, #0x4000 @ the rounding bias
|
||||
ldrsh r6, [r1, #2] @ x1
|
||||
.L8k_loop:
|
||||
add r8, r6, r6, lsl #2
|
||||
ldrsh r7, [r1, #4] @ x2
|
||||
add r3, r11, r8, lsl #3 @ x1 * -600
|
||||
sub r3, r3, r8, lsl #7
|
||||
add r4, r11, r6, lsl #7 @ x1 * 758
|
||||
sub r4, r4, r8, lsl #1
|
||||
add r4, r4, r8, lsl #7
|
||||
sub r5, r11, r6, lsl #7 @ x1 * 896
|
||||
add r5, r5, r6, lsl #10
|
||||
add r8, r7, r7, lsl #1
|
||||
ldrsh r6, [r1, #6] @ x3
|
||||
rsb r9, r7, r7, lsl #5
|
||||
sub r3, r3, r8 @ x2 * 617
|
||||
add r3, r3, r9, lsl #2
|
||||
add r3, r3, r9, lsl #4
|
||||
add r4, r4, r8, lsl #2 @ x2 * -3956
|
||||
sub r4, r4, r9, lsl #7
|
||||
add r5, r5, r7, lsl #9 @ x2 * -3487
|
||||
sub r5, r5, r9
|
||||
sub r5, r5, r9, lsl #7
|
||||
rsb r8, r6, r6, lsl #4
|
||||
ldrsh r7, [r1, #8] @ x4
|
||||
add r9, r6, r6, lsl #5
|
||||
sub r3, r3, r8, lsl #3 @ x3 * 30567
|
||||
add r3, r3, r8, lsl #11
|
||||
sub r3, r3, r9
|
||||
add r4, r4, r8, lsl #10 @ x3 * 23973
|
||||
add r4, r4, r9
|
||||
add r4, r4, r9, lsl #2
|
||||
add r4, r4, r9, lsl #8
|
||||
add r5, r5, r6, lsl #4 @ x3 * 11950
|
||||
add r5, r5, r8, lsl #1
|
||||
add r5, r5, r8, lsl #9
|
||||
add r5, r5, r9, lsl #7
|
||||
add r8, r7, r7, lsl #1
|
||||
ldrsh r6, [r1, #10] @ x5
|
||||
rsb r9, r7, r7, lsl #3
|
||||
sub r3, r3, r7, lsl #6 @ x4 * 2996
|
||||
sub r3, r3, r8, lsl #2
|
||||
add r3, r3, r8, lsl #10
|
||||
add r4, r4, r7, lsl #5 @ x4 * 15143
|
||||
add r4, r4, r8, lsl #8
|
||||
add r4, r4, r9
|
||||
add r4, r4, r9, lsl #11
|
||||
add r5, r5, r7 @ x4 * 26341
|
||||
add r5, r5, r8, lsl #13
|
||||
sub r5, r5, r9, lsl #2
|
||||
add r5, r5, r9, lsl #8
|
||||
rsb r8, r6, r6, lsl #3
|
||||
ldrsh r7, [r1, #12] @ x6
|
||||
rsb r9, r6, r6, lsl #5
|
||||
add r3, r3, r8, lsl #6 @ x5 * -1375
|
||||
sub r3, r3, r8, lsl #8
|
||||
sub r3, r3, r9
|
||||
add r4, r4, r6, lsl #2 @ x5 * -3957
|
||||
add r4, r4, r8
|
||||
sub r4, r4, r9, lsl #7
|
||||
sub r5, r5, r8, lsl #1 @ x5 * -3350
|
||||
sub r5, r5, r8, lsl #9
|
||||
add r5, r5, r9, lsl #3
|
||||
rsb r8, r7, r7, lsl #3
|
||||
ldrsh r6, [r1, #14] @ x7
|
||||
sub r3, r3, r7, lsl #4 @ x6 * 425
|
||||
sub r3, r3, r8
|
||||
add r3, r3, r8, lsl #6
|
||||
sub r4, r4, r7 @ x6 * 967
|
||||
add r4, r4, r7, lsl #10
|
||||
sub r4, r4, r8, lsl #3
|
||||
add r5, r5, r7 @ x6 * 529
|
||||
add r5, r5, r7, lsl #4
|
||||
add r5, r5, r7, lsl #9
|
||||
add r8, r6, r6, lsl #1
|
||||
ldrsh r7, [r1], #2 @ x0, and advance
|
||||
add r3, r3, r6, lsl #1 @ x7 * -46
|
||||
sub r3, r3, r8, lsl #4
|
||||
add r4, r4, r6 @ x7 * -107
|
||||
sub r4, r4, r8, lsl #2
|
||||
sub r4, r4, r8, lsl #5
|
||||
sub r5, r5, r6, lsl #2 @ x7 * -4
|
||||
add r8, r7, r7, lsl #1
|
||||
sub r3, r3, r8 @ x0 * 189
|
||||
add r3, r3, r8, lsl #6
|
||||
sub r4, r4, r8, lsl #4 @ x0 * -48
|
||||
add r5, r5, r7 @ x0 * -103
|
||||
sub r5, r5, r7, lsl #3
|
||||
sub r5, r5, r8, lsl #5
|
||||
teq r3, r3, lsl #1 @ out of 16 bits?
|
||||
ldrsh r6, [r1, #2] @ next x1
|
||||
mov r8, r3, asr #15
|
||||
eormi r8, r10, r3, asr #31
|
||||
strh r8, [r0], #2
|
||||
teq r4, r4, lsl #1 @ out of 16 bits?
|
||||
mov r9, r4, asr #15
|
||||
eormi r9, r10, r4, asr #31
|
||||
strh r9, [r0], #2
|
||||
teq r5, r5, lsl #1 @ out of 16 bits?
|
||||
mov r8, r5, asr #15
|
||||
eormi r8, r10, r5, asr #31
|
||||
strh r8, [r0], #2
|
||||
subs r2, r2, #1
|
||||
bne .L8k_loop
|
||||
pop {r4-r11, pc}
|
||||
.size silk_IIR_FIR_8k_armv4, .-silk_IIR_FIR_8k_armv4
|
||||
|
||||
/* 12k: phases 0/6, 8 samples a cycle, advancing 1. 55 shifted adds a
|
||||
cycle, 27.5 an output. */
|
||||
.global silk_IIR_FIR_12k_armv4
|
||||
.type silk_IIR_FIR_12k_armv4, %function
|
||||
silk_IIR_FIR_12k_armv4:
|
||||
push {r4-r11, lr}
|
||||
mov r10, #0x7f00
|
||||
orr r10, r10, #0xff @ 0x7fff, for the clamp
|
||||
mov r11, #0x4000 @ the rounding bias
|
||||
ldrsh r6, [r1, #2] @ x1
|
||||
.L12k_loop:
|
||||
add r8, r6, r6, lsl #2
|
||||
ldrsh r7, [r1, #4] @ x2
|
||||
add r3, r11, r8, lsl #3 @ x1 * -600
|
||||
sub r3, r3, r8, lsl #7
|
||||
sub r4, r11, r6, lsl #5 @ x1 * 972
|
||||
add r4, r4, r6, lsl #10
|
||||
sub r4, r4, r8, lsl #2
|
||||
rsb r8, r7, r7, lsl #3
|
||||
ldrsh r6, [r1, #6] @ x3
|
||||
add r3, r3, r7, lsl #9 @ x2 * 617
|
||||
sub r3, r3, r8
|
||||
add r3, r3, r8, lsl #4
|
||||
add r4, r4, r7, lsl #1 @ x2 * -4222
|
||||
sub r4, r4, r7, lsl #7
|
||||
sub r4, r4, r7, lsl #12
|
||||
add r8, r6, r6, lsl #3
|
||||
ldrsh r7, [r1, #8] @ x4
|
||||
sub r3, r3, r6, lsl #11 @ x3 * 30567
|
||||
add r3, r3, r6, lsl #15
|
||||
sub r3, r3, r8
|
||||
sub r3, r3, r8, lsl #4
|
||||
sub r4, r4, r6 @ x3 * 18278
|
||||
sub r4, r4, r8
|
||||
sub r4, r4, r8, lsl #4
|
||||
add r4, r4, r8, lsl #11
|
||||
add r8, r7, r7, lsl #1
|
||||
ldrsh r6, [r1, #10] @ x5
|
||||
sub r3, r3, r7, lsl #6 @ x4 * 2996
|
||||
sub r3, r3, r8, lsl #2
|
||||
add r3, r3, r8, lsl #10
|
||||
sub r4, r4, r7, lsl #8 @ x4 * 21254
|
||||
add r4, r4, r8, lsl #1
|
||||
sub r4, r4, r8, lsl #10
|
||||
add r4, r4, r8, lsl #13
|
||||
add r8, r6, r6, lsl #1
|
||||
ldrsh r7, [r1, #12] @ x6
|
||||
add r9, r6, r6, lsl #5
|
||||
add r3, r3, r6, lsl #7 @ x5 * -1375
|
||||
sub r3, r3, r8, lsl #9
|
||||
add r3, r3, r9
|
||||
add r4, r4, r6 @ x5 * -4235
|
||||
sub r4, r4, r8, lsl #2
|
||||
sub r4, r4, r9, lsl #7
|
||||
rsb r8, r7, r7, lsl #3
|
||||
ldrsh r6, [r1, #14] @ x7
|
||||
sub r3, r3, r7, lsl #4 @ x6 * 425
|
||||
sub r3, r3, r8
|
||||
add r3, r3, r8, lsl #6
|
||||
add r4, r4, r7 @ x6 * 905
|
||||
add r4, r4, r7, lsl #3
|
||||
add r4, r4, r8, lsl #7
|
||||
add r3, r3, r6, lsl #1 @ x7 * -46
|
||||
ldrsh r7, [r1], #2 @ x0, and advance
|
||||
add r3, r3, r6, lsl #4
|
||||
sub r3, r3, r6, lsl #6
|
||||
sub r4, r4, r6, lsl #4 @ x7 * -80
|
||||
sub r4, r4, r6, lsl #6
|
||||
add r8, r7, r7, lsl #1
|
||||
sub r3, r3, r8 @ x0 * 189
|
||||
add r3, r3, r8, lsl #6
|
||||
sub r4, r4, r8 @ x0 * -99
|
||||
sub r4, r4, r8, lsl #5
|
||||
teq r3, r3, lsl #1 @ out of 16 bits?
|
||||
ldrsh r6, [r1, #2] @ next x1
|
||||
mov r8, r3, asr #15
|
||||
eormi r8, r10, r3, asr #31
|
||||
strh r8, [r0], #2
|
||||
teq r4, r4, lsl #1 @ out of 16 bits?
|
||||
mov r9, r4, asr #15
|
||||
eormi r9, r10, r4, asr #31
|
||||
strh r9, [r0], #2
|
||||
subs r2, r2, #1
|
||||
bne .L12k_loop
|
||||
pop {r4-r11, pc}
|
||||
.size silk_IIR_FIR_12k_armv4, .-silk_IIR_FIR_12k_armv4
|
||||
|
|
@ -108,6 +108,36 @@ static OPUS_INLINE opus_int16 *silk_IIR_FIR_cycle2(
|
|||
}
|
||||
return out;
|
||||
}
|
||||
|
||||
#if defined(OPUS_ARM_ASM_ARMV4_ONLY) && !defined(OPUS_ARM_NO_SILK_ASM)
|
||||
/* The same cycles as shifts and adds of constants, in
|
||||
silk/arm/resampler_armv4_asm.S; each runs whole cycles only. */
|
||||
#define SILK_IIR_FIR_ASM
|
||||
#define SILK_IIR_FIR_16K silk_IIR_FIR_16k_armv4, 43691, 3, 1, 2
|
||||
#define SILK_IIR_FIR_8K silk_IIR_FIR_8k_armv4, 21846, 3, 1, 1
|
||||
#define SILK_IIR_FIR_12K silk_IIR_FIR_12k_armv4, 32768, 2, 1, 1
|
||||
#endif
|
||||
|
||||
#ifdef SILK_IIR_FIR_ASM
|
||||
opus_int16 *silk_IIR_FIR_16k_armv4( opus_int16 *out, const opus_int16 *buf, opus_int32 iters );
|
||||
opus_int16 *silk_IIR_FIR_8k_armv4( opus_int16 *out, const opus_int16 *buf, opus_int32 iters );
|
||||
opus_int16 *silk_IIR_FIR_12k_armv4( opus_int16 *out, const opus_int16 *buf, opus_int32 iters );
|
||||
|
||||
/* Run the kernel over every whole iteration of cyc cycles of n outputs at
|
||||
step inc, each advancing adv samples, and leave the C the rest. Cycle j
|
||||
is whole when its last output's index, (j*n + n-1)*inc, is below
|
||||
max_index_Q16. */
|
||||
#define SILK_IIR_FIR_RUN( args ) SILK_IIR_FIR_RUN_( args )
|
||||
#define SILK_IIR_FIR_RUN_( fn, inc, n, cyc, adv ) \
|
||||
do { \
|
||||
opus_int32 iters = ( max_index_Q16 + (inc) - 1 ) / ( (n) * (inc) ) / (cyc); \
|
||||
if( iters > 0 ) { \
|
||||
out = fn( out, buf, iters ); \
|
||||
buf += (adv) * iters; \
|
||||
max_index_Q16 -= iters * (cyc) * (n) * (inc); \
|
||||
} \
|
||||
} while( 0 )
|
||||
#endif
|
||||
#endif
|
||||
|
||||
static OPUS_INLINE opus_int16 *silk_resampler_private_IIR_FIR_INTERPOL(
|
||||
|
|
@ -124,10 +154,19 @@ static OPUS_INLINE opus_int16 *silk_resampler_private_IIR_FIR_INTERPOL(
|
|||
#ifndef OPUS_NO_SILK_FIXED_PHASE
|
||||
switch( index_increment_Q16 ) {
|
||||
case 43691: /* 16 kHz */
|
||||
#ifdef SILK_IIR_FIR_ASM
|
||||
SILK_IIR_FIR_RUN( SILK_IIR_FIR_16K );
|
||||
#endif
|
||||
return silk_IIR_FIR_cycle3( out, buf, max_index_Q16, 43691, 0, 8, 4, 1, 2 );
|
||||
case 21846: /* 8 kHz */
|
||||
#ifdef SILK_IIR_FIR_ASM
|
||||
SILK_IIR_FIR_RUN( SILK_IIR_FIR_8K );
|
||||
#endif
|
||||
return silk_IIR_FIR_cycle3( out, buf, max_index_Q16, 21846, 0, 4, 8, 0, 1 );
|
||||
case 32768: /* 12 kHz */
|
||||
#ifdef SILK_IIR_FIR_ASM
|
||||
SILK_IIR_FIR_RUN( SILK_IIR_FIR_12K );
|
||||
#endif
|
||||
return silk_IIR_FIR_cycle2( out, buf, max_index_Q16 );
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue