mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-07-04 11:27:16 -04:00
255b9b642b
The goal of this commit is to add the GCC/ARMClang non-MPU port variant for ARM Cortex-R82 processor which is ARMv8-R AArch64 based. The work done is inspired by the GCC ARM_AARCH64 FreeRTOS port. This port has the following features: * Uses single security state (non TrustZone). * Supports SMP (Symmetric multi-processing). * Doesn't support Hypervisor (EL2). * Doesn't support neither PMSA (MPU) nor VMSA (MMU). Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>
812 lines
31 KiB
C
812 lines
31 KiB
C
/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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* Copyright 2025 Arm Limited and/or its affiliates
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* <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/* Standard includes. */
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#include <stdlib.h>
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#include <string.h>
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
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#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. Refer to Cortex-A equivalent: /* https://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors */
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#endif
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#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
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#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. Refer to Cortex-A equivalent: /* https://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors */
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#endif
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#ifndef configUNIQUE_INTERRUPT_PRIORITIES
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#error configUNIQUE_INTERRUPT_PRIORITIES must be defined. Refer to Cortex-A equivalent: /* https://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors */
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#endif
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#ifndef configSETUP_TICK_INTERRUPT
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#error configSETUP_TICK_INTERRUPT() must be defined. Refer to Cortex-A equivalent: /* https://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors */
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#endif /* configSETUP_TICK_INTERRUPT */
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#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
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#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. Refer to Cortex-A equivalent: /* https://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors */
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#endif
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#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
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#error "configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0"
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#endif
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#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
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#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority"
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#endif
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#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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/* Check the configuration. */
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#if ( configMAX_PRIORITIES > 32 )
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#error "configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice."
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#endif
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#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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/* In case security extensions are implemented. */
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#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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#error "configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )"
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#endif
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#ifndef configCLEAR_TICK_INTERRUPT
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#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
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#endif
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#if configNUMBER_OF_CORES < 1
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#error configNUMBER_OF_CORES must be set to 1 or greater. If the application is not using multiple cores then set configNUMBER_OF_CORES to 1.
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#endif /* configNUMBER_OF_CORES < 1 */
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/* A critical section is exited when the critical section nesting count reaches
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* this value. */
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#define portNO_CRITICAL_NESTING ( ( size_t ) 0 )
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/* In all GICs 255 can be written to the priority mask register to unmask all
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* (but the lowest) interrupt priority. */
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#define portUNMASK_VALUE ( 0xFFUL )
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/* Macro to unmask all interrupt priorities. */
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#define portCLEAR_INTERRUPT_PRIORITIES_MASK() \
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{ \
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__asm volatile ( \
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"MSR DAIFSET, #2 \n" \
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"DSB SY \n" \
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"ISB SY \n" \
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"MSR ICC_PMR_EL1, %0 \n" \
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"DSB SY \n" \
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"ISB SY \n" \
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"MSR DAIFCLR, #2 \n" \
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"DSB SY \n" \
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"ISB SY \n" \
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: \
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: "r" ( portUNMASK_VALUE ) \
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); \
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}
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/* Tasks are not created with a floating point context, but can be given a
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* floating point context after they have been created. A variable is stored as
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* part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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* does not have an FPU context, or any other value if the task does have an FPU
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* context. */
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#define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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/* Constants required to setup the initial task context. */
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#define portSP_ELx ( ( StackType_t ) 0x01 )
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#define portSP_EL0 ( ( StackType_t ) 0x00 )
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#define portEL1 ( ( StackType_t ) 0x04 )
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#define portINITIAL_PSTATE ( portEL1 | portSP_EL0 )
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/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
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* point is zero. */
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#define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
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/* Masks all bits in the APSR other than the mode bits. */
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#define portAPSR_MODE_BITS_MASK ( 0x0C )
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/* The I bit in the DAIF bits. */
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#define portDAIF_I ( 0x80 )
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#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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#define portBIT_0_SET ( ( uint8_t ) 0x01 )
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/* The space on the stack required to hold the FPU registers.
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* There are 32 128-bit plus 2 64-bit status registers.*/
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#define portFPU_REGISTER_WORDS ( ( 32 * 2 ) + 2 )
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/*-----------------------------------------------------------*/
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/*
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* Starts the first task executing. This function is necessarily written in
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* assembly code so is implemented in portASM.s.
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*/
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extern void vPortRestoreTaskContext( void );
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extern void vGIC_EnableIRQ( uint32_t ulInterruptID );
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extern void vGIC_SetPriority( uint32_t ulInterruptID, uint32_t ulPriority );
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extern void vGIC_PowerUpRedistributor( void );
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extern void vGIC_EnableCPUInterface( void );
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/*-----------------------------------------------------------*/
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#if ( configNUMBER_OF_CORES == 1 )
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volatile uint64_t ullCriticalNesting = 0ULL;
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/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
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* then floating point context must be saved and restored for the task. */
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uint64_t ullPortTaskHasFPUContext = pdFALSE;
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/* Set to 1 to pend a context switch from an ISR. */
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uint64_t ullPortYieldRequired = pdFALSE;
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/* Counts the interrupt nesting depth. A context switch is only performed if
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* if the nesting depth is 0. */
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uint64_t ullPortInterruptNesting = 0;
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#else /* #if ( configNUMBER_OF_CORES == 1 ) */
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volatile uint64_t ullCriticalNestings[ configNUMBER_OF_CORES ] = { 0 };
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/* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
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* then floating point context must be saved and restored for the task. */
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uint64_t ullPortTaskHasFPUContext[ configNUMBER_OF_CORES ] = { pdFALSE };
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uint64_t ullPortYieldRequired[ configNUMBER_OF_CORES ] = { pdFALSE };
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uint64_t ullPortInterruptNestings[ configNUMBER_OF_CORES ] = { 0 };
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/* flag to control tick ISR handling, this is made true just before schedular start */
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__attribute__((section(".shared_ram")))
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uint8_t ucPortSchedulerRunning = pdFALSE;
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#endif /* #if ( configNUMBER_OF_CORES == 1 ) */
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/* Used in the ASM code. */
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__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters )
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{
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/* Setup the initial stack of the task. The stack is set exactly as
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* expected by the portRESTORE_CONTEXT() macro. */
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/* First all the general purpose registers. */
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pxTopOfStack--;
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*pxTopOfStack = 0x0101010101010101ULL; /* R1 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0303030303030303ULL; /* R3 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0202020202020202ULL; /* R2 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0505050505050505ULL; /* R5 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0404040404040404ULL; /* R4 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0707070707070707ULL; /* R7 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0606060606060606ULL; /* R6 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0909090909090909ULL; /* R9 */
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pxTopOfStack--;
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*pxTopOfStack = 0x0808080808080808ULL; /* R8 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1111111111111111ULL; /* R11 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1010101010101010ULL; /* R10 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1313131313131313ULL; /* R13 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1212121212121212ULL; /* R12 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1515151515151515ULL; /* R15 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1414141414141414ULL; /* R14 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1717171717171717ULL; /* R17 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1616161616161616ULL; /* R16 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1919191919191919ULL; /* R19 */
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pxTopOfStack--;
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*pxTopOfStack = 0x1818181818181818ULL; /* R18 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2121212121212121ULL; /* R21 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2020202020202020ULL; /* R20 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2323232323232323ULL; /* R23 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2222222222222222ULL; /* R22 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2525252525252525ULL; /* R25 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2424242424242424ULL; /* R24 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2727272727272727ULL; /* R27 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2626262626262626ULL; /* R26 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2929292929292929ULL; /* R29 */
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pxTopOfStack--;
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*pxTopOfStack = 0x2828282828282828ULL; /* R28 */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00; /* XZR - has no effect, used so there are an even number of registers. */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0x00; /* R30 - procedure call link register. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_PSTATE;
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
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#if ( configUSE_TASK_FPU_SUPPORT == portTASK_NO_FPU_CONTEXT_BY_DEFAULT )
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{
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/* The task will start with a critical nesting count of 0 as interrupts are
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* enabled. */
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pxTopOfStack--;
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*pxTopOfStack = portNO_CRITICAL_NESTING;
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/* The task will start without a floating point context. A task that
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* uses the floating point hardware must call vPortTaskUsesFPU() before
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* executing any floating point instructions. */
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pxTopOfStack--;
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*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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}
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#elif ( configUSE_TASK_FPU_SUPPORT == portTASK_HAVE_FPU_CONTEXT_BY_DEFAULT )
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{
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/* The task will start with a floating point context. Leave enough
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* space for the registers - and ensure they are initialised to 0. */
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pxTopOfStack -= portFPU_REGISTER_WORDS;
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memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
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/* The task will start with a critical nesting count of 0 as interrupts are
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* enabled. */
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pxTopOfStack--;
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*pxTopOfStack = portNO_CRITICAL_NESTING;
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pxTopOfStack--;
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*pxTopOfStack = pdTRUE;
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#if ( configNUMBER_OF_CORES == 1 )
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ullPortTaskHasFPUContext = pdTRUE;
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#else
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ullPortTaskHasFPUContext[ portGET_CORE_ID() ] = pdTRUE;
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#endif
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}
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#else /* if ( configUSE_TASK_FPU_SUPPORT == portTASK_NO_FPU_CONTEXT_BY_DEFAULT ) */
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{
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#error "Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined."
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}
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#endif /* if ( configUSE_TASK_FPU_SUPPORT == portTASK_NO_FPU_CONTEXT_BY_DEFAULT ) */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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{
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uint64_t ullAPSR;
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#if ( configASSERT_DEFINED == 1 )
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{
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if ( portGET_CORE_ID() == 0 )
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{
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volatile uint8_t ucOriginalPriority;
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volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
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volatile uint8_t ucMaxPriorityValue;
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/* Determine how many priority bits are implemented in the GIC.
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*
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* Save the interrupt priority value that is about to be clobbered. */
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ucOriginalPriority = *pucFirstUserPriorityRegister;
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/* Determine the number of priority bits available. First write to
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* all possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Read the value back to see how many bits stuck. */
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ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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/* Shift to the least significant bits. */
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while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
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{
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ucMaxPriorityValue >>= ( uint8_t ) 0x01;
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}
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/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
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* value. */
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configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
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/* Restore the clobbered interrupt priority register to its original
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* value. */
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*pucFirstUserPriorityRegister = ucOriginalPriority;
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}
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}
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#endif /* configASSERT_DEFINED */
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__asm volatile ( "MRS %0, CurrentEL" : "=r" ( ullAPSR ) );
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ullAPSR &= portAPSR_MODE_BITS_MASK;
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configASSERT( ullAPSR == portEL1 );
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/* Interrupts are turned off in the CPU itself to ensure a tick does
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* not execute while the scheduler is being started. Interrupts are
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* automatically turned back on in the CPU when the first task starts
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* executing. */
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portDISABLE_INTERRUPTS();
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#if ( configNUMBER_OF_CORES > 1 )
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if (0 == portGET_CORE_ID())
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{
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/* Start the timer that generates the tick ISR. */
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configSETUP_TICK_INTERRUPT();
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ucPortSchedulerRunning = pdTRUE;
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__asm__ volatile ("dsb sy");
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/* Start all other Cores and let them execute vPortRestoreTaskContext()*/
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__asm__ volatile ("sev");
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}
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else
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{
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portSETUP_SGI_INTERRUPT();
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}
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#else /* if ( configNUMBER_OF_CORES > 1 ) */
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/* Start the timer that generates the tick ISR. */
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configSETUP_TICK_INTERRUPT();
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#endif /* if ( configNUMBER_OF_CORES > 1 ) */
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/* Start the first task executing. */
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vPortRestoreTaskContext();
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Stub implementation for ports where there is nothing to return to
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* Artificially force an assert. */
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configASSERT( NULL );
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}
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/*-----------------------------------------------------------*/
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#if ( configNUMBER_OF_CORES == 1 )
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void vPortEnterCritical( void )
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{
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/* Mask interrupts up to the max syscall interrupt priority. */
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uxPortSetInterruptMask();
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/* Now interrupts are disabled ullCriticalNesting can be accessed
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* directly. Increment ullCriticalNesting to keep a count of how many times
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* portENTER_CRITICAL() has been called. */
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ullCriticalNesting++;
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/* This is not the interrupt safe version of the enter critical function so
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* assert() if it is being called from an interrupt context. Only API
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* functions that end in "FromISR" can be used in an interrupt. Only assert if
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* the critical nesting count is 1 to protect against recursive calls if the
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* assert function also uses a critical section. */
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if( ullCriticalNesting == 1ULL )
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{
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configASSERT( ullPortInterruptNesting == 0 );
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}
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}
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/*-----------------------------------------------------------*/
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void vPortExitCritical( void )
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{
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if( ullCriticalNesting > portNO_CRITICAL_NESTING )
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{
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/* Decrement the nesting count as the critical section is being
|
|
* exited. */
|
|
ullCriticalNesting--;
|
|
|
|
/* If the nesting level has reached zero then all interrupt
|
|
* priorities must be re-enabled. */
|
|
if( ullCriticalNesting == portNO_CRITICAL_NESTING )
|
|
{
|
|
/* Critical nesting has reached zero so all interrupt priorities
|
|
* should be unmasked. */
|
|
portCLEAR_INTERRUPT_PRIORITIES_MASK();
|
|
}
|
|
}
|
|
}
|
|
#endif /* if ( configNUMBER_OF_CORES == 1 ) */
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void FreeRTOS_Tick_Handler( void )
|
|
{
|
|
/* Must be the lowest possible priority. */
|
|
uint64_t ullRunningInterruptPriority;
|
|
__asm volatile ( "MRS %0, ICC_RPR_EL1" : "=r" ( ullRunningInterruptPriority ) );
|
|
|
|
configASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
|
|
/* Interrupts should not be enabled before this point. */
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
{
|
|
uint64_t ullMaskBits;
|
|
|
|
__asm volatile ( "mrs %0, DAIF" : "=r" ( ullMaskBits )::"memory" );
|
|
configASSERT( ( ullMaskBits & portDAIF_I ) != 0 );
|
|
}
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
/* Set interrupt mask before altering scheduler structures. The tick
|
|
* handler runs at the lowest priority, so interrupts cannot already be masked,
|
|
* so there is no need to save and restore the current mask value. It is
|
|
* necessary to turn off interrupts in the CPU itself while the ICCPMR is being
|
|
* updated. */
|
|
__asm volatile ( "MSR ICC_PMR_EL1, %0 \n"
|
|
"DSB SY \n"
|
|
"ISB SY \n"
|
|
::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
|
|
|
|
/* Ok to enable interrupts after the interrupt source has been cleared. */
|
|
configCLEAR_TICK_INTERRUPT();
|
|
portENABLE_INTERRUPTS();
|
|
|
|
#if ( configNUMBER_OF_CORES > 1 )
|
|
UBaseType_t x = portENTER_CRITICAL_FROM_ISR();
|
|
#endif /* if ( configNUMBER_OF_CORES > 1 ) */
|
|
/* Increment the RTOS tick. */
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
{
|
|
#if ( configNUMBER_OF_CORES == 1 )
|
|
ullPortYieldRequired = pdTRUE;
|
|
#else
|
|
ullPortYieldRequired[ portGET_CORE_ID() ] = pdTRUE;
|
|
#endif
|
|
}
|
|
#if ( configNUMBER_OF_CORES > 1 )
|
|
portEXIT_CRITICAL_FROM_ISR(x);
|
|
#endif /* if ( configNUMBER_OF_CORES > 1 ) */
|
|
/* Ensure all interrupt priorities are active again. */
|
|
portCLEAR_INTERRUPT_PRIORITIES_MASK();
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configUSE_TASK_FPU_SUPPORT == portTASK_NO_FPU_CONTEXT_BY_DEFAULT )
|
|
|
|
void vPortTaskUsesFPU( void )
|
|
{
|
|
/* A task is registering the fact that it needs an FPU context. Set the
|
|
* FPU flag (which is saved as part of the task context). */
|
|
#if ( configNUMBER_OF_CORES == 1 )
|
|
ullPortTaskHasFPUContext = pdTRUE;
|
|
#else
|
|
ullPortTaskHasFPUContext[ portGET_CORE_ID() ] = pdTRUE;
|
|
#endif
|
|
|
|
/* Consider initialising the FPSR here - but probably not necessary in
|
|
* AArch64. */
|
|
}
|
|
|
|
#endif /* configUSE_TASK_FPU_SUPPORT */
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
|
|
{
|
|
if( uxNewMaskValue == pdFALSE )
|
|
{
|
|
portCLEAR_INTERRUPT_PRIORITIES_MASK();
|
|
}
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
UBaseType_t uxPortSetInterruptMask( void )
|
|
{
|
|
uint32_t ulReturn;
|
|
uint64_t ullPMRValue;
|
|
|
|
/* Interrupt in the CPU must be turned off while the ICCPMR is being
|
|
* updated. */
|
|
portDISABLE_INTERRUPTS();
|
|
__asm volatile ( "MRS %0, ICC_PMR_EL1" : "=r" ( ullPMRValue ) );
|
|
|
|
if( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
|
|
{
|
|
/* Interrupts were already masked. */
|
|
ulReturn = pdTRUE;
|
|
}
|
|
else
|
|
{
|
|
ulReturn = pdFALSE;
|
|
__asm volatile ( "MSR ICC_PMR_EL1, %0 \n"
|
|
"DSB SY \n"
|
|
"ISB SY \n"
|
|
::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
|
|
}
|
|
|
|
portENABLE_INTERRUPTS();
|
|
|
|
return ulReturn;
|
|
}
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
|
|
void vPortValidateInterruptPriority( void )
|
|
{
|
|
/* The following assertion will fail if a service routine (ISR) for
|
|
* an interrupt that has been assigned a priority above
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
|
|
* function. ISR safe FreeRTOS API functions must *only* be called
|
|
* from interrupts that have been assigned a priority at or below
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
*
|
|
* Numerically low interrupt priority numbers represent logically high
|
|
* interrupt priorities, therefore the priority of the interrupt must
|
|
* be set to a value equal to or numerically *higher* than
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
*
|
|
* FreeRTOS maintains separate thread and ISR API functions to ensure
|
|
* interrupt entry is as fast and simple as possible. */
|
|
uint64_t ullRunningInterruptPriority;
|
|
__asm volatile ( "MRS %0, ICC_RPR_EL1" : "=r" ( ullRunningInterruptPriority ) );
|
|
configASSERT( ullRunningInterruptPriority >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
|
|
}
|
|
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
/*-----------------------------------------------------------*/
|
|
|
|
/*
|
|
* If the application provides an implementation of vApplicationIRQHandler(),
|
|
* then it will get called directly without saving the FPU registers on
|
|
* interrupt entry, and this weak implementation of
|
|
* vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
|
|
* it should never actually get called so its implementation contains a
|
|
* call to configASSERT() that will always fail.
|
|
*
|
|
* If the application provides its own implementation of
|
|
* vApplicationFPUSafeIRQHandler() then the implementation of
|
|
* vApplicationIRQHandler() provided in portASM.S will save the FPU registers
|
|
* before calling it.
|
|
*
|
|
* Therefore, if the application writer wants FPU registers to be saved on
|
|
* interrupt entry their IRQ handler must be called
|
|
* vApplicationFPUSafeIRQHandler(), and if the application writer does not want
|
|
* FPU registers to be saved on interrupt entry their IRQ handler must be
|
|
* called vApplicationIRQHandler().
|
|
*/
|
|
__attribute__( ( weak ) ) void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
|
|
{
|
|
( void ) ulICCIAR;
|
|
configASSERT( ( volatile void * ) NULL );
|
|
}
|
|
|
|
#if ( configNUMBER_OF_CORES > 1 )
|
|
|
|
/* Which core owns the lock */
|
|
volatile uint64_t ucOwnedByCore[ portMAX_CORE_COUNT ];
|
|
/* Lock count a core owns */
|
|
volatile uint64_t ucRecursionCountByLock[ eLockCount ];
|
|
/* Index 0 is used for ISR lock and Index 1 is used for task lock */
|
|
uint32_t ulGateWord[ eLockCount ];
|
|
|
|
void vInterruptCore(uint32_t ulInterruptID, uint32_t ulCoreID)
|
|
{
|
|
uint64_t ulRegVal = 0;
|
|
uint32_t ulCoreMask = (1UL << ulCoreID);
|
|
ulRegVal |= ( (ulCoreMask & 0xFFFF) | ( ( ulInterruptID & 0xF ) << 24U ) );
|
|
__asm__ volatile ( "msr ICC_SGI1R_EL1, %0" : : "r" ( ulRegVal ) );
|
|
__asm__ volatile ( "dsb sy");
|
|
__asm__ volatile ( "isb sy");
|
|
}
|
|
|
|
static inline void prvSpinUnlock( uint32_t * ulLock )
|
|
{
|
|
__asm volatile (
|
|
"dmb sy\n"
|
|
"mov w1, #0\n"
|
|
"str w1, [%x0]\n"
|
|
"dsb sy\n"
|
|
"sev\n"
|
|
:
|
|
: "r" ( ulLock )
|
|
: "memory", "w1"
|
|
);
|
|
}
|
|
|
|
static inline uint32_t prvSpinTrylock( uint32_t * ulLock )
|
|
{
|
|
register uint32_t ulRet;
|
|
/* Try to acquire spinlock; caller is responsible for further barriers. */
|
|
__asm volatile (
|
|
"1:\n"
|
|
"ldxr w1, [%x1]\n"
|
|
"cmp w1, #1\n"
|
|
"beq 2f\n"
|
|
"mov w2, #1\n"
|
|
"stxr w1, w2, [%x1]\n"
|
|
"cmp w1, #0\n"
|
|
"bne 1b\n"
|
|
"2:\n"
|
|
"mov %w0, w1\n"
|
|
: "=r" ( ulRet )
|
|
: "r" ( ulLock )
|
|
: "memory", "w1", "w2"
|
|
);
|
|
|
|
return ulRet;
|
|
}
|
|
|
|
/* Read 64b value shared between cores */
|
|
static inline uint64_t prvGet64( volatile uint64_t * x )
|
|
{
|
|
__asm( "dsb sy" );
|
|
return *x;
|
|
}
|
|
|
|
/* Write 64b value shared between cores */
|
|
static inline void prvSet64( volatile uint64_t * x,
|
|
uint64_t value )
|
|
{
|
|
*x = value;
|
|
__asm( "dsb sy" );
|
|
}
|
|
|
|
void vPortRecursiveLock( BaseType_t xCoreID,
|
|
ePortRTOSLock eLockNum,
|
|
BaseType_t uxAcquire )
|
|
{
|
|
/* Validate the core ID and lock number */
|
|
configASSERT( xCoreID < portMAX_CORE_COUNT );
|
|
configASSERT( eLockNum < eLockCount );
|
|
|
|
uint32_t ulLockBit = 1u << eLockNum;
|
|
|
|
/* Lock acquire */
|
|
if( uxAcquire )
|
|
{
|
|
/* Check if spinlock is available */
|
|
/* If spinlock is not available check if the core owns the lock */
|
|
/* If the core owns the lock wait increment the lock count by the core */
|
|
/* If core does not own the lock wait for the spinlock */
|
|
if( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 )
|
|
{
|
|
/* Check if the core owns the spinlock */
|
|
if( prvGet64( &ucOwnedByCore[ xCoreID ] ) & ulLockBit )
|
|
{
|
|
configASSERT( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) != 255u );
|
|
prvSet64( &ucRecursionCountByLock[ eLockNum ], ( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) + 1 ) );
|
|
return;
|
|
}
|
|
|
|
/* Preload the gate word into the cache */
|
|
uint32_t dummy = ulGateWord[ eLockNum ];
|
|
dummy++;
|
|
|
|
while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 )
|
|
{
|
|
__asm volatile ( "wfe" );
|
|
}
|
|
}
|
|
|
|
/* Add barrier to ensure lock is taken before we proceed */
|
|
__asm__ __volatile__ ( "dmb sy" ::: "memory" );
|
|
|
|
/* Assert the lock count is 0 when the spinlock is free and is acquired */
|
|
configASSERT( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) == 0 );
|
|
|
|
/* Set lock count as 1 */
|
|
prvSet64( &ucRecursionCountByLock[ eLockNum ], 1 );
|
|
/* Set ucOwnedByCore */
|
|
prvSet64( &ucOwnedByCore[ xCoreID ], ( prvGet64( &ucOwnedByCore[ xCoreID ] ) | ulLockBit ) );
|
|
}
|
|
/* Lock release */
|
|
else
|
|
{
|
|
/* Assert the lock is not free already */
|
|
configASSERT( ( prvGet64( &ucOwnedByCore[ xCoreID ] ) & ulLockBit ) != 0 );
|
|
configASSERT( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) != 0 );
|
|
|
|
/* Reduce ucRecursionCountByLock by 1 */
|
|
prvSet64( &ucRecursionCountByLock[ eLockNum ], ( prvGet64( &ucRecursionCountByLock[ eLockNum ] ) - 1 ) );
|
|
|
|
if( !prvGet64( &ucRecursionCountByLock[ eLockNum ] ) )
|
|
{
|
|
prvSet64( &ucOwnedByCore[ xCoreID ], ( prvGet64( &ucOwnedByCore[ xCoreID ] ) & ~ulLockBit ) );
|
|
prvSpinUnlock( &ulGateWord[ eLockNum ] );
|
|
/* Add barrier to ensure lock status is reflected before we proceed */
|
|
__asm__ __volatile__ ( "dmb sy" ::: "memory" );
|
|
}
|
|
}
|
|
}
|
|
|
|
BaseType_t xPortGetCoreID( void )
|
|
{
|
|
register BaseType_t xCoreID;
|
|
|
|
__asm volatile (
|
|
"mrs x0, MPIDR_EL1\n"
|
|
"and %0, x0, #0xFF\n"
|
|
: "=r" ( xCoreID )
|
|
:
|
|
: "memory", "x0"
|
|
);
|
|
|
|
return xCoreID;
|
|
}
|
|
|
|
void FreeRTOS_SGI_Handler( void )
|
|
{
|
|
/* Must be the lowest possible priority. */
|
|
uint64_t ullRunningInterruptPriority;
|
|
__asm volatile ( "MRS %0, ICC_RPR_EL1" : "=r" ( ullRunningInterruptPriority ) );
|
|
|
|
configASSERT( ullRunningInterruptPriority == ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
|
|
/* Interrupts should not be enabled before this point. */
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
{
|
|
uint64_t ullMaskBits;
|
|
|
|
__asm volatile ( "mrs %0, DAIF" : "=r" ( ullMaskBits )::"memory" );
|
|
configASSERT( ( ullMaskBits & portDAIF_I ) != 0 );
|
|
}
|
|
#endif /* configASSERT_DEFINED */
|
|
|
|
/* Set interrupt mask before altering scheduler structures. The SGI
|
|
* handler runs at the lowest priority, so interrupts cannot already be masked,
|
|
* so there is no need to save and restore the current mask value. It is
|
|
* necessary to turn off interrupts in the CPU itself while the ICCPMR is being
|
|
* updated. */
|
|
__asm volatile ( "MSR ICC_PMR_EL1, %0 \n"
|
|
"DSB SY \n"
|
|
"ISB SY \n"
|
|
::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
|
|
|
|
/* Ok to enable interrupts after the interrupt source has been cleared. */
|
|
portENABLE_INTERRUPTS();
|
|
|
|
#if ( configNUMBER_OF_CORES == 1 )
|
|
ullPortYieldRequired = pdTRUE;
|
|
#else
|
|
ullPortYieldRequired[ portGET_CORE_ID() ] = pdTRUE;
|
|
#endif
|
|
|
|
/* Ensure all interrupt priorities are active again. */
|
|
portCLEAR_INTERRUPT_PRIORITIES_MASK();
|
|
}
|
|
|
|
#endif /* if( configNUMBER_OF_CORES > 1 ) */
|