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FreeRTOS-Kernel/FreeRTOS/Demo/RISC-V_RV32_SiFive_HiFive1-RevB_IAR/README.md
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Add Vectored Interrupt Support To SiFive RISC-V Demo (#871) 
Update SiFive IAR demo to support vectored interrupts. This is a near copy of https://github.com/FreeRTOS/FreeRTOS/pull/797.

Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
Co-authored-by: Gaurav Aggarwal <aggarg@amazon.com>
2022-11-09 10:34:04 -08:00

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RISC-V SiFive HiFive1 Rev B Demo

View https://www.freertos.org/RTOS-RISC-V-FreedomStudio-IAR-HiFive-RevB.html for more information on how to run this demo