FreeRTOS-Kernel

len0rd/FreeRTOS-Kernel

Fork 0

mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-09-11 16:47:42 -04:00

Commit graph

Select branches

Hide pull requests

ci-test

main

smp

#10

#1000

#1002

#1003

#1004

#1005

#1006

#1007

#1008

#1009

#101

#1010

#1011

#1016

#1017

#1018

#102

#1020

#1021

#1022

#1023

#1024

#1025

#1026

#1027

#1028

#1029

#103

#1030

#1031

#1032

#1033

#1034

#1035

#1036

#1037

#1038

#1039

#104

#1040

#1041

#1042

#1043

#1044

#1045

#1046

#1047

#1048

#1049

#1051

#1052

#1055

#1056

#106

#1060

#1061

#1062

#1065

#1067

#1069

#1071

#1072

#1074

#1075

#1079

#108

#1080

#1081

#1082

#1083

#1084

#1085

#1088

#1089

#109

#1090

#1092

#1093

#1094

#1095

#1096

#1097

#1098

#1099

#11

#110

#1100

#1101

#1103

#1104

#1105

#1106

#1107

#1109

#1110

#1111

#1112

#1113

#1116

#1117

#1118

#1119

#112

#1122

#1123

#1124

#1125

#1127

#1129

#113

#1131

#1132

#1133

#1135

#1136

#1137

#1138

#1139

#114

#1140

#1141

#1143

#1144

#1145

#1146

#1147

#1148

#1149

#115

#1150

#1152

#1153

#1154

#1156

#1157

#1158

#1161

#1162

#1164

#1166

#1168

#1169

#117

#1170

#1174

#1175

#1176

#1177

#1178

#1179

#118

#1180

#1181

#1182

#1183

#1185

#1189

#1190

#1191

#1192

#1193

#1194

#1195

#1196

#1197

#1198

#12

#120

#1201

#1203

#1206

#1207

#1208

#1209

#121

#1211

#1212

#1214

#1215

#1216

#1218

#1219

#122

#1221

#1222

#1223

#1224

#1225

#1226

#1227

#1228

#1229

#123

#1230

#1231

#1232

#1233

#1234

#1237

#1238

#124

#1240

#1241

#1243

#1245

#1247

#1248

#1249

#125

#1250

#1251

#1253

#1254

#1255

#1256

#1257

#1258

#126

#1260

#1261

#1262

#1264

#1267

#127

#1270

#1271

#1272

#1274

#1276

#1278

#128

#1280

#1281

#1282

#1283

#1284

#1286

#1287

#1288

#1289

#129

#1290

#1291

#1292

#1294

#1297

#130

#1300

#1301

#1302

#1303

#1307

#1309

#131

#1310

#1311

#1314

#1317

#132

#133

#134

#135

#136

#137

#138

#14

#140

#141

#142

#143

#144

#145

#146

#147

#148

#149

#15

#150

#151

#152

#153

#156

#157

#158

#16

#160

#161

#162

#163

#166

#168

#169

#17

#170

#171

#172

#173

#174

#177

#178

#179

#18

#181

#182

#183

#184

#185

#186

#187

#188

#19

#190

#191

#192

#193

#194

#195

#196

#197

#198

#199

#20

#200

#201

#202

#203

#205

#206

#207

#208

#209

#21

#210

#212

#213

#214

#215

#216

#217

#219

#22

#220

#221

#223

#224

#225

#226

#227

#228

#23

#230

#231

#232

#233

#235

#236

#237

#238

#239

#24

#240

#241

#242

#243

#244

#245

#246

#248

#249

#25

#250

#253

#255

#256

#258

#259

#26

#260

#262

#263

#264

#265

#266

#267

#269

#27

#270

#271

#272

#273

#274

#275

#276

#277

#278

#279

#28

#280

#281

#282

#283

#284

#285

#286

#287

#288

#289

#29

#290

#291

#292

#293

#294

#295

#296

#298

#30

#300

#301

#302

#303

#304

#305

#306

#308

#309

#31

#310

#313

#314

#315

#317

#318

#32

#320

#321

#322

#323

#324

#325

#326

#327

#328

#329

#330

#332

#333

#334

#335

#336

#337

#338

#34

#340

#341

#342

#343

#344

#345

#346

#348

#350

#351

#352

#353

#354

#355

#356

#357

#359

#36

#360

#361

#362

#363

#364

#366

#367

#368

#369

#371

#372

#373

#374

#375

#376

#378

#38

#380

#381

#382

#384

#385

#386

#387

#388

#390

#391

#392

#393

#394

#395

#398

#399

#40

#400

#401

#402

#403

#405

#407

#408

#409

#41

#410

#411

#412

#413

#416

#417

#418

#420

#421

#422

#424

#425

#426

#427

#428

#429

#43

#430

#431

#432

#433

#434

#435

#436

#437

#438

#439

#44

#440

#441

#443

#444

#445

#446

#448

#449

#451

#452

#453

#454

#455

#456

#457

#458

#459

#46

#460

#461

#462

#463

#464

#465

#467

#469

#47

#470

#471

#472

#473

#474

#475

#478

#479

#48

#480

#481

#482

#483

#484

#485

#486

#487

#488

#489

#49

#490

#491

#493

#494

#496

#497

#498

#499

#50

#500

#501

#504

#505

#506

#507

#508

#509

#51

#512

#513

#514

#516

#517

#518

#52

#520

#521

#523

#524

#525

#528

#530

#532

#533

#535

#536

#537

#538

#539

#54

#540

#542

#543

#544

#546

#547

#548

#549

#55

#550

#552

#555

#556

#559

#56

#560

#561

#562

#563

#567

#568

#57

#570

#571

#572

#574

#575

#576

#577

#578

#579

#580

#581

#582

#583

#584

#585

#586

#587

#588

#589

#59

#590

#591

#592

#595

#596

#597

#598

#600

#601

#602

#603

#607

#608

#61

#610

#611

#613

#614

#616

#618

#619

#62

#620

#621

#624

#625

#626

#627

#629

#63

#630

#631

#633

#634

#635

#636

#637

#639

#64

#640

#641

#642

#644

#645

#649

#65

#650

#651

#652

#653

#658

#659

#660

#662

#663

#664

#665

#666

#667

#668

#669

#67

#670

#673

#674

#675

#676

#677

#679

#680

#681

#682

#683

#685

#686

#688

#689

#69

#690

#691

#692

#693

#694

#695

#696

#698

#699

#700

#702

#703

#704

#705

#706

#707

#708

#709

#71

#711

#712

#713

#715

#716

#717

#719

#72

#720

#721

#722

#723

#724

#725

#726

#727

#728

#73

#730

#732

#733

#734

#735

#736

#737

#738

#739

#741

#742

#743

#744

#745

#746

#747

#748

#749

#75

#750

#751

#754

#755

#756

#758

#759

#760

#761

#762

#763

#764

#765

#766

#768

#769

#77

#770

#771

#773

#774

#775

#776

#777

#778

#779

#78

#780

#781

#782

#783

#784

#785

#786

#787

#789

#79

#790

#791

#793

#794

#795

#796

#797

#798

#799

#80

#800

#801

#802

#803

#804

#805

#806

#807

#808

#809

#81

#810

#812

#813

#814

#815

#816

#817

#818

#819

#82

#820

#821

#822

#823

#824

#827

#828

#829

#83

#830

#831

#832

#833

#835

#836

#837

#838

#839

#84

#840

#841

#842

#843

#844

#845

#846

#847

#848

#849

#85

#850

#851

#852

#853

#855

#856

#857

#858

#859

#86

#860

#861

#862

#863

#864

#865

#866

#867

#868

#869

#87

#870

#871

#872

#873

#874

#875

#876

#877

#878

#879

#88

#880

#881

#882

#883

#884

#885

#886

#887

#888

#89

#890

#891

#893

#894

#895

#896

#897

#898

#899

#900

#901

#902

#903

#909

#910

#911

#912

#913

#914

#916

#919

#92

#920

#921

#922

#923

#924

#925

#926

#927

#931

#932

#933

#934

#935

#937

#938

#939

#94

#940

#941

#942

#943

#944

#945

#946

#947

#948

#949

#95

#950

#951

#952

#953

#954

#957

#958

#959

#96

#960

#961

#962

#963

#964

#965

#966

#967

#968

#969

#970

#971

#972

#973

#974

#975

#976

#977

#978

#979

#980

#981

#982

#983

#984

#985

#987

#988

#989

#99

#991

#992

#994

#995

#996

#998

#999

BackupPoints

PartialReleases

V10.0.0

V10.0.1

V10.1.0

V10.1.1

V10.2.0

V10.2.1

V10.3.0

V10.3.0-kernel-only

V10.3.1-kernel-only

V10.4.0-kernel-only

V10.4.1-kernel-only

V10.4.2

V10.4.3

V10.4.3-LTS-Patch-1

V10.4.3-LTS-Patch-2

V10.4.3-LTS-Patch-3

V10.4.4

V10.4.5

V10.4.6

V10.5.0

V10.5.1

V10.6.0

V10.6.1

V10.6.2

V11.0.0

V11.0.1

V11.1.0

V11.2.0

V202110.00-SMP

V4.0.1

V4.0.2

V4.0.3

V4.0.5

V4.1.0

V4.1.1

V4.1.2

V4.1.3

V4.2.0

V4.2.1

V4.3.0

V4.3.1

V4.4.0

V4.5.0

V4.6.1

V4.7.0

V4.7.1

V4.7.2

V4.8.0

V5.0.0

V5.0.2

V5.0.3

V5.1.2

V5.2.0

V5.3.0

V5.3.1

V5.4.1

V5.4.2

V6.0.0

V6.0.1

V6.0.3

V6.0.4

V6.0.5

V6.1.0

V6.1.1

V7.0.0

V7.0.1

V7.0.2

V7.1.0

V7.1.1

V7.2.0

V7.3.0

V7.4.0

V7.4.1

V7.4.2

V7.5.0

V7.5.1

V7.5.2

V7.5.3

V7.6.0

V8.0.0

V8.0.0-rc1

V8.0.0rc1

V8.0.1

V8.1.0

V8.1.1

V8.1.2

V8.2.0

V8.2.0-rc1

V8.2.0rc1

V8.2.1

V8.2.2

V8.2.3

V9.0.0

V9.0.0-rc1

V9.0.0-rc2

V9.0.0rc1

V9.0.0rc2

d2914041f8 Update the GCC and IAR SiFive HiFive rev-b demos to use the new configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS constants in place of the deprecated configCLINT_BASE_ADDRESS constant. Update the IAR RISC-V HiFive demo to use the latest IAR Embedded Workbench version. Richard Barry 2020-01-09 02:28:45 +00:00
066e2bc7d2 Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the IAR RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old. Richard Barry 2020-01-09 02:23:51 +00:00
75b81a1fab Work in progress update of LPC51U68 MCUXpresso project to rearrange the folder structure and names. Richard Barry 2020-01-09 00:19:36 +00:00
fbb23055cd Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the GCC RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old. Richard Barry 2020-01-07 01:14:36 +00:00
eaf9318df8 Add Source/portable/ARMClang file that directs users to the GCC port if they which to use the ARMClang compiler. Richard Barry 2020-01-04 00:14:18 +00:00
881958514b If tickless idle mode is in use then ensure prvResetNextTaskUnblockTime() is called after a task is unblocked due to a bit being set in an event group. This allows the MCU to re-enter sleep mode at the earliest possible time (rather than waiting until the timeout that would occur had the task not being unblocked be the event group) and matches a similar change made for queues and derivative objects (semaphores, etc.) some time ago. Richard Barry 2020-01-03 22:50:31 +00:00
853856e8cc Correct #error text in multiple fat file system files. Richard Barry 2020-01-03 20:53:27 +00:00
9e86cb95a7 Add xPortIsInsideInterrupt() to the IAR ARMv7-M ports. Richard Barry 2020-01-03 01:17:29 +00:00
be3561ed53 Added xTaskAbortDelayFromISR() and ulTaskNotifyValueClear() API functions. Added tests for xTaskAbortDelayFromISR() into Demo/Common/Minimal/AbortDelay.c. Added tests for ulTaskNotifyValueClear() into Demo/Common/Minimal/TaskNotify.c. Richard Barry 2020-01-02 18:55:20 +00:00
0a29d350b1 Renamed RISC-V_RV32_SiFive_HiFive1_IAR directory to RISC-V_RV32_SiFive_HiFive1-RevB_IAR as it targets the RevB hardware. Richard Barry 2020-01-01 22:38:23 +00:00
62b413627a Minor updates to comment block for xTaskCheckForTimeOut(). Richard Barry 2020-01-01 22:24:44 +00:00
dfc1bf8ec3 Rename RISC-V_RV32_SiFive_HiFive1-FreedomStudio directory to RISC-V_RV32_SiFive_HiFive1-RevB-FreedomStudio as it targets Rev B of the hardware. Richard Barry 2020-01-01 22:05:35 +00:00
4b943b35e0 Update RISCC-V-RV32-SiFive_HiFive1_FreedomStudio project to latest tools and metal library versions. Richard Barry 2020-01-01 22:02:06 +00:00
cfa83672ef Rename STM32Cube to GCC for STM32L4 Discovery projects as GCC is the compiler used. Gaurav Aggarwal 2020-01-01 00:35:42 +00:00
474182ab39 Make vSetupTimerInterrupt weak in the RVDS M4 MPU port to give the application writer a chance to override this function. This gives the application write ability to use a different timer. Gaurav Aggarwal 2020-01-01 00:04:10 +00:00
22dd9a55ab Update documentation of xTaskCheckForTimeOut function to reflect the intended use of this API. Gaurav Aggarwal 2019-12-31 20:49:07 +00:00
8f0eaf274c - Updates to projects due to demo folder name change. (IAR source file paths and assembler path were fixed. Keil source file paths were fixed.) - Added back power static library for GCC and IAR. (Power management related interface definitions are in drivers/fsl_power.h. power.c is empty due to "implementation is in header file and power library") - Note for GCC link: the command used for linking is arm-none-eabi-gcc -nostdlib -L<additional lib search path> -Xlinker ... -o "CORTEX_M0+_LPC51U68_LPCXpresso.axf" <all *.o> -lpower. Per GCC doc, static library name in file system is libpower.a. Yuhui.Zheng 2019-12-31 08:06:33 +00:00
3203c5cc85 Previously the STM32F0518 compiler setting was changed to enable the use of the __weak attribute - however changing the port layer to use #pragma weak in place of __weak means the compiler setting change is not required and removes the risk of introducing incompatibilities - so this check in reverts the compiler settings change. Richard Barry 2019-12-30 22:24:58 +00:00
cc673eb6a5 Ensure the CORTEX_M0_STM32F0518_IAR demo builds after updates to the Cortex-M0 port layer - required an update to the project settings to allow IAR extensions as the port layer now uses the _weak qualifier. Richard Barry 2019-12-30 22:07:33 +00:00
801e63bd10 Ensure the LPC1114 demo still builds after updates to the Cortex-M0 port layer - includes minor update to remove compiler warning that resulted from a newer compiler version. Richard Barry 2019-12-30 22:00:26 +00:00
53c98357b0 Ensure the LPC1114 demo still builds after updates to the Cortex-M0 port layer - includes minor update to remove compiler warning that resulted from a newer compiler version. Richard Barry 2019-12-30 21:59:11 +00:00
49052a6581 Ensure the XMC1000_IAR_KEIL_GCC projects still build after updates to the Cortex-M0 port layer - minor change to remove warning related to using a newer version of the IAR tools. Richard Barry 2019-12-30 21:44:22 +00:00
e292c67933 Replace the static prvSetupTimerInterrupt() function in the Cortex-M port layers that still used it (other than MPU ports so far) with a weakly defined function call vPortSetupTimerInterrupt() - which allows application writers to override the function with one that uses a different clock. Richard Barry 2019-12-30 21:16:09 +00:00
e23d638afd Correct use of xStreamBufferRead() to xStreamBufferReceive() in code comments - no source code changes. Richard Barry 2019-12-30 20:00:49 +00:00
c72df2f98d Tidy up comments only. Richard Barry 2019-12-27 21:22:07 +00:00
7ddea8fc8b Enable the Win32 comprehensive test/demo build and run when configUSE_QUEUE_SETS is set to 0. Richard Barry 2019-12-27 21:02:23 +00:00
70dbc12579 Update the LM3Sxxxx_IAR_Keil demo so the IAR project writes to the UART and executes in QEMU. Richard Barry 2019-12-27 20:59:57 +00:00
cef6548e8b Updates to CM4_MPU RCDS port Gaurav Aggarwal 2019-12-24 22:45:32 +00:00
18c3e5e02a Remove local paths from the URL files Gaurav Aggarwal 2019-12-24 19:16:19 +00:00
05adf564f6 Add readme into the third party RISC-V port that points to the directories that contains the official ports. Richard Barry 2019-12-24 17:24:23 +00:00
892baef9bd

Fix a typo in croutine.h Chih-Hsuan Yen 2019-12-23 16:49:33 +08:00
ce7e8b87d8 Add IAR MPU project for STM32L475 Discovery Kit IoT Node Gaurav Aggarwal 2019-12-21 00:04:04 +00:00
96b6746364 Updates to CM4_MPU IAR port Gaurav Aggarwal 2019-12-21 00:02:31 +00:00
b27fb82bc1 Increase test coverage for queue sets. Rename the CORTEX_M0+_LPC51U68_LPCXpresso demo to CORTEX_M0+_LPC51U68_GCC_IAR_KEIL as it supports all three compilers. Richard Barry 2019-12-20 02:54:30 +00:00
b55bbe55ac Remove build files accidentally checked in. Remove the CMSIS math library as it is large and not used. Richard Barry 2019-12-20 02:49:15 +00:00
47c666bb1e Add MPU projects for STM32L475 Discovery Kit IoT Node Gaurav Aggarwal 2019-12-20 02:07:09 +00:00
47d8ac6ac6 Updates to CM4_MPU GCC port Gaurav Aggarwal 2019-12-20 02:05:44 +00:00
24b0c90d86 Added "xPortIsInsideInterrupt" function into portmacro.h for IAR compiler and CM4F and CM7 cores. Petr Gargulak 2019-12-19 14:10:44 +01:00
c07f60c383 Adding GCC/Keil/IAR projects for NXP LPC51U68 (CM0+). Yuhui.Zheng 2019-12-18 10:06:30 +00:00
9c0e3fe9f1 Cortex M0 GCC/IAR/Keil ports -- tickless support. Yuhui.Zheng 2019-12-18 09:55:08 +00:00
3cde02a046 RVDS/Keil weak linkage for vPortSetupTimerInterrupt() -- CM4F, CM3 Yuhui.Zheng 2019-12-18 02:08:06 +00:00
d58e6a7b09 Use linker script variables for MPU setup for Nuvoton M2351 Keil Project Gaurav Aggarwal 2019-12-17 01:45:53 +00:00
d449c8979d Use the linker script variables for MPU setup for Keil Simulator Demo Gaurav Aggarwal 2019-12-17 00:14:26 +00:00
66ce9f7d72 Move warning suppression for IAR compiler to portmacro.h for v8M ports Gaurav Aggarwal 2019-12-07 01:23:17 +00:00
1deeb6dd84 Check socket binding result before doing anything with socket. (This is to address ARG findings.) Breaking the single return rule here, due to precedent violation at line 1039 and 1144. Yuhui.Zheng 2019-12-04 07:52:49 +00:00
9491af1fd7 Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to overwrite items in two queues that are part of the same set. Minor queue optimisations. Richard Barry 2019-12-03 01:50:07 +00:00
e5708b38e9 Add the Labs projects provided in the V10.2.1_191129 zip file. Richard Barry 2019-12-02 23:39:25 +00:00
46e5937529 Remove guards against __ARMCC_VERSION version numbers that were previously used to avoid compiler warnings in some GCC ARM Cortex ports. Richard Barry 2019-11-21 22:35:21 +00:00
d1fb8907ab Add software timer to the Win32 blinky demo. Richard Barry 2019-11-18 17:35:40 +00:00
07622ed3ee Remove driver files that generate compiler warnings from the RISC-V_Renode_Emulator_SoftConsole project. Update RISC-V ports so the interrupt stack is set to a known value before the scheduler is started if the interrupt stack is statically defined rather than re-using the main.c() stack. Richard Barry 2019-11-18 17:23:14 +00:00
16639d2d63 Update to the latest atomic.h. Improve commenting in RISC-V GCC port. Fix IAR RISC-V port so the first task starts with interrupts enabled. Add references to third party page ref using newlib with FreeRTOS into the tasks.c file in each place newlib is referenced. Move the position of the traceTASK_DELETE() trace macro in case of use with a memory allocator that writes over freed memory even when inside a critical section. Efficiency improvement: Make sure xTaskIncrementTick() does not return pdTRUE when the scheduler is locked. This just prevents an unnecessary yield interrupt (unnecessary as it is ignored) when xYieldPending happens to be pdTRUE. Richard Barry 2019-11-18 16:28:03 +00:00
f6393c2dbe Added quick start guide url. Carl Lundin 2019-10-29 10:24:00 -07:00
18916d5820 Rename the RISC-V_RV32_SiFive_Hifive1_GCC folder to RISC-V_RV32_SiFive_HiFive1_FreedomStudio as it is built with Freedom Studio. Richard Barry 2019-10-22 22:30:06 +00:00
5306ba245d Add nano-specs linker option to HiFive1_GCC demo. Richard Barry 2019-10-22 22:27:55 +00:00
c0741e36ed Fix spelling mistakes copied and pasted into a couple of RISC-V demo main.c files. Richard Barry 2019-10-22 16:31:57 +00:00
fccc445865 Change version and license text in RISC-V_RV32_SiFive_HiFive1_GCC FreeRTOSConfig.h file. Richard Barry 2019-10-22 02:17:15 +00:00
11c391dfb3 Tidy up main_full.c and change alignment of variable accesses in RegTest.S for the RISC-V_Renode_Emulator_SoftConsole demo. Richard Barry 2019-10-22 02:15:28 +00:00
343fbe795f Rework RISC-V QEMU example to use vanilla Eclipse in place of Freedom Studio. NOTE: RISC-V QEMU mtime interrupts are not generated consistently. Richard Barry 2019-10-22 02:03:15 +00:00
ef31243396 Add some asserts into the common demo tasks to catch scenarios where the tasks are not being used but the part of the demo/test that gets called from the tick hook is called resultant in an access to objects that were not created. Richard Barry 2019-10-21 17:17:34 +00:00
61a003088d Update RISK-V GCC port to ensure the first task starts with interrupts enabled - previously its interrupts were only enabled after it yielded for the first time. Richard Barry 2019-10-21 04:16:32 +00:00
a83244a37e Add the miv-basic.resc reNode script into the RISC-V_Renode_Emulator_SoftConsole demo as it is no longer shipped with the Microsemi tools. Richard Barry 2019-10-17 20:39:40 +00:00
c7c60cff15 Rename RISC-V-Qemu-sive_e_Freedom_Studio directory to RISC-V-Qemu-sifive_e-Eclipse-GCC as it is now using Vanilla Eclipse and vanilla GCC in place of Freedom Studio. Richard Barry 2019-10-16 04:31:57 +00:00
f78ccd077a Recreate the RISC-V-Qemu demo using Vanilla Eclipse in place of Freedom Studio as there is not a new Freedom Studio project that targets the HiFive1 board, and the updated Freedom Studio version didn't work with this project any more anyway. Richard Barry 2019-10-16 04:28:28 +00:00
d435a7b62d Move the call to traceTASK_DELETE() to before port portPRE_TASK_DELETE_HOOK() as in the Windows port portPRE_TASK_DELETE_HOOK() never returns. Richard Barry 2019-10-15 22:14:40 +00:00
4922cff4ce Add IAR demo for the SiFive RISC-V HiFive Rev B board. Richard Barry 2019-10-14 03:20:18 +00:00
f6edf4adf9 Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignment of constant loads from assembly code. Richard Barry 2019-10-14 00:16:25 +00:00
96e61a10a5 Tidy up the RISC-V_RV32_SiFive_HiFive1_GCC demo ready for its eventual release. Richard Barry 2019-10-14 00:04:53 +00:00
d4216903d9 Added the "full" demo to the RISC-V_RV32_SiFive_HiFive1_GCC demo - backup check in only as still a work in progress. Richard Barry 2019-10-13 22:53:00 +00:00
71d9450836 RIS-V_RV32_SiFive_HiFive1_GCC project now running the blinky demo - still a work in progress. Richard Barry 2019-10-11 02:59:13 +00:00
dbac79045c Formatting changes only. Richard Barry 2019-10-10 17:56:10 +00:00
dbbebbfcbc RISC-V-RV32_SiFive_HiFive1_GCC project is now also building the FreeRTOS kernel code - but not using it yet - still a work in progress. Richard Barry 2019-10-10 17:54:56 +00:00
9bb072a2ab Base project to replace existing Freedom Studio project using latest Freedom Studio project format - builds and executes but does not yet include RTOS code. Richard Barry 2019-10-09 04:50:11 +00:00
fd118f1888 Minor formatting change in comment only. Richard Barry 2019-10-07 18:56:33 +00:00
7c67f18cee Seperated Kernel from rest of FreeRTOS code base. Carl Lundin 2019-09-24 15:57:53 -07:00
eb5c60c60b Update FreeRTOS.h with the version in GitHub. This is also to test submodule. Yuhui.Zheng 2019-09-24 22:29:35 +00:00
0fe36e497d Nordic port. Notes for Richard -- the work items we discussed about for nrf52840-dk and Wiced_CY still remain. The only reason for this commit is we want to test out submodule. Yuhui.Zheng 2019-09-24 22:26:36 +00:00
35bc9d7938 Revert 2728. Not because the files are still needed, but because we want to test out submodule. Yuhui.Zheng 2019-09-24 22:19:54 +00:00
f001126ea8 Wiced_CY port is not needed anymore. Use GCC/ARM_CRx_No_GIC instead. Yuhui.Zheng 2019-09-24 20:56:55 +00:00
9052882500 Adding tickless hooks to GCC/ARM_CRx_No_GIC port. Yuhui.Zheng 2019-09-24 20:07:40 +00:00
80c1cb5de1 Correct code comments that referred to taskYIELD_FROM_ISR to portYIELD_FROM_ISR. Update RV32 port to use 16 byte-alignment all the time (only strictly necessary when using FLOP instructions). Richard Barry 2019-09-24 16:06:21 +00:00
c217b68d38 sync from github to svn: this version of atomic.h does not have compiler specific symbols. compiler specific optimization is to be merged in each port/<compiler>/<arch> directory. Yuhui.Zheng 2019-09-23 16:51:03 +00:00
6f958bbf80 sync from github to svn: Xtensa GCC as-is. Yuhui.Zheng 2019-09-20 22:09:21 +00:00
1c5fcc7f05 sync from github to svn: Wiced_CY for AFR Cypress ports. Yuhui.Zheng 2019-09-20 20:52:30 +00:00
74df636c78 sync from github to svn: documentation for RISC-V. This may be a temporary parking location. Yuhui.Zheng 2019-09-20 20:47:29 +00:00
cc0aee651e sync from github to svn: Renasas/RX100 #pragma _VECT() Yuhui.Zheng 2019-09-20 20:41:32 +00:00
da3d370ff7 RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores. Richard Barry 2019-09-04 15:46:45 +00:00
96bad0f6c3 Minor bug fix in NTPDemo.c -> use of FREERTOS_INVALID_SOCKET in place of NULL. Update trace recorder code to account for uxPendedTicks renaming to xPendedTicks. Richard Barry 2019-09-04 00:13:17 +00:00
ab41d89285 Add IAR RISC-V port to SVN - a work in progress. Richard Barry 2019-09-03 01:39:29 +00:00
2b546b1984 Atollic project update for CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC, GCC port. Yuhui Zheng 2019-08-30 00:18:41 +00:00
973a4f9869 Correct alignment of stack top in RISC-V port when configISR_STACK_SIZE_WORDS is defined to a non zero value. Richard Barry 2019-08-27 15:57:45 +00:00
7d285f3dcb + Moved the History.txt file from the website git repo into the source code SVN repo. + Added xTaskCatchUpTicks() which corrects the tick count value after the application code has held interrupts disabled for an extended period. + Updated the xTaskResumeAll() implementation so it uses the new xTaskCatchUpTicks() function mentioned above to unwind ticks that were pended while the scheduler was suspended. + Various maintenance on the message buffer, stream buffer and abort delay demos. + Change type of uxPendedTicks from UBaseType_t to TickType_t to ensure it has same type as variables it is compared to, and therefore also rename the variable xPendingTicks. + Correct spelling mistake within a comment that was common to all the ARMv7-M ports. Richard Barry 2019-08-25 19:35:59 +00:00
72af51cd86 Starting point for IAR RISC-V project created some time ago - checking in now so it can be completed - currently work in progress. Richard Barry 2019-08-04 15:24:15 +00:00
5352cb4f45 Tidy up Win32 port layer - include addition of new variable that prevents recursive attempts to obtain a mutex when the trace recorder is used inside an interrupt. Richard Barry 2019-08-04 01:14:43 +00:00
b1e35551c4 Update the FreeRTOS version number in task.h Gaurav Aggarwal 2019-07-29 23:48:11 +00:00
6bad7d2055 Add the default definition of configPRECONDITION to FreeRTOS.h. Gaurav Aggarwal 2019-07-27 23:03:23 +00:00
b7be189b4e PartialReleases Richard Barry 2019-07-25 20:23:26 +00:00
7b70a2c6bb Richard Barry 2019-07-25 20:22:39 +00:00
b4c06085e1 Files as per 190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview interim release. Richard Barry 2019-07-25 20:20:24 +00:00
b24ab46d39 Delete obsolete makefiles that were causing confusion from RISC-V-Qemu-sifive_e-FreedomStudio demo. Richard Barry 2019-07-25 20:11:37 +00:00
10b7b52995 Remove unnecessary include path from the MQTT demo. Richard Barry 2019-07-24 02:01:43 +00:00