23 commits

Author	SHA1	Message	Date
Richard Barry	c99f3c55cd	Update to V6.0.2.	2010-01-09 14:48:45 +00:00
Richard Barry	9ec30de7f4	Update Cortex M3 ports to ensure 8 byte alignment.	2009-11-15 21:47:15 +00:00
Richard Barry	26bf0da04e	Change to the file headers only.	2009-10-13 11:05:41 +00:00
Richard Barry	7f0c4ef656	Remove unnecessary use of portLONG, portCHAR and portSHORT. ... Change version number in headers.	2009-10-05 10:08:35 +00:00
Richard Barry	ed06a0400a	Update to V5.4.2. See http://www.freertos.org/History.txt .	2009-08-09 19:10:57 +00:00
Richard Barry	3a883a776c	Update to V5.4.1	2009-07-25 20:14:06 +00:00
Richard Barry	f312118bf9	Ensure LPC1768 demos are correct prior to V5.4.0 release.	2009-07-12 19:00:28 +00:00
Richard Barry	836860067f	Update version number.	2009-07-07 09:29:47 +00:00
Richard Barry	f1d6aa1a06	Prepare for V5.3.1 release.	2009-06-21 19:20:26 +00:00
Richard Barry	aad5dce4a1	Prepare for V5.3.0 release.	2009-05-30 15:59:59 +00:00
Richard Barry	2f40ad7393	Ready for V5.2.0 release.	2009-03-14 19:20:12 +00:00
Richard Barry	52ba0e651e	Update to V5.1.2.	2009-02-09 20:21:35 +00:00
Richard Barry	57e58b25af	Ready for V5.1.1 release.	2008-11-20 16:16:31 +00:00
Richard Barry	758b1c7c59	Update ready for V5.1.0 release.	2008-10-24 18:07:39 +00:00
Richard Barry	130e2f2c0a	Prepare for V5.0.4 release.	2008-09-22 15:48:40 +00:00
Richard Barry	8f33ce9c30	Use correct counter in reg test 2 task.	2008-08-14 13:59:59 +00:00
Richard Barry	5d83f61228	Documentation only.	2008-08-14 12:57:30 +00:00
Richard Barry	be92c862be	Minor mods only.	2008-08-14 11:13:34 +00:00
Richard Barry	d427489391	Tidy up.	2008-08-13 08:06:49 +00:00
Richard Barry	60da4247dd	Add interrupt nesting support, cache setup and reg test tasks.	2008-08-10 21:17:20 +00:00
Richard Barry	3a8161372d	Add serial test code (not yet complete).	2008-08-08 15:55:31 +00:00
Richard Barry	5ff84b9869	Basic demo up and running.	2008-08-08 12:47:06 +00:00
Richard Barry	78d3b371fd	Stubs ready for ColdFire V2 demo.	2008-08-07 19:13:15 +00:00